faults.cc revision 2800
16657Snate@binkert.org/* 26657Snate@binkert.org * Copyright (c) 2003-2005 The Regents of The University of Michigan 36657Snate@binkert.org * All rights reserved. 46657Snate@binkert.org * 56657Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66657Snate@binkert.org * modification, are permitted provided that the following conditions are 76657Snate@binkert.org * met: redistributions of source code must retain the above copyright 86657Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96657Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106657Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116657Snate@binkert.org * documentation and/or other materials provided with the distribution; 126657Snate@binkert.org * neither the name of the copyright holders nor the names of its 136657Snate@binkert.org * contributors may be used to endorse or promote products derived from 146657Snate@binkert.org * this software without specific prior written permission. 156657Snate@binkert.org * 166657Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176657Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186657Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196657Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206657Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216657Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226657Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236657Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246657Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256657Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266657Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276657Snate@binkert.org * 286657Snate@binkert.org * Authors: Korey Sewell 296657Snate@binkert.org */ 306657Snate@binkert.org 316657Snate@binkert.org#include "arch/mips/faults.hh" 326657Snate@binkert.org#include "cpu/thread_context.hh" 336657Snate@binkert.org#include "cpu/base.hh" 346657Snate@binkert.org#include "base/trace.hh" 356657Snate@binkert.org#if !FULL_SYSTEM 366657Snate@binkert.org#include "sim/process.hh" 376657Snate@binkert.org#include "mem/page_table.hh" 386657Snate@binkert.org#endif 396657Snate@binkert.org 406657Snate@binkert.orgnamespace MipsISA 416657Snate@binkert.org{ 426657Snate@binkert.org 436657Snate@binkert.orgFaultName MachineCheckFault::_name = "Machine Check"; 446657Snate@binkert.orgFaultVect MachineCheckFault::_vect = 0x0401; 456657Snate@binkert.orgFaultStat MachineCheckFault::_count; 466999Snate@binkert.org 476657Snate@binkert.orgFaultName AlignmentFault::_name = "Alignment"; 486657Snate@binkert.orgFaultVect AlignmentFault::_vect = 0x0301; 496657Snate@binkert.orgFaultStat AlignmentFault::_count; 506657Snate@binkert.org 519628Spowerjg@cs.wisc.eduFaultName ResetFault::_name = "reset"; 526657Snate@binkert.orgFaultVect ResetFault::_vect = 0x0001; 536657Snate@binkert.orgFaultStat ResetFault::_count; 546657Snate@binkert.org 556657Snate@binkert.orgFaultName ArithmeticFault::_name = "arith"; 566657Snate@binkert.orgFaultVect ArithmeticFault::_vect = 0x0501; 576657Snate@binkert.orgFaultStat ArithmeticFault::_count; 587839Snilay@cs.wisc.edu 596657Snate@binkert.org#if !FULL_SYSTEM 607839Snilay@cs.wisc.eduFaultName PageTableFault::_name = "page_table_fault"; 616657Snate@binkert.orgFaultVect PageTableFault::_vect = 0x0000; 626657Snate@binkert.orgFaultStat PageTableFault::_count; 636657Snate@binkert.org#endif 646657Snate@binkert.org 656657Snate@binkert.orgFaultName InterruptFault::_name = "interrupt"; 667839Snilay@cs.wisc.eduFaultVect InterruptFault::_vect = 0x0101; 676657Snate@binkert.orgFaultStat InterruptFault::_count; 687839Snilay@cs.wisc.edu 696657Snate@binkert.orgFaultName NDtbMissFault::_name = "dtb_miss_single"; 706657Snate@binkert.orgFaultVect NDtbMissFault::_vect = 0x0201; 716657Snate@binkert.orgFaultStat NDtbMissFault::_count; 726657Snate@binkert.org 736657Snate@binkert.orgFaultName PDtbMissFault::_name = "dtb_miss_double"; 746657Snate@binkert.orgFaultVect PDtbMissFault::_vect = 0x0281; 756657Snate@binkert.orgFaultStat PDtbMissFault::_count; 766657Snate@binkert.org 77FaultName DtbPageFault::_name = "dfault"; 78FaultVect DtbPageFault::_vect = 0x0381; 79FaultStat DtbPageFault::_count; 80 81FaultName DtbAcvFault::_name = "dfault"; 82FaultVect DtbAcvFault::_vect = 0x0381; 83FaultStat DtbAcvFault::_count; 84 85FaultName ItbMissFault::_name = "itbmiss"; 86FaultVect ItbMissFault::_vect = 0x0181; 87FaultStat ItbMissFault::_count; 88 89FaultName ItbPageFault::_name = "itbmiss"; 90FaultVect ItbPageFault::_vect = 0x0181; 91FaultStat ItbPageFault::_count; 92 93FaultName ItbAcvFault::_name = "iaccvio"; 94FaultVect ItbAcvFault::_vect = 0x0081; 95FaultStat ItbAcvFault::_count; 96 97FaultName UnimplementedOpcodeFault::_name = "opdec"; 98FaultVect UnimplementedOpcodeFault::_vect = 0x0481; 99FaultStat UnimplementedOpcodeFault::_count; 100 101FaultName FloatEnableFault::_name = "fen"; 102FaultVect FloatEnableFault::_vect = 0x0581; 103FaultStat FloatEnableFault::_count; 104 105FaultName PalFault::_name = "pal"; 106FaultVect PalFault::_vect = 0x2001; 107FaultStat PalFault::_count; 108 109FaultName IntegerOverflowFault::_name = "intover"; 110FaultVect IntegerOverflowFault::_vect = 0x0501; 111FaultStat IntegerOverflowFault::_count; 112 113#if FULL_SYSTEM 114 115void MipsFault::invoke(ThreadContext * tc) 116{ 117 FaultBase::invoke(tc); 118 countStat()++; 119 120 // exception restart address 121 if (setRestartAddress() || !tc->inPalMode()) 122 tc->setMiscReg(MipsISA::IPR_EXC_ADDR, tc->readPC()); 123 124 if (skipFaultingInstruction()) { 125 // traps... skip faulting instruction. 126 tc->setMiscReg(MipsISA::IPR_EXC_ADDR, 127 tc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4); 128 } 129 130 tc->setPC(tc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect()); 131 tc->setNextPC(tc->readPC() + sizeof(MachInst)); 132} 133 134void ArithmeticFault::invoke(ThreadContext * tc) 135{ 136 FaultBase::invoke(tc); 137 panic("Arithmetic traps are unimplemented!"); 138} 139 140#else //!FULL_SYSTEM 141 142void PageTableFault::invoke(ThreadContext *tc) 143{ 144 Process *p = tc->getProcessPtr(); 145 146 // address is higher than the stack region or in the current stack region 147 if (vaddr > p->stack_base || vaddr > p->stack_min) 148 FaultBase::invoke(tc); 149 150 // We've accessed the next page 151 if (vaddr > p->stack_min - PageBytes) { 152 p->stack_min -= PageBytes; 153 if (p->stack_base - p->stack_min > 8*1024*1024) 154 fatal("Over max stack size for one thread\n"); 155 p->pTable->allocate(p->stack_min, PageBytes); 156 warn("Increasing stack size by one page."); 157 } else { 158 FaultBase::invoke(tc); 159 } 160} 161 162#endif 163} // namespace MipsISA 164 165