faults.cc revision 11793
12131SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 52131SN/A * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 162131SN/A * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 295254Sksewell@umich.edu * Authors: Gabe Black 305254Sksewell@umich.edu * Korey Sewell 315222Sksewell@umich.edu * Jaidev Patwardhan 328696Sguodeyuan@tsinghua.org.cn * Zhengxing Li 338696Sguodeyuan@tsinghua.org.cn * Deyuan Guo 342131SN/A */ 352131SN/A 362239SN/A#include "arch/mips/faults.hh" 3711793Sbrandon.potter@amd.com 387676Snate@binkert.org#include "arch/mips/pra_constants.hh" 397676Snate@binkert.org#include "base/trace.hh" 407676Snate@binkert.org#include "cpu/base.hh" 412680Sktlim@umich.edu#include "cpu/thread_context.hh" 428232Snate@binkert.org#include "debug/MipsPRA.hh" 437676Snate@binkert.org#include "mem/page_table.hh" 442800Ssaidi@eecs.umich.edu#include "sim/process.hh" 452131SN/A 462447SN/Anamespace MipsISA 472447SN/A{ 482131SN/A 498566Sgblack@eecs.umich.edutypedef MipsFaultBase::FaultVals FaultVals; 502131SN/A 518578Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<SystemCallFault>::vals = 528578Sgblack@eecs.umich.edu { "Syscall", 0x180, ExcCodeSys }; 538578Sgblack@eecs.umich.edu 548578Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ReservedInstructionFault>::vals = 558578Sgblack@eecs.umich.edu { "Reserved Instruction Fault", 0x180, ExcCodeRI }; 568578Sgblack@eecs.umich.edu 578578Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ThreadFault>::vals = 588578Sgblack@eecs.umich.edu { "Thread Fault", 0x180, ExcCodeDummy }; 598578Sgblack@eecs.umich.edu 608578Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<IntegerOverflowFault>::vals = 618578Sgblack@eecs.umich.edu { "Integer Overflow Exception", 0x180, ExcCodeOv }; 628578Sgblack@eecs.umich.edu 638578Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TrapFault>::vals = 648578Sgblack@eecs.umich.edu { "Trap", 0x180, ExcCodeTr }; 658578Sgblack@eecs.umich.edu 668578Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<BreakpointFault>::vals = 678578Sgblack@eecs.umich.edu { "Breakpoint", 0x180, ExcCodeBp }; 688578Sgblack@eecs.umich.edu 698578Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<DspStateDisabledFault>::vals = 708578Sgblack@eecs.umich.edu { "DSP Disabled Fault", 0x180, ExcCodeDummy }; 718578Sgblack@eecs.umich.edu 728566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<MachineCheckFault>::vals = 738578Sgblack@eecs.umich.edu { "Machine Check", 0x180, ExcCodeMCheck }; 742447SN/A 758566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<ResetFault>::vals = 768578Sgblack@eecs.umich.edu { "Reset Fault", 0x000, ExcCodeDummy }; 778578Sgblack@eecs.umich.edu 788578Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<SoftResetFault>::vals = 798578Sgblack@eecs.umich.edu { "Soft Reset Fault", 0x000, ExcCodeDummy }; 808578Sgblack@eecs.umich.edu 818578Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<NonMaskableInterrupt>::vals = 828578Sgblack@eecs.umich.edu { "Non Maskable Interrupt", 0x000, ExcCodeDummy }; 838578Sgblack@eecs.umich.edu 848578Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<CoprocessorUnusableFault>::vals = 858578Sgblack@eecs.umich.edu { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU }; 868578Sgblack@eecs.umich.edu 878578Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<InterruptFault>::vals = 888578Sgblack@eecs.umich.edu { "Interrupt", 0x000, ExcCodeInt }; 892447SN/A 908566Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<AddressErrorFault>::vals = 918578Sgblack@eecs.umich.edu { "Address Error", 0x180, ExcCodeDummy }; 925222Sksewell@umich.edu 938573Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TlbInvalidFault>::vals = 948578Sgblack@eecs.umich.edu { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy }; 955222Sksewell@umich.edu 968573Sgblack@eecs.umich.edutemplate <> FaultVals MipsFault<TlbRefillFault>::vals = 978578Sgblack@eecs.umich.edu { "TLB Refill Exception", 0x180, ExcCodeDummy }; 982447SN/A 998737Skoansin.tan@gmail.comtemplate <> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals = 1008578Sgblack@eecs.umich.edu { "TLB Modified Exception", 0x180, ExcCodeMod }; 1014661Sksewell@umich.edu 1026378Sgblack@eecs.umich.eduvoid 1038566Sgblack@eecs.umich.eduMipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) 1045222Sksewell@umich.edu{ 1056378Sgblack@eecs.umich.edu // modify SRS Ctl - Save CSS, put ESS into CSS 1066383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscReg(MISCREG_STATUS); 1076379Sgblack@eecs.umich.edu if (status.exl != 1 && status.bev != 1) { 1086378Sgblack@eecs.umich.edu // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 1096383Sgblack@eecs.umich.edu SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); 1106379Sgblack@eecs.umich.edu srsCtl.pss = srsCtl.css; 1116379Sgblack@eecs.umich.edu srsCtl.css = srsCtl.ess; 1126383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl); 1135222Sksewell@umich.edu } 1145222Sksewell@umich.edu 1156378Sgblack@eecs.umich.edu // set EXL bit (don't care if it is already set!) 1166379Sgblack@eecs.umich.edu status.exl = 1; 1176383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_STATUS, status); 1185222Sksewell@umich.edu 1196378Sgblack@eecs.umich.edu // write EPC 1208574Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 1218574Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "PC: %s\n", pc); 1228574Sgblack@eecs.umich.edu bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc(); 1238574Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_EPC, 1248696Sguodeyuan@tsinghua.org.cn pc.pc() - (delay_slot ? sizeof(MachInst) : 0)); 1255222Sksewell@umich.edu 1266378Sgblack@eecs.umich.edu // Set Cause_EXCCODE field 1276383Sgblack@eecs.umich.edu CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 1286379Sgblack@eecs.umich.edu cause.excCode = excCode; 1298574Sgblack@eecs.umich.edu cause.bd = delay_slot ? 1 : 0; 1306379Sgblack@eecs.umich.edu cause.ce = 0; 1316383Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 1326378Sgblack@eecs.umich.edu} 1336378Sgblack@eecs.umich.edu 1346378Sgblack@eecs.umich.eduvoid 13510417Sandreas.hansson@arm.comMipsFaultBase::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1366378Sgblack@eecs.umich.edu{ 1378738Sgblack@eecs.umich.edu if (FullSystem) { 1388578Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "Fault %s encountered.\n", name()); 1398578Sgblack@eecs.umich.edu setExceptionState(tc, code()); 1408578Sgblack@eecs.umich.edu tc->pcState(vect(tc)); 1416378Sgblack@eecs.umich.edu } else { 1428578Sgblack@eecs.umich.edu panic("Fault %s encountered.\n", name()); 1436378Sgblack@eecs.umich.edu } 1446378Sgblack@eecs.umich.edu} 1456378Sgblack@eecs.umich.edu 1466378Sgblack@eecs.umich.eduvoid 14710417Sandreas.hansson@arm.comResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1484661Sksewell@umich.edu{ 1498738Sgblack@eecs.umich.edu if (FullSystem) { 1508578Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "%s encountered.\n", name()); 1518578Sgblack@eecs.umich.edu /* All reset activity must be invoked from here */ 1528578Sgblack@eecs.umich.edu Addr handler = vect(tc); 1538578Sgblack@eecs.umich.edu tc->pcState(handler); 1548578Sgblack@eecs.umich.edu DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler); 1558578Sgblack@eecs.umich.edu } 1565224Sksewell@umich.edu 1576378Sgblack@eecs.umich.edu // Set Coprocessor 1 (Floating Point) To Usable 1586383Sgblack@eecs.umich.edu StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 1596379Sgblack@eecs.umich.edu status.cu.cu1 = 1; 1606383Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_STATUS, status); 1615222Sksewell@umich.edu} 1625222Sksewell@umich.edu 1636378Sgblack@eecs.umich.eduvoid 16410417Sandreas.hansson@arm.comSoftResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1655222Sksewell@umich.edu{ 1668578Sgblack@eecs.umich.edu panic("Soft reset not implemented.\n"); 1675222Sksewell@umich.edu} 1685222Sksewell@umich.edu 1696378Sgblack@eecs.umich.eduvoid 17010417Sandreas.hansson@arm.comNonMaskableInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1715222Sksewell@umich.edu{ 1728578Sgblack@eecs.umich.edu panic("Non maskable interrupt not implemented.\n"); 1734661Sksewell@umich.edu} 1744661Sksewell@umich.edu 1752447SN/A} // namespace MipsISA 1762447SN/A 177