dsp.hh revision 5254:c555f8b07345
1/* 2 * Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved 3 * 4 * This software is part of the M5 simulator. 5 * 6 * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 7 * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 8 * TO THESE TERMS AND CONDITIONS. 9 * 10 * Permission is granted to use, copy, create derivative works and 11 * distribute this software and such derivative works for any purpose, 12 * so long as (1) the copyright notice above, this grant of permission, 13 * and the disclaimer below appear in all copies and derivative works 14 * made, (2) the copyright notice above is augmented as appropriate to 15 * reflect the addition of any new copyrightable work in a derivative 16 * work (e.g., Copyright (c) <Publication Year> Copyright Owner), and (3) 17 * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any 18 * advertising or publicity pertaining to the use or distribution of 19 * this software without specific, written prior authorization. 20 * 21 * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND 22 * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 23 * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 25 * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 26 * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 27 * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 28 * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 29 * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 30 * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 31 * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 32 * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 33 * 34 * Authors: Brett Miller 35 * 36 */ 37 38#ifndef __ARCH_MIPS_DSP_HH__ 39#define __ARCH_MIPS_DSP_HH__ 40 41#include "arch/mips/types.hh" 42#include "arch/mips/isa_traits.hh" 43#include "base/misc.hh" 44#include "config/full_system.hh" 45#include "sim/host.hh" 46 47class ThreadContext; 48 49namespace MipsISA { 50 51 // SIMD formats 52 enum { 53 SIMD_FMT_L, // long word 54 SIMD_FMT_W, // word 55 SIMD_FMT_PH, // paired halfword 56 SIMD_FMT_QB, // quad byte 57 SIMD_NUM_FMTS 58 }; 59 60 // DSPControl Fields 61 enum { 62 DSP_POS, // insertion bitfield position 63 DSP_SCOUNT, // insertion bitfield size 64 DSP_C, // carry bit 65 DSP_OUFLAG, // overflow-underflow flag 66 DSP_CCOND, // condition code 67 DSP_EFI, // extract fail indicator bit 68 DSP_NUM_FIELDS 69 }; 70 71 // compare instruction operations 72 enum { 73 CMP_EQ, // equal 74 CMP_LT, // less than 75 CMP_LE // less than or equal 76 }; 77 78 // SIMD operation order modes 79 enum { 80 MODE_L, // left 81 MODE_R, // right 82 MODE_LA, // left-alternate 83 MODE_RA, // right-alternate 84 MODE_X // cross 85 }; 86 87 // dsp operation parameters 88 enum { UNSIGNED, SIGNED }; 89 enum { NOSATURATE, SATURATE }; 90 enum { NOROUND, ROUND }; 91 92 // DSPControl field positions and masks 93 const uint32_t DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 }; 94 const uint32_t DSP_CTL_MASK[DSP_NUM_FIELDS] = { 0x0000003f, 0x00001f80, 0x00002000, 95 0x00ff0000, 0x0f000000, 0x00004000 }; 96 97 // SIMD format constants 98 const uint32_t SIMD_MAX_VALS = 4; // maximum values per register 99 const uint32_t SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 }; // number of values in fmt 100 const uint32_t SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 }; // number of bits per value 101 const uint32_t SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 }; // log2( bits per value ) 102 103 // DSP maximum values 104 const uint64_t FIXED_L_SMAX = ULL(0x7fffffffffffffff); 105 const uint64_t FIXED_W_SMAX = ULL(0x000000007fffffff); 106 const uint64_t FIXED_H_SMAX = ULL(0x0000000000007fff); 107 const uint64_t FIXED_B_SMAX = ULL(0x000000000000007f); 108 const uint64_t FIXED_L_UMAX = ULL(0xffffffffffffffff); 109 const uint64_t FIXED_W_UMAX = ULL(0x00000000ffffffff); 110 const uint64_t FIXED_H_UMAX = ULL(0x000000000000ffff); 111 const uint64_t FIXED_B_UMAX = ULL(0x00000000000000ff); 112 const uint64_t FIXED_SMAX[SIMD_NUM_FMTS] = { FIXED_L_SMAX, FIXED_W_SMAX, FIXED_H_SMAX, FIXED_B_SMAX }; 113 const uint64_t FIXED_UMAX[SIMD_NUM_FMTS] = { FIXED_L_UMAX, FIXED_W_UMAX, FIXED_H_UMAX, FIXED_B_UMAX }; 114 115 // DSP minimum values 116 const uint64_t FIXED_L_SMIN = ULL(0x8000000000000000); 117 const uint64_t FIXED_W_SMIN = ULL(0xffffffff80000000); 118 const uint64_t FIXED_H_SMIN = ULL(0xffffffffffff8000); 119 const uint64_t FIXED_B_SMIN = ULL(0xffffffffffffff80); 120 const uint64_t FIXED_L_UMIN = ULL(0x0000000000000000); 121 const uint64_t FIXED_W_UMIN = ULL(0x0000000000000000); 122 const uint64_t FIXED_H_UMIN = ULL(0x0000000000000000); 123 const uint64_t FIXED_B_UMIN = ULL(0x0000000000000000); 124 const uint64_t FIXED_SMIN[SIMD_NUM_FMTS] = { FIXED_L_SMIN, FIXED_W_SMIN, FIXED_H_SMIN, FIXED_B_SMIN }; 125 const uint64_t FIXED_UMIN[SIMD_NUM_FMTS] = { FIXED_L_UMIN, FIXED_W_UMIN, FIXED_H_UMIN, FIXED_B_UMIN }; 126 127 // DSP utility functions 128 int32_t bitrev( int32_t value ); 129 uint64_t dspSaturate( uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow ); 130 uint64_t checkOverflow( uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow ); 131 uint64_t signExtend( uint64_t value, int32_t signpos ); 132 uint64_t addHalfLsb( uint64_t value, int32_t lsbpos ); 133 int32_t dspAbs( int32_t a, int32_t fmt, uint32_t *dspctl ); 134 int32_t dspAdd( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl ); 135 int32_t dspAddh( int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign ); 136 int32_t dspSub( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl ); 137 int32_t dspSubh( int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign ); 138 int32_t dspShll( int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl ); 139 int32_t dspShrl( int32_t a, uint32_t sa, int32_t fmt, int32_t sign ); 140 int32_t dspShra( int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl ); 141 int32_t dspMul( int32_t a, int32_t b, int32_t fmt, int32_t saturate, uint32_t *dspctl ); 142 int32_t dspMulq( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl ); 143 int32_t dspMuleu( int32_t a, int32_t b, int32_t mode, uint32_t *dspctl ); 144 int32_t dspMuleq( int32_t a, int32_t b, int32_t mode, uint32_t *dspctl ); 145 int64_t dspDpaq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, 146 int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl ); 147 int64_t dspDpsq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, 148 int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl ); 149 int64_t dspDpa( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode ); 150 int64_t dspDps( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode ); 151 int64_t dspMaq( int64_t dspac, int32_t a, int32_t b, int32_t ac, 152 int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl ); 153 int64_t dspMulsa( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt ); 154 int64_t dspMulsaq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, uint32_t *dspctl ); 155 void dspCmp( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl ); 156 int32_t dspCmpg( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op ); 157 int32_t dspCmpgd( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl ); 158 int32_t dspPrece( int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode ); 159 int32_t dspPrecrqu( int32_t a, int32_t b, uint32_t *dspctl ); 160 int32_t dspPrecrq( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl ); 161 int32_t dspPrecrSra( int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round ); 162 int32_t dspPick( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl ); 163 int32_t dspPack( int32_t a, int32_t b, int32_t fmt ); 164 int32_t dspExtr( int64_t dspac, int32_t fmt, int32_t sa, int32_t round, 165 int32_t saturate, uint32_t *dspctl ); 166 int32_t dspExtp( int64_t dspac, int32_t size, uint32_t *dspctl ); 167 int32_t dspExtpd( int64_t dspac, int32_t size, uint32_t *dspctl ); 168 169 // SIMD pack/unpack utility functions 170 void simdPack( uint64_t *values_ptr, int32_t *reg, int32_t fmt ); 171 void simdUnpack( int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign ); 172 173 // DSPControl r/w utility functions 174 void writeDSPControl( uint32_t *dspctl, uint32_t value, uint32_t mask ); 175 uint32_t readDSPControl( uint32_t *dspctl, uint32_t mask ); 176}; 177 178#endif 179