dsp.hh revision 4661
14661Sksewell@umich.edu/* 24661Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 34661Sksewell@umich.edu * All rights reserved. 44661Sksewell@umich.edu * 54661Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 64661Sksewell@umich.edu * modification, are permitted provided that the following conditions are 74661Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 84661Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 94661Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 104661Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 114661Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 124661Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 134661Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 144661Sksewell@umich.edu * this software without specific prior written permission. 154661Sksewell@umich.edu * 164661Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174661Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184661Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194661Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204661Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214661Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224661Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234661Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244661Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254661Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264661Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274661Sksewell@umich.edu * 284661Sksewell@umich.edu * Authors: Brett Miller 294661Sksewell@umich.edu */ 304661Sksewell@umich.edu 314661Sksewell@umich.edu#ifndef __ARCH_MIPS_DSP_HH__ 324661Sksewell@umich.edu#define __ARCH_MIPS_DSP_HH__ 334661Sksewell@umich.edu 344661Sksewell@umich.edu#include "arch/mips/types.hh" 354661Sksewell@umich.edu#include "arch/mips/isa_traits.hh" 364661Sksewell@umich.edu#include "base/misc.hh" 374661Sksewell@umich.edu#include "config/full_system.hh" 384661Sksewell@umich.edu#include "sim/host.hh" 394661Sksewell@umich.edu 404661Sksewell@umich.educlass ThreadContext; 414661Sksewell@umich.edu 424661Sksewell@umich.edunamespace MipsISA { 434661Sksewell@umich.edu 444661Sksewell@umich.edu // SIMD formats 454661Sksewell@umich.edu enum { 464661Sksewell@umich.edu SIMD_FMT_L, // long word 474661Sksewell@umich.edu SIMD_FMT_W, // word 484661Sksewell@umich.edu SIMD_FMT_PH, // paired halfword 494661Sksewell@umich.edu SIMD_FMT_QB, // quad byte 504661Sksewell@umich.edu SIMD_NUM_FMTS 514661Sksewell@umich.edu }; 524661Sksewell@umich.edu 534661Sksewell@umich.edu // DSPControl Fields 544661Sksewell@umich.edu enum { 554661Sksewell@umich.edu DSP_POS, // insertion bitfield position 564661Sksewell@umich.edu DSP_SCOUNT, // insertion bitfield size 574661Sksewell@umich.edu DSP_C, // carry bit 584661Sksewell@umich.edu DSP_OUFLAG, // overflow-underflow flag 594661Sksewell@umich.edu DSP_CCOND, // condition code 604661Sksewell@umich.edu DSP_EFI, // extract fail indicator bit 614661Sksewell@umich.edu DSP_NUM_FIELDS 624661Sksewell@umich.edu }; 634661Sksewell@umich.edu 644661Sksewell@umich.edu // compare instruction operations 654661Sksewell@umich.edu enum { 664661Sksewell@umich.edu CMP_EQ, // equal 674661Sksewell@umich.edu CMP_LT, // less than 684661Sksewell@umich.edu CMP_LE // less than or equal 694661Sksewell@umich.edu }; 704661Sksewell@umich.edu 714661Sksewell@umich.edu // SIMD operation order modes 724661Sksewell@umich.edu enum { 734661Sksewell@umich.edu MODE_L, // left 744661Sksewell@umich.edu MODE_R, // right 754661Sksewell@umich.edu MODE_LA, // left-alternate 764661Sksewell@umich.edu MODE_RA, // right-alternate 774661Sksewell@umich.edu MODE_X // cross 784661Sksewell@umich.edu }; 794661Sksewell@umich.edu 804661Sksewell@umich.edu // dsp operation parameters 814661Sksewell@umich.edu enum { UNSIGNED, SIGNED }; 824661Sksewell@umich.edu enum { NOSATURATE, SATURATE }; 834661Sksewell@umich.edu enum { NOROUND, ROUND }; 844661Sksewell@umich.edu 854661Sksewell@umich.edu // DSPControl field positions and masks 864661Sksewell@umich.edu const uint32_t DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 }; 874661Sksewell@umich.edu const uint32_t DSP_CTL_MASK[DSP_NUM_FIELDS] = { 0x0000003f, 0x00001f80, 0x00002000, 884661Sksewell@umich.edu 0x00ff0000, 0x0f000000, 0x00004000 }; 894661Sksewell@umich.edu 904661Sksewell@umich.edu // SIMD format constants 914661Sksewell@umich.edu const uint32_t SIMD_MAX_VALS = 4; // maximum values per register 924661Sksewell@umich.edu const uint32_t SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 }; // number of values in fmt 934661Sksewell@umich.edu const uint32_t SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 }; // number of bits per value 944661Sksewell@umich.edu const uint32_t SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 }; // log2( bits per value ) 954661Sksewell@umich.edu 964661Sksewell@umich.edu // DSP maximum values 974661Sksewell@umich.edu const uint64_t FIXED_L_SMAX = ULL(0x7fffffffffffffff); 984661Sksewell@umich.edu const uint64_t FIXED_W_SMAX = ULL(0x000000007fffffff); 994661Sksewell@umich.edu const uint64_t FIXED_H_SMAX = ULL(0x0000000000007fff); 1004661Sksewell@umich.edu const uint64_t FIXED_B_SMAX = ULL(0x000000000000007f); 1014661Sksewell@umich.edu const uint64_t FIXED_L_UMAX = ULL(0xffffffffffffffff); 1024661Sksewell@umich.edu const uint64_t FIXED_W_UMAX = ULL(0x00000000ffffffff); 1034661Sksewell@umich.edu const uint64_t FIXED_H_UMAX = ULL(0x000000000000ffff); 1044661Sksewell@umich.edu const uint64_t FIXED_B_UMAX = ULL(0x00000000000000ff); 1054661Sksewell@umich.edu const uint64_t FIXED_SMAX[SIMD_NUM_FMTS] = { FIXED_L_SMAX, FIXED_W_SMAX, FIXED_H_SMAX, FIXED_B_SMAX }; 1064661Sksewell@umich.edu const uint64_t FIXED_UMAX[SIMD_NUM_FMTS] = { FIXED_L_UMAX, FIXED_W_UMAX, FIXED_H_UMAX, FIXED_B_UMAX }; 1074661Sksewell@umich.edu 1084661Sksewell@umich.edu // DSP minimum values 1094661Sksewell@umich.edu const uint64_t FIXED_L_SMIN = ULL(0x8000000000000000); 1104661Sksewell@umich.edu const uint64_t FIXED_W_SMIN = ULL(0xffffffff80000000); 1114661Sksewell@umich.edu const uint64_t FIXED_H_SMIN = ULL(0xffffffffffff8000); 1124661Sksewell@umich.edu const uint64_t FIXED_B_SMIN = ULL(0xffffffffffffff80); 1134661Sksewell@umich.edu const uint64_t FIXED_L_UMIN = ULL(0x0000000000000000); 1144661Sksewell@umich.edu const uint64_t FIXED_W_UMIN = ULL(0x0000000000000000); 1154661Sksewell@umich.edu const uint64_t FIXED_H_UMIN = ULL(0x0000000000000000); 1164661Sksewell@umich.edu const uint64_t FIXED_B_UMIN = ULL(0x0000000000000000); 1174661Sksewell@umich.edu const uint64_t FIXED_SMIN[SIMD_NUM_FMTS] = { FIXED_L_SMIN, FIXED_W_SMIN, FIXED_H_SMIN, FIXED_B_SMIN }; 1184661Sksewell@umich.edu const uint64_t FIXED_UMIN[SIMD_NUM_FMTS] = { FIXED_L_UMIN, FIXED_W_UMIN, FIXED_H_UMIN, FIXED_B_UMIN }; 1194661Sksewell@umich.edu 1204661Sksewell@umich.edu // DSP utility functions 1214661Sksewell@umich.edu int32_t bitrev( int32_t value ); 1224661Sksewell@umich.edu uint64_t dspSaturate( uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow ); 1234661Sksewell@umich.edu uint64_t checkOverflow( uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow ); 1244661Sksewell@umich.edu uint64_t signExtend( uint64_t value, int32_t signpos ); 1254661Sksewell@umich.edu uint64_t addHalfLsb( uint64_t value, int32_t lsbpos ); 1264661Sksewell@umich.edu int32_t dspAbs( int32_t a, int32_t fmt, uint32_t *dspctl ); 1274661Sksewell@umich.edu int32_t dspAdd( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl ); 1284661Sksewell@umich.edu int32_t dspAddh( int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign ); 1294661Sksewell@umich.edu int32_t dspSub( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl ); 1304661Sksewell@umich.edu int32_t dspSubh( int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign ); 1314661Sksewell@umich.edu int32_t dspShll( int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl ); 1324661Sksewell@umich.edu int32_t dspShrl( int32_t a, uint32_t sa, int32_t fmt, int32_t sign ); 1334661Sksewell@umich.edu int32_t dspShra( int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl ); 1344661Sksewell@umich.edu int32_t dspMul( int32_t a, int32_t b, int32_t fmt, int32_t saturate, uint32_t *dspctl ); 1354661Sksewell@umich.edu int32_t dspMulq( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl ); 1364661Sksewell@umich.edu int32_t dspMuleu( int32_t a, int32_t b, int32_t mode, uint32_t *dspctl ); 1374661Sksewell@umich.edu int32_t dspMuleq( int32_t a, int32_t b, int32_t mode, uint32_t *dspctl ); 1384661Sksewell@umich.edu int64_t dspDpaq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, 1394661Sksewell@umich.edu int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl ); 1404661Sksewell@umich.edu int64_t dspDpsq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, 1414661Sksewell@umich.edu int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl ); 1424661Sksewell@umich.edu int64_t dspDpa( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode ); 1434661Sksewell@umich.edu int64_t dspDps( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode ); 1444661Sksewell@umich.edu int64_t dspMaq( int64_t dspac, int32_t a, int32_t b, int32_t ac, 1454661Sksewell@umich.edu int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl ); 1464661Sksewell@umich.edu int64_t dspMulsa( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt ); 1474661Sksewell@umich.edu int64_t dspMulsaq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, uint32_t *dspctl ); 1484661Sksewell@umich.edu void dspCmp( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl ); 1494661Sksewell@umich.edu int32_t dspCmpg( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op ); 1504661Sksewell@umich.edu int32_t dspCmpgd( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl ); 1514661Sksewell@umich.edu int32_t dspPrece( int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode ); 1524661Sksewell@umich.edu int32_t dspPrecrqu( int32_t a, int32_t b, uint32_t *dspctl ); 1534661Sksewell@umich.edu int32_t dspPrecrq( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl ); 1544661Sksewell@umich.edu int32_t dspPrecrSra( int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round ); 1554661Sksewell@umich.edu int32_t dspPick( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl ); 1564661Sksewell@umich.edu int32_t dspPack( int32_t a, int32_t b, int32_t fmt ); 1574661Sksewell@umich.edu int32_t dspExtr( int64_t dspac, int32_t fmt, int32_t sa, int32_t round, 1584661Sksewell@umich.edu int32_t saturate, uint32_t *dspctl ); 1594661Sksewell@umich.edu int32_t dspExtp( int64_t dspac, int32_t size, uint32_t *dspctl ); 1604661Sksewell@umich.edu int32_t dspExtpd( int64_t dspac, int32_t size, uint32_t *dspctl ); 1614661Sksewell@umich.edu 1624661Sksewell@umich.edu // SIMD pack/unpack utility functions 1634661Sksewell@umich.edu void simdPack( uint64_t *values_ptr, int32_t *reg, int32_t fmt ); 1644661Sksewell@umich.edu void simdUnpack( int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign ); 1654661Sksewell@umich.edu 1664661Sksewell@umich.edu // DSPControl r/w utility functions 1674661Sksewell@umich.edu void writeDSPControl( uint32_t *dspctl, uint32_t value, uint32_t mask ); 1684661Sksewell@umich.edu uint32_t readDSPControl( uint32_t *dspctl, uint32_t mask ); 1694661Sksewell@umich.edu}; 1704661Sksewell@umich.edu 1714661Sksewell@umich.edu#endif 172