dsp.hh revision 12334
18504SN/A/* 28504SN/A * Copyright (c) 2007 MIPS Technologies, Inc. 38504SN/A * All rights reserved. 48825Snilay@cs.wisc.edu * 58504SN/A * Redistribution and use in source and binary forms, with or without 68504SN/A * modification, are permitted provided that the following conditions are 78504SN/A * met: redistributions of source code must retain the above copyright 88504SN/A * notice, this list of conditions and the following disclaimer; 98504SN/A * redistributions in binary form must reproduce the above copyright 108504SN/A * notice, this list of conditions and the following disclaimer in the 118721SN/A * documentation and/or other materials provided with the distribution; 128504SN/A * neither the name of the copyright holders nor the names of its 138504SN/A * contributors may be used to endorse or promote products derived from 148504SN/A * this software without specific prior written permission. 158504SN/A * 168504SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178504SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188728SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198504SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208504SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218504SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228673SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238504SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248504SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258504SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268504SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278504SN/A * 288504SN/A * Authors: Brett Miller 298504SN/A */ 308504SN/A 318504SN/A#ifndef __ARCH_MIPS_DSP_HH__ 328504SN/A#define __ARCH_MIPS_DSP_HH__ 338504SN/A 348721SN/A#include "arch/mips/isa_traits.hh" 358504SN/A#include "arch/mips/types.hh" 368504SN/A#include "base/logging.hh" 378504SN/A#include "base/types.hh" 388504SN/A 398504SN/Aclass ThreadContext; 408504SN/A 418504SN/Anamespace MipsISA { 428504SN/A 438504SN/A// SIMD formats 448504SN/Aenum { 458504SN/A SIMD_FMT_L, // long word 468504SN/A SIMD_FMT_W, // word 478504SN/A SIMD_FMT_PH, // paired halfword 488504SN/A SIMD_FMT_QB, // quad byte 498504SN/A SIMD_NUM_FMTS 508504SN/A}; 518504SN/A 528504SN/A// DSPControl Fields 538504SN/Aenum { 548504SN/A DSP_POS, // insertion bitfield position 558504SN/A DSP_SCOUNT, // insertion bitfield size 568504SN/A DSP_C, // carry bit 578721SN/A DSP_OUFLAG, // overflow-underflow flag 588721SN/A DSP_CCOND, // condition code 598721SN/A DSP_EFI, // extract fail indicator bit 608504SN/A DSP_NUM_FIELDS 618721SN/A}; 628721SN/A 638504SN/A// compare instruction operations 648504SN/Aenum { 658504SN/A CMP_EQ, // equal 668504SN/A CMP_LT, // less than 678504SN/A CMP_LE // less than or equal 688504SN/A}; 698504SN/A 708504SN/A// SIMD operation order modes 718504SN/Aenum { 728504SN/A MODE_L, // left 738504SN/A MODE_R, // right 748504SN/A MODE_LA, // left-alternate 758504SN/A MODE_RA, // right-alternate 768504SN/A MODE_X // cross 778504SN/A}; 788504SN/A 798504SN/A// dsp operation parameters 808504SN/Aenum { UNSIGNED, SIGNED }; 818504SN/Aenum { NOSATURATE, SATURATE }; 828504SN/Aenum { NOROUND, ROUND }; 838504SN/A 848504SN/A// DSPControl field positions and masks 858504SN/Aconst uint32_t DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 }; 868504SN/Aconst uint32_t DSP_CTL_MASK[DSP_NUM_FIELDS] = 878504SN/A{ 0x0000003f, 0x00001f80, 0x00002000, 888504SN/A 0x00ff0000, 0x0f000000, 0x00004000 }; 898504SN/A 908504SN/A/* 918504SN/A * SIMD format constants 928504SN/A */ 938504SN/A 948504SN/A// maximum values per register 958504SN/Aconst uint32_t SIMD_MAX_VALS = 4; 968504SN/A// number of values in fmt 978504SN/Aconst uint32_t SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 }; 988504SN/A// number of bits per value 998504SN/Aconst uint32_t SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 }; 1008504SN/A// log2(bits per value) 1018504SN/Aconst uint32_t SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 }; 1028504SN/A 1038504SN/A 1048504SN/A// DSP maximum values 1058504SN/Aconst uint64_t FIXED_L_SMAX = ULL(0x7fffffffffffffff); 1068504SN/Aconst uint64_t FIXED_W_SMAX = ULL(0x000000007fffffff); 1078504SN/Aconst uint64_t FIXED_H_SMAX = ULL(0x0000000000007fff); 1088504SN/Aconst uint64_t FIXED_B_SMAX = ULL(0x000000000000007f); 1098504SN/Aconst uint64_t FIXED_L_UMAX = ULL(0xffffffffffffffff); 1108504SN/Aconst uint64_t FIXED_W_UMAX = ULL(0x00000000ffffffff); 1118504SN/Aconst uint64_t FIXED_H_UMAX = ULL(0x000000000000ffff); 1128504SN/Aconst uint64_t FIXED_B_UMAX = ULL(0x00000000000000ff); 1138504SN/Aconst uint64_t FIXED_SMAX[SIMD_NUM_FMTS] = 1148504SN/A{ FIXED_L_SMAX, FIXED_W_SMAX, FIXED_H_SMAX, FIXED_B_SMAX }; 1158504SN/Aconst uint64_t FIXED_UMAX[SIMD_NUM_FMTS] = 1168504SN/A{ FIXED_L_UMAX, FIXED_W_UMAX, FIXED_H_UMAX, FIXED_B_UMAX }; 1178504SN/A 1188504SN/A// DSP minimum values 1198504SN/Aconst uint64_t FIXED_L_SMIN = ULL(0x8000000000000000); 1208504SN/Aconst uint64_t FIXED_W_SMIN = ULL(0xffffffff80000000); 1218504SN/Aconst uint64_t FIXED_H_SMIN = ULL(0xffffffffffff8000); 1228504SN/Aconst uint64_t FIXED_B_SMIN = ULL(0xffffffffffffff80); 1238504SN/Aconst uint64_t FIXED_L_UMIN = ULL(0x0000000000000000); 1248504SN/Aconst uint64_t FIXED_W_UMIN = ULL(0x0000000000000000); 1258728SN/Aconst uint64_t FIXED_H_UMIN = ULL(0x0000000000000000); 1268504SN/Aconst uint64_t FIXED_B_UMIN = ULL(0x0000000000000000); 1278504SN/Aconst uint64_t FIXED_SMIN[SIMD_NUM_FMTS] = 1288504SN/A{ FIXED_L_SMIN, FIXED_W_SMIN, FIXED_H_SMIN, FIXED_B_SMIN }; 1298504SN/Aconst uint64_t FIXED_UMIN[SIMD_NUM_FMTS] = 1308504SN/A{ FIXED_L_UMIN, FIXED_W_UMIN, FIXED_H_UMIN, FIXED_B_UMIN }; 1318504SN/A 1328504SN/A// DSP utility functions 1338504SN/Aint32_t bitrev(int32_t value); 1348504SN/Auint64_t dspSaturate(uint64_t value, int32_t fmt, int32_t sign, 1358504SN/A uint32_t *overflow); 1368504SN/Auint64_t checkOverflow(uint64_t value, int32_t fmt, int32_t sign, 1378504SN/A uint32_t *overflow); 1388504SN/Auint64_t signExtend(uint64_t value, int32_t signpos); 1398504SN/Auint64_t addHalfLsb(uint64_t value, int32_t lsbpos); 1408504SN/Aint32_t dspAbs(int32_t a, int32_t fmt, uint32_t *dspctl); 1418504SN/Aint32_t dspAdd(int32_t a, int32_t b, int32_t fmt, int32_t saturate, 1428504SN/A int32_t sign, uint32_t *dspctl); 1438504SN/Aint32_t dspAddh(int32_t a, int32_t b, int32_t fmt, int32_t round, 1448504SN/A int32_t sign); 1458504SN/Aint32_t dspSub(int32_t a, int32_t b, int32_t fmt, int32_t saturate, 1468504SN/A int32_t sign, uint32_t *dspctl); 1478504SN/Aint32_t dspSubh(int32_t a, int32_t b, int32_t fmt, int32_t round, 1488504SN/A int32_t sign); 1498504SN/Aint32_t dspShll(int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, 1508504SN/A int32_t sign, uint32_t *dspctl); 1518521SN/Aint32_t dspShrl(int32_t a, uint32_t sa, int32_t fmt, int32_t sign); 1528504SN/Aint32_t dspShra(int32_t a, uint32_t sa, int32_t fmt, int32_t round, 1538504SN/A int32_t sign, uint32_t *dspctl); 1548504SN/Aint32_t dspMul(int32_t a, int32_t b, int32_t fmt, int32_t saturate, 1558504SN/A uint32_t *dspctl); 1568504SN/Aint32_t dspMulq(int32_t a, int32_t b, int32_t fmt, int32_t saturate, 1578825Snilay@cs.wisc.edu int32_t round, uint32_t *dspctl); 1588504SN/Aint32_t dspMuleu(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl); 1598504SN/Aint32_t dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl); 1608504SN/Aint64_t dspDpaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, 1618504SN/A int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, 1628504SN/A uint32_t *dspctl); 1638504SN/Aint64_t dspDpsq(int64_t dspac, int32_t a, int32_t b, int32_t ac, 1648504SN/A int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, 1658504SN/A uint32_t *dspctl); 1668504SN/Aint64_t dspDpa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, 1678504SN/A int32_t sign, int32_t mode); 1688504SN/Aint64_t dspDps(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, 1698504SN/A int32_t sign, int32_t mode); 1708504SN/Aint64_t dspMaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, 1718504SN/A int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl); 1728504SN/Aint64_t dspMulsa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt); 1738504SN/Aint64_t dspMulsaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, 1748504SN/A uint32_t *dspctl); 1758504SN/Avoid dspCmp(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, 1768504SN/A uint32_t *dspctl); 1778504SN/Aint32_t dspCmpg(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op); 1788504SN/Aint32_t dspCmpgd(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, 1798504SN/A uint32_t *dspctl); 1808504SN/Aint32_t dspPrece(int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, 1818504SN/A int32_t outsign, int32_t mode); 1828504SN/Aint32_t dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl); 1838504SN/Aint32_t dspPrecrq(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl); 1848504SN/Aint32_t dspPrecrSra(int32_t a, int32_t b, int32_t sa, int32_t fmt, 1858504SN/A int32_t round); 1868504SN/Aint32_t dspPick(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl); 1878504SN/Aint32_t dspPack(int32_t a, int32_t b, int32_t fmt); 1888504SN/Aint32_t dspExtr(int64_t dspac, int32_t fmt, int32_t sa, int32_t round, 1898504SN/A int32_t saturate, uint32_t *dspctl); 1908504SN/Aint32_t dspExtp(int64_t dspac, int32_t size, uint32_t *dspctl); 1918504SN/Aint32_t dspExtpd(int64_t dspac, int32_t size, uint32_t *dspctl); 1928504SN/A 1938504SN/A// SIMD pack/unpack utility functions 1948504SN/Avoid simdPack(uint64_t *values_ptr, int32_t *reg, int32_t fmt); 1958504SN/Avoid simdUnpack(int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign); 1968504SN/A 1978504SN/A// DSPControl r/w utility functions 1988504SN/Avoid writeDSPControl(uint32_t *dspctl, uint32_t value, uint32_t mask); 1998504SN/Auint32_t readDSPControl(uint32_t *dspctl, uint32_t mask); 2008504SN/A 2018504SN/A} // namespace MipsISA 2028504SN/A 2038504SN/A#endif // __ARCH_MIPS_DSP_HH__ 2048504SN/A