decoder.hh revision 9377:6f294e7a93d1
110612SMarco.Elver@ARM.com/* 210612SMarco.Elver@ARM.com * Copyright (c) 2012 Google 310612SMarco.Elver@ARM.com * All rights reserved. 410612SMarco.Elver@ARM.com * 510612SMarco.Elver@ARM.com * Redistribution and use in source and binary forms, with or without 610612SMarco.Elver@ARM.com * modification, are permitted provided that the following conditions are 710612SMarco.Elver@ARM.com * met: redistributions of source code must retain the above copyright 810612SMarco.Elver@ARM.com * notice, this list of conditions and the following disclaimer; 910612SMarco.Elver@ARM.com * redistributions in binary form must reproduce the above copyright 1010612SMarco.Elver@ARM.com * notice, this list of conditions and the following disclaimer in the 1110612SMarco.Elver@ARM.com * documentation and/or other materials provided with the distribution; 1210612SMarco.Elver@ARM.com * neither the name of the copyright holders nor the names of its 1310612SMarco.Elver@ARM.com * contributors may be used to endorse or promote products derived from 1410612SMarco.Elver@ARM.com * this software without specific prior written permission. 1510612SMarco.Elver@ARM.com * 1610612SMarco.Elver@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710612SMarco.Elver@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810612SMarco.Elver@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910612SMarco.Elver@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010612SMarco.Elver@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110612SMarco.Elver@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210612SMarco.Elver@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310612SMarco.Elver@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410612SMarco.Elver@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510612SMarco.Elver@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610612SMarco.Elver@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710612SMarco.Elver@ARM.com * 2810612SMarco.Elver@ARM.com * Authors: Gabe Black 2910612SMarco.Elver@ARM.com */ 3010612SMarco.Elver@ARM.com 3110612SMarco.Elver@ARM.com#ifndef __ARCH_MIPS_DECODER_HH__ 3210612SMarco.Elver@ARM.com#define __ARCH_MIPS_DECODER_HH__ 3310612SMarco.Elver@ARM.com 3410612SMarco.Elver@ARM.com#include "arch/generic/decode_cache.hh" 3510612SMarco.Elver@ARM.com#include "arch/mips/types.hh" 3610612SMarco.Elver@ARM.com#include "base/misc.hh" 3710612SMarco.Elver@ARM.com#include "base/types.hh" 3810612SMarco.Elver@ARM.com#include "cpu/static_inst.hh" 3910612SMarco.Elver@ARM.com 4010612SMarco.Elver@ARM.comnamespace MipsISA 4110612SMarco.Elver@ARM.com{ 4210612SMarco.Elver@ARM.com 4310612SMarco.Elver@ARM.comclass Decoder 4410612SMarco.Elver@ARM.com{ 4510612SMarco.Elver@ARM.com protected: 4610612SMarco.Elver@ARM.com //The extended machine instruction being generated 4710612SMarco.Elver@ARM.com ExtMachInst emi; 4810612SMarco.Elver@ARM.com bool instDone; 4910612SMarco.Elver@ARM.com 5010612SMarco.Elver@ARM.com public: 5110612SMarco.Elver@ARM.com Decoder() : instDone(false) 5210612SMarco.Elver@ARM.com {} 5310612SMarco.Elver@ARM.com 5410612SMarco.Elver@ARM.com void 5510612SMarco.Elver@ARM.com process() 5610612SMarco.Elver@ARM.com { 5710612SMarco.Elver@ARM.com } 5810612SMarco.Elver@ARM.com 59 void 60 reset() 61 { 62 instDone = false; 63 } 64 65 //Use this to give data to the decoder. This should be used 66 //when there is control flow. 67 void 68 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) 69 { 70 emi = inst; 71 instDone = true; 72 } 73 74 bool 75 needMoreBytes() 76 { 77 return true; 78 } 79 80 bool 81 instReady() 82 { 83 return instDone; 84 } 85 86 protected: 87 /// A cache of decoded instruction objects. 88 static GenericISA::BasicDecodeCache defaultCache; 89 90 public: 91 StaticInstPtr decodeInst(ExtMachInst mach_inst); 92 93 /// Decode a machine instruction. 94 /// @param mach_inst The binary instruction to decode. 95 /// @retval A pointer to the corresponding StaticInst object. 96 StaticInstPtr 97 decode(ExtMachInst mach_inst, Addr addr) 98 { 99 return defaultCache.decode(this, mach_inst, addr); 100 } 101 102 StaticInstPtr 103 decode(MipsISA::PCState &nextPC) 104 { 105 if (!instDone) 106 return NULL; 107 instDone = false; 108 return decode(emi, nextPC.instAddr()); 109 } 110}; 111 112} // namespace MipsISA 113 114#endif // __ARCH_MIPS_DECODER_HH__ 115