tlb.hh revision 13741:d994984b842a
1298SN/A/* 22188SN/A * Copyright (c) 2011 ARM Limited 3298SN/A * All rights reserved. 4298SN/A * 5298SN/A * The license below extends only to copyright in the software and shall 6298SN/A * not be construed as granting a license to any other intellectual 7298SN/A * property including but not limited to intellectual property relating 8298SN/A * to a hardware implementation of the functionality of the software 9298SN/A * licensed hereunder. You may use the software subject to the license 10298SN/A * terms below provided that you ensure that this notice is replicated 11298SN/A * unmodified and in its entirety in all distributions of the software, 12298SN/A * modified or unmodified, in source code or in binary form. 13298SN/A * 14298SN/A * Copyright (c) 2006 The Regents of The University of Michigan 15298SN/A * All rights reserved. 16298SN/A * 17298SN/A * Redistribution and use in source and binary forms, with or without 18298SN/A * modification, are permitted provided that the following conditions are 19298SN/A * met: redistributions of source code must retain the above copyright 20298SN/A * notice, this list of conditions and the following disclaimer; 21298SN/A * redistributions in binary form must reproduce the above copyright 22298SN/A * notice, this list of conditions and the following disclaimer in the 23298SN/A * documentation and/or other materials provided with the distribution; 24298SN/A * neither the name of the copyright holders nor the names of its 25298SN/A * contributors may be used to endorse or promote products derived from 26298SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29298SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30298SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311642SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32954SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33956SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34956SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354078Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36299SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37299SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386118Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396118Snate@binkert.org * 402170SN/A * Authors: Gabe Black 415882Snate@binkert.org */ 421717SN/A 432680Sktlim@umich.edu#ifndef __ARCH_GENERIC_TLB_HH__ 442313SN/A#define __ARCH_GENERIC_TLB_HH__ 455529Snate@binkert.org 463565Sgblack@eecs.umich.edu#include "base/logging.hh" 47298SN/A#include "mem/mem_object.hh" 485606Snate@binkert.org#include "mem/request.hh" 49298SN/A 50695SN/Aclass ThreadContext; 51695SN/Aclass BaseMasterPort; 52954SN/A 536118Snate@binkert.orgclass BaseTLB : public MemObject 545780Ssteve.reinhardt@amd.com{ 556118Snate@binkert.org protected: 562080SN/A BaseTLB(const Params *p) 575780Ssteve.reinhardt@amd.com : MemObject(p) 58298SN/A {} 59299SN/A 601052SN/A public: 61729SN/A 622107SN/A enum Mode { Read, Write, Execute }; 63298SN/A 645504Snate@binkert.org class Translation 655504Snate@binkert.org { 665780Ssteve.reinhardt@amd.com public: 675780Ssteve.reinhardt@amd.com virtual ~Translation() 685504Snate@binkert.org {} 695504Snate@binkert.org 70298SN/A /** 715504Snate@binkert.org * Signal that the translation has been delayed due to a hw page table 725504Snate@binkert.org * walk. 735504Snate@binkert.org */ 745504Snate@binkert.org virtual void markDelayed() = 0; 755504Snate@binkert.org 765504Snate@binkert.org /* 775504Snate@binkert.org * The memory for this object may be dynamically allocated, and it may 785529Snate@binkert.org * be responsible for cleaning itself up which will happen in this 795504Snate@binkert.org * function. Once it's called, the object is no longer valid. 805504Snate@binkert.org */ 815504Snate@binkert.org virtual void finish(const Fault &fault, const RequestPtr &req, 825504Snate@binkert.org ThreadContext *tc, Mode mode) = 0; 835504Snate@binkert.org 845504Snate@binkert.org /** This function is used by the page table walker to determine if it 855504Snate@binkert.org * should translate the a pending request or if the underlying request 865504Snate@binkert.org * has been squashed. 875504Snate@binkert.org * @ return Is the instruction that requested this translation squashed? 885504Snate@binkert.org */ 895504Snate@binkert.org virtual bool squashed() const { return false; } 905504Snate@binkert.org }; 915529Snate@binkert.org 925504Snate@binkert.org public: 935504Snate@binkert.org virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 945504Snate@binkert.org 955504Snate@binkert.org virtual Fault translateAtomic( 965504Snate@binkert.org const RequestPtr &req, ThreadContext *tc, Mode mode) = 0; 975504Snate@binkert.org virtual void translateTiming( 985606Snate@binkert.org const RequestPtr &req, ThreadContext *tc, 995504Snate@binkert.org Translation *translation, Mode mode) = 0; 1005504Snate@binkert.org virtual Fault 1015504Snate@binkert.org translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode) 1025504Snate@binkert.org { 1035504Snate@binkert.org panic("Not implemented.\n"); 1045504Snate@binkert.org } 1055504Snate@binkert.org 1065504Snate@binkert.org /** 1075504Snate@binkert.org * Do post-translation physical address finalization. 1085504Snate@binkert.org * 1095504Snate@binkert.org * This method is used by some architectures that need 1105504Snate@binkert.org * post-translation massaging of physical addresses. For example, 1115529Snate@binkert.org * X86 uses this to remap physical addresses in the APIC range to 1125504Snate@binkert.org * a range of physical memory not normally available to real x86 1135504Snate@binkert.org * implementations. 1145504Snate@binkert.org * 1155504Snate@binkert.org * @param req Request to updated in-place. 1165504Snate@binkert.org * @param tc Thread context that created the request. 1175504Snate@binkert.org * @param mode Request type (read/write/execute). 1185606Snate@binkert.org * @return A fault on failure, NoFault otherwise. 1195504Snate@binkert.org */ 1205504Snate@binkert.org virtual Fault finalizePhysical( 1215504Snate@binkert.org const RequestPtr &req, ThreadContext *tc, Mode mode) const = 0; 1225504Snate@binkert.org 1235504Snate@binkert.org /** 1245504Snate@binkert.org * Remove all entries from the TLB 1255504Snate@binkert.org */ 1265504Snate@binkert.org virtual void flushAll() = 0; 1275504Snate@binkert.org 1285504Snate@binkert.org /** 1295504Snate@binkert.org * Take over from an old tlb context 1305504Snate@binkert.org */ 1315504Snate@binkert.org virtual void takeOverFrom(BaseTLB *otlb) = 0; 1325504Snate@binkert.org 1335504Snate@binkert.org /** 1345780Ssteve.reinhardt@amd.com * Get the table walker master port if present. This is used for 1355780Ssteve.reinhardt@amd.com * migrating port connections during a CPU takeOverFrom() 1365741Snate@binkert.org * call. For architectures that do not have a table walker, NULL 1375741Snate@binkert.org * is returned, hence the use of a pointer rather than a 1385741Snate@binkert.org * reference. 1395741Snate@binkert.org * 1405741Snate@binkert.org * @return A pointer to the walker master port or NULL if not present 1415741Snate@binkert.org */ 1425504Snate@binkert.org virtual BaseMasterPort* getTableWalkerMasterPort() { return NULL; } 1435808Snate@binkert.org 1445808Snate@binkert.org void memInvalidate() { flushAll(); } 1455808Snate@binkert.org}; 1465808Snate@binkert.org 1475808Snate@binkert.orgclass GenericTLB : public BaseTLB 1485808Snate@binkert.org{ 1495808Snate@binkert.org protected: 1505808Snate@binkert.org GenericTLB(const Params *p) 1515808Snate@binkert.org : BaseTLB(p) 1525504Snate@binkert.org {} 1535504Snate@binkert.org 1545504Snate@binkert.org public: 1555606Snate@binkert.org void demapPage(Addr vaddr, uint64_t asn) override; 1565606Snate@binkert.org 1575504Snate@binkert.org Fault translateAtomic( 1585504Snate@binkert.org const RequestPtr &req, ThreadContext *tc, Mode mode) override; 1595780Ssteve.reinhardt@amd.com void translateTiming( 1605780Ssteve.reinhardt@amd.com const RequestPtr &req, ThreadContext *tc, 1615504Snate@binkert.org Translation *translation, Mode mode) override; 1625504Snate@binkert.org 1635504Snate@binkert.org Fault finalizePhysical( 1645504Snate@binkert.org const RequestPtr &req, ThreadContext *tc, Mode mode) const override; 1655504Snate@binkert.org}; 1665504Snate@binkert.org 167711SN/A#endif // __ARCH_GENERIC_TLB_HH__ 168711SN/A