mmapped_ipr.hh revision 9911:676d3dcf1cc2 
1/*
2 * Copyright (c) 2013 Andreas Sandberg
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Andreas Sandberg
29 */
30
31#ifndef __ARCH_GENERIC_MMAPPED_IPR_HH__
32#define __ARCH_GENERIC_MMAPPED_IPR_HH__
33
34#include "base/types.hh"
35#include "mem/packet.hh"
36
37class ThreadContext;
38
39/**
40 * @file
41 *
42 * ISA-generic helper functions for memory mapped IPR accesses.
43 */
44
45namespace GenericISA
46{
47    /** @{ */
48    /**
49     * Memory requests with the MMAPPED_IPR flag are generally mapped
50     * to registers. There is a class of these registers that are
51     * internal to gem5, for example gem5 pseudo-ops in virtualized
52     * mode. Such IPRs always have the flag GENERIC_IPR set and are
53     * handled by this code.
54     */
55
56    /** Shift amount when extracting the class of a generic IPR */
57    const int IPR_CLASS_SHIFT = 48;
58
59    /** Mask to extract the offset in within a generic IPR class */
60    const Addr IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF);
61
62    /** gem5 pseudo-inst emulation.
63     *
64     * Read and writes to this class execute gem5
65     * pseudo-instructions. A write discards the return value of the
66     * instruction, while a read returns it.
67     *
68     * @see pseudoInst()
69     */
70    const Addr IPR_CLASS_PSEUDO_INST = 0x0;
71
72    /** @} */
73
74    /**
75     * Generate a generic IPR address that emulates a pseudo inst
76     *
77     * @see PseudoInst::pseudoInst()
78     *
79     * @param func Function ID to call.
80     * @param subfunc Sub-function, usually 0.
81     * @return Address in the IPR space corresponding to the call.
82     */
83    inline Addr
84    iprAddressPseudoInst(uint8_t func, uint8_t subfunc)
85    {
86        return (IPR_CLASS_PSEUDO_INST << IPR_CLASS_SHIFT)  |
87            (func << 8) | subfunc;
88    }
89
90    /**
91     * Check if this is an platform independent IPR access
92     *
93     * Accesses to internal platform independent gem5 registers are
94     * handled by handleGenericIprRead() and
95     * handleGenericIprWrite(). This method determines if a packet
96     * should be routed to those functions instead of the platform
97     * specific code.
98     *
99     * @see handleGenericIprRead
100     * @see handleGenericIprWrite
101     */
102    inline bool
103    isGenericIprAccess(const Packet *pkt)
104    {
105        Request::Flags flags(pkt->req->getFlags());
106        return (flags & Request::MMAPPED_IPR) &&
107            (flags & Request::GENERIC_IPR);
108    }
109
110    /**
111     * Handle generic IPR reads
112     *
113     * @param xc Thread context of the current thread.
114     * @param pkt Packet from the CPU
115     * @return Latency in CPU cycles
116     */
117    Cycles handleGenericIprRead(ThreadContext *xc, Packet *pkt);
118    /**
119     * Handle generic IPR writes
120     *
121     * @param xc Thread context of the current thread.
122     * @param pkt Packet from the CPU
123     * @return Latency in CPU cycles
124     */
125    Cycles handleGenericIprWrite(ThreadContext *xc, Packet *pkt);
126
127    /**
128     * Helper function to handle IPRs when the target architecture doesn't
129     * need its own IPR handling.
130     *
131     * This function calls handleGenericIprRead if the accessing a
132     * generic IPR and panics otherwise.
133     *
134     * @param xc Thread context of the current thread.
135     * @param pkt Packet from the CPU
136     * @return Latency in CPU cycles
137     */
138    inline Cycles
139    handleIprRead(ThreadContext *xc, Packet *pkt)
140    {
141        if (!isGenericIprAccess(pkt))
142            panic("Unhandled IPR access\n");
143
144        return handleGenericIprRead(xc, pkt);
145    }
146
147
148    /**
149     * Helper function to handle IPRs when the target architecture
150     * doesn't need its own IPR handling.
151     *
152     * This function calls handleGenericIprWrite if the accessing a
153     * generic IPR and panics otherwise.
154     *
155     * @param xc Thread context of the current thread.
156     * @param pkt Packet from the CPU
157     * @return Latency in CPU cycles
158     */
159    inline Cycles
160    handleIprWrite(ThreadContext *xc, Packet *pkt)
161    {
162        if (!isGenericIprAccess(pkt))
163            panic("Unhandled IPR access\n");
164
165        return handleGenericIprWrite(xc, pkt);
166    }
167
168} // namespace GenericISA
169
170
171
172#endif
173