vtophys.cc revision 8232 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Nathan Binkert
43 *          Stephen Hines
44 */
45
46#include <string>
47
48#include "arch/arm/table_walker.hh"
49#include "arch/arm/tlb.hh"
50#include "arch/arm/vtophys.hh"
51#include "base/chunk_generator.hh"
52#include "base/trace.hh"
53#include "cpu/thread_context.hh"
54#include "mem/vport.hh"
55
56using namespace std;
57using namespace ArmISA;
58
59Addr
60ArmISA::vtophys(Addr vaddr)
61{
62    fatal("VTOPHYS: Can't convert vaddr to paddr on ARM without a thread context");
63}
64
65Addr
66ArmISA::vtophys(ThreadContext *tc, Addr addr)
67{
68    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
69    if (!sctlr.m) {
70        // Translation is currently disabled PA == VA
71        return addr;
72    }
73    bool success;
74    Addr pa;
75    ArmISA::TLB *tlb;
76
77    // Check the TLBs far a translation
78    // It's possible that there is a validy translation in the tlb
79    // that is no loger valid in the page table in memory
80    // so we need to check here first
81    tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr());
82    success = tlb->translateFunctional(tc, addr, pa);
83    if (success)
84        return pa;
85
86    tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
87    success = tlb->translateFunctional(tc, addr, pa);
88    if (success)
89        return pa;
90
91    // We've failed everything, so we need to do a
92    // hardware tlb walk without messing with any
93    // state
94
95    uint32_t N = tc->readMiscReg(MISCREG_TTBCR);
96    Addr ttbr;
97    if (N == 0 || !mbits(addr, 31, 32-N)) {
98        ttbr = tc->readMiscReg(MISCREG_TTBR0);
99    } else {
100        ttbr = tc->readMiscReg(MISCREG_TTBR1);
101        N = 0;
102    }
103
104    FunctionalPort *port = tc->getPhysPort();
105    Addr l1desc_addr = mbits(ttbr, 31, 14-N) | (bits(addr,31-N,20) << 2);
106
107    TableWalker::L1Descriptor l1desc;
108    l1desc.data = port->read<uint32_t>(l1desc_addr);
109    if (l1desc.type() == TableWalker::L1Descriptor::Ignore ||
110            l1desc.type() == TableWalker::L1Descriptor::Reserved) {
111        warn("Unable to translate virtual address: %#x\n", addr);
112        return -1;
113    }
114    if (l1desc.type() == TableWalker::L1Descriptor::Section)
115        return l1desc.paddr(addr);
116
117    // Didn't find it at the first level, try againt
118    Addr l2desc_addr = l1desc.l2Addr() | (bits(addr, 19, 12) << 2);
119    TableWalker::L2Descriptor l2desc;
120    l2desc.data = port->read<uint32_t>(l2desc_addr);
121
122    if (l2desc.invalid()) {
123        warn("Unable to translate virtual address: %#x\n", addr);
124        return -1;
125    }
126
127    return l2desc.paddr(addr);
128}
129
130bool
131ArmISA::virtvalid(ThreadContext *tc, Addr vaddr)
132{
133    if (vtophys(tc, vaddr) != -1)
134        return true;
135    return false;
136}
137
138
139