utility.cc revision 8852
1/* 2 * Copyright (c) 2009-2010 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 */ 39 40 41#include "arch/arm/faults.hh" 42#include "arch/arm/isa_traits.hh" 43#include "arch/arm/tlb.hh" 44#include "arch/arm/utility.hh" 45#include "arch/arm/vtophys.hh" 46#include "config/use_checker.hh" 47#include "cpu/thread_context.hh" 48#include "mem/fs_translating_port_proxy.hh" 49#include "sim/full_system.hh" 50 51namespace ArmISA { 52 53void 54initCPU(ThreadContext *tc, int cpuId) 55{ 56 // Reset CP15?? What does that mean -- ali 57 58 // FPEXC.EN = 0 59 60 static Fault reset = new Reset; 61 reset->invoke(tc); 62} 63 64uint64_t 65getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 66{ 67 if (!FullSystem) { 68 panic("getArgument() only implemented for full system mode.\n"); 69 M5_DUMMY_RETURN 70 } 71 72 if (size == (uint16_t)(-1)) 73 size = ArmISA::MachineBytes; 74 if (fp) 75 panic("getArgument(): Floating point arguments not implemented\n"); 76 77 if (number < NumArgumentRegs) { 78 // If the argument is 64 bits, it must be in an even regiser 79 // number. Increment the number here if it isn't even. 80 if (size == sizeof(uint64_t)) { 81 if ((number % 2) != 0) 82 number++; 83 // Read the two halves of the data. Number is inc here to 84 // get the second half of the 64 bit reg. 85 uint64_t tmp; 86 tmp = tc->readIntReg(number++); 87 tmp |= tc->readIntReg(number) << 32; 88 return tmp; 89 } else { 90 return tc->readIntReg(number); 91 } 92 } else { 93 Addr sp = tc->readIntReg(StackPointerReg); 94 FSTranslatingPortProxy &vp = tc->getVirtProxy(); 95 uint64_t arg; 96 if (size == sizeof(uint64_t)) { 97 // If the argument is even it must be aligned 98 if ((number % 2) != 0) 99 number++; 100 arg = vp.read<uint64_t>(sp + 101 (number-NumArgumentRegs) * sizeof(uint32_t)); 102 // since two 32 bit args == 1 64 bit arg, increment number 103 number++; 104 } else { 105 arg = vp.read<uint32_t>(sp + 106 (number-NumArgumentRegs) * sizeof(uint32_t)); 107 } 108 return arg; 109 } 110} 111 112void 113skipFunction(ThreadContext *tc) 114{ 115 TheISA::PCState newPC = tc->pcState(); 116 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1)); 117#if USE_CHECKER 118 tc->pcStateNoRecord(newPC); 119#else 120 tc->pcState(newPC); 121#endif 122} 123 124void 125copyRegs(ThreadContext *src, ThreadContext *dest) 126{ 127 int i; 128 129 int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode; 130 131 // Make sure we're in user mode, so we can easily see all the registers 132 // in the copy loop 133 src->setMiscReg(MISCREG_CPSR_MODE, MODE_USER); 134 dest->setMiscReg(MISCREG_CPSR_MODE, MODE_USER); 135 136 for(i = 0; i < TheISA::NumIntRegs; i++) 137 dest->setIntReg(i, src->readIntReg(i)); 138 139 // Restore us back to the old mode 140 src->setMiscReg(MISCREG_CPSR_MODE, saved_mode); 141 dest->setMiscReg(MISCREG_CPSR_MODE, saved_mode); 142 143 for(i = 0; i < TheISA::NumFloatRegs; i++) 144 dest->setFloatReg(i, src->readFloatReg(i)); 145 for(i = 0; i < TheISA::NumMiscRegs; i++) 146 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 147 148 // setMiscReg "with effect" will set the misc register mapping correctly. 149 // e.g. updateRegMap(val) 150 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR)); 151 152 // Copy over the PC State 153 dest->pcState(src->pcState()); 154 155 // Invalidate the tlb misc register cache 156 dest->getITBPtr()->invalidateMiscReg(); 157 dest->getDTBPtr()->invalidateMiscReg(); 158} 159 160Addr 161truncPage(Addr addr) 162{ 163 return addr & ~(PageBytes - 1); 164} 165 166Addr 167roundPage(Addr addr) 168{ 169 return (addr + PageBytes - 1) & ~(PageBytes - 1); 170} 171 172} // namespace ArmISA 173