utility.cc revision 12712
1/* 2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 */ 39 40#include "arch/arm/utility.hh" 41 42#include <memory> 43 44#include "arch/arm/faults.hh" 45#include "arch/arm/isa_traits.hh" 46#include "arch/arm/system.hh" 47#include "arch/arm/tlb.hh" 48#include "arch/arm/vtophys.hh" 49#include "cpu/base.hh" 50#include "cpu/checker/cpu.hh" 51#include "cpu/thread_context.hh" 52#include "mem/fs_translating_port_proxy.hh" 53#include "sim/full_system.hh" 54 55namespace ArmISA { 56 57void 58initCPU(ThreadContext *tc, int cpuId) 59{ 60 // Reset CP15?? What does that mean -- ali 61 62 // FPEXC.EN = 0 63 64 static Fault reset = std::make_shared<Reset>(); 65 reset->invoke(tc); 66} 67 68uint64_t 69getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 70{ 71 if (!FullSystem) { 72 panic("getArgument() only implemented for full system mode.\n"); 73 M5_DUMMY_RETURN 74 } 75 76 if (fp) 77 panic("getArgument(): Floating point arguments not implemented\n"); 78 79 if (inAArch64(tc)) { 80 if (size == (uint16_t)(-1)) 81 size = sizeof(uint64_t); 82 83 if (number < 8 /*NumArgumentRegs64*/) { 84 return tc->readIntReg(number); 85 } else { 86 panic("getArgument(): No support reading stack args for AArch64\n"); 87 } 88 } else { 89 if (size == (uint16_t)(-1)) 90 // todo: should this not be sizeof(uint32_t) rather? 91 size = ArmISA::MachineBytes; 92 93 if (number < NumArgumentRegs) { 94 // If the argument is 64 bits, it must be in an even regiser 95 // number. Increment the number here if it isn't even. 96 if (size == sizeof(uint64_t)) { 97 if ((number % 2) != 0) 98 number++; 99 // Read the two halves of the data. Number is inc here to 100 // get the second half of the 64 bit reg. 101 uint64_t tmp; 102 tmp = tc->readIntReg(number++); 103 tmp |= tc->readIntReg(number) << 32; 104 return tmp; 105 } else { 106 return tc->readIntReg(number); 107 } 108 } else { 109 Addr sp = tc->readIntReg(StackPointerReg); 110 FSTranslatingPortProxy &vp = tc->getVirtProxy(); 111 uint64_t arg; 112 if (size == sizeof(uint64_t)) { 113 // If the argument is even it must be aligned 114 if ((number % 2) != 0) 115 number++; 116 arg = vp.read<uint64_t>(sp + 117 (number-NumArgumentRegs) * sizeof(uint32_t)); 118 // since two 32 bit args == 1 64 bit arg, increment number 119 number++; 120 } else { 121 arg = vp.read<uint32_t>(sp + 122 (number-NumArgumentRegs) * sizeof(uint32_t)); 123 } 124 return arg; 125 } 126 } 127 panic("getArgument() should always return\n"); 128} 129 130void 131skipFunction(ThreadContext *tc) 132{ 133 PCState newPC = tc->pcState(); 134 if (inAArch64(tc)) { 135 newPC.set(tc->readIntReg(INTREG_X30)); 136 } else { 137 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1)); 138 } 139 140 CheckerCPU *checker = tc->getCheckerCpuPtr(); 141 if (checker) { 142 tc->pcStateNoRecord(newPC); 143 } else { 144 tc->pcState(newPC); 145 } 146} 147 148void 149copyRegs(ThreadContext *src, ThreadContext *dest) 150{ 151 for (int i = 0; i < NumIntRegs; i++) 152 dest->setIntRegFlat(i, src->readIntRegFlat(i)); 153 154 for (int i = 0; i < NumFloatRegs; i++) 155 dest->setFloatRegFlat(i, src->readFloatRegFlat(i)); 156 157 for (int i = 0; i < NumVecRegs; i++) 158 dest->setVecRegFlat(i, src->readVecRegFlat(i)); 159 160 for (int i = 0; i < NumCCRegs; i++) 161 dest->setCCReg(i, src->readCCReg(i)); 162 163 for (int i = 0; i < NumMiscRegs; i++) 164 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 165 166 // setMiscReg "with effect" will set the misc register mapping correctly. 167 // e.g. updateRegMap(val) 168 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR)); 169 170 // Copy over the PC State 171 dest->pcState(src->pcState()); 172 173 // Invalidate the tlb misc register cache 174 dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg(); 175 dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg(); 176} 177 178bool 179inSecureState(ThreadContext *tc) 180{ 181 SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) : 182 tc->readMiscReg(MISCREG_SCR); 183 return ArmSystem::haveSecurity(tc) && inSecureState( 184 scr, tc->readMiscReg(MISCREG_CPSR)); 185} 186 187inline bool 188isSecureBelowEL3(ThreadContext *tc) 189{ 190 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); 191 return ArmSystem::haveEL(tc, EL3) && scr.ns == 0; 192} 193 194bool 195inAArch64(ThreadContext *tc) 196{ 197 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 198 return opModeIs64((OperatingMode) (uint8_t) cpsr.mode); 199} 200 201bool 202longDescFormatInUse(ThreadContext *tc) 203{ 204 TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR); 205 return ArmSystem::haveLPAE(tc) && ttbcr.eae; 206} 207 208uint32_t 209getMPIDR(ArmSystem *arm_sys, ThreadContext *tc) 210{ 211 // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical 212 // Reference Manual 213 // 214 // bit 31 - Multi-processor extensions available 215 // bit 30 - Uni-processor system 216 // bit 24 - Multi-threaded cores 217 // bit 11-8 - Cluster ID 218 // bit 1-0 - CPU ID 219 // 220 // We deliberately extend both the Cluster ID and CPU ID fields to allow 221 // for simulation of larger systems 222 assert((0 <= tc->cpuId()) && (tc->cpuId() < 256)); 223 assert(tc->socketId() < 65536); 224 if (arm_sys->multiThread) { 225 return 0x80000000 | // multiprocessor extensions available 226 0x01000000 | // multi-threaded cores 227 tc->contextId(); 228 } else if (arm_sys->multiProc) { 229 return 0x80000000 | // multiprocessor extensions available 230 tc->cpuId() | tc->socketId() << 8; 231 } else { 232 return 0x80000000 | // multiprocessor extensions available 233 0x40000000 | // in up system 234 tc->cpuId() | tc->socketId() << 8; 235 } 236} 237 238bool 239ELIs64(ThreadContext *tc, ExceptionLevel el) 240{ 241 return !ELIs32(tc, el); 242} 243 244bool 245ELIs32(ThreadContext *tc, ExceptionLevel el) 246{ 247 bool known, aarch32; 248 std::tie(known, aarch32) = ELUsingAArch32K(tc, el); 249 panic_if(!known, "EL state is UNKNOWN"); 250 return aarch32; 251} 252 253std::pair<bool, bool> 254ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el) 255{ 256 // Return true if the specified EL is in aarch32 state. 257 const bool have_el3 = ArmSystem::haveSecurity(tc); 258 const bool have_el2 = ArmSystem::haveVirtualization(tc); 259 260 panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist"); 261 panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist"); 262 263 bool known, aarch32; 264 known = aarch32 = false; 265 if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) { 266 // Target EL is the highest one in a system where 267 // the highest is using AArch64. 268 known = true; aarch32 = false; 269 } else if (!ArmSystem::highestELIs64(tc)) { 270 // All ELs are using AArch32: 271 known = true; aarch32 = true; 272 } else { 273 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); 274 bool aarch32_below_el3 = (have_el3 && scr.rw == 0); 275 276 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); 277 bool aarch32_at_el1 = (aarch32_below_el3 278 || (have_el2 279 && !isSecureBelowEL3(tc) && hcr.rw == 0)); 280 281 // Only know if EL0 using AArch32 from PSTATE 282 if (el == EL0 && !aarch32_at_el1) { 283 // EL0 controlled by PSTATE 284 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 285 286 known = (cpsr.el == EL0); 287 aarch32 = (cpsr.width == 1); 288 } else { 289 known = true; 290 aarch32 = (aarch32_below_el3 && el != EL3) 291 || (aarch32_at_el1 && (el == EL0 || el == EL1) ); 292 } 293 } 294 295 return std::make_pair(known, aarch32); 296} 297 298bool 299isBigEndian64(ThreadContext *tc) 300{ 301 switch (opModeToEL(currOpMode(tc))) { 302 case EL3: 303 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee; 304 case EL2: 305 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee; 306 case EL1: 307 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee; 308 case EL0: 309 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e; 310 default: 311 panic("Invalid exception level"); 312 break; 313 } 314} 315 316Addr 317purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, 318 TTBCR tcr) 319{ 320 switch (el) { 321 case EL0: 322 case EL1: 323 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1) 324 return addr | mask(63, 55); 325 else if (!bits(addr, 55, 48) && tcr.tbi0) 326 return bits(addr,55, 0); 327 break; 328 case EL2: 329 assert(ArmSystem::haveVirtualization(tc)); 330 tcr = tc->readMiscReg(MISCREG_TCR_EL2); 331 if (tcr.tbi) 332 return addr & mask(56); 333 break; 334 case EL3: 335 assert(ArmSystem::haveSecurity(tc)); 336 if (tcr.tbi) 337 return addr & mask(56); 338 break; 339 default: 340 panic("Invalid exception level"); 341 break; 342 } 343 344 return addr; // Nothing to do if this is not a tagged address 345} 346 347Addr 348purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el) 349{ 350 TTBCR tcr; 351 352 switch (el) { 353 case EL0: 354 case EL1: 355 tcr = tc->readMiscReg(MISCREG_TCR_EL1); 356 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1) 357 return addr | mask(63, 55); 358 else if (!bits(addr, 55, 48) && tcr.tbi0) 359 return bits(addr,55, 0); 360 break; 361 case EL2: 362 assert(ArmSystem::haveVirtualization(tc)); 363 tcr = tc->readMiscReg(MISCREG_TCR_EL2); 364 if (tcr.tbi) 365 return addr & mask(56); 366 break; 367 case EL3: 368 assert(ArmSystem::haveSecurity(tc)); 369 tcr = tc->readMiscReg(MISCREG_TCR_EL3); 370 if (tcr.tbi) 371 return addr & mask(56); 372 break; 373 default: 374 panic("Invalid exception level"); 375 break; 376 } 377 378 return addr; // Nothing to do if this is not a tagged address 379} 380 381Addr 382truncPage(Addr addr) 383{ 384 return addr & ~(PageBytes - 1); 385} 386 387Addr 388roundPage(Addr addr) 389{ 390 return (addr + PageBytes - 1) & ~(PageBytes - 1); 391} 392 393bool 394mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, 395 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss) 396{ 397 bool isRead; 398 uint32_t crm; 399 IntRegIndex rt; 400 uint32_t crn; 401 uint32_t opc1; 402 uint32_t opc2; 403 bool trapToHype = false; 404 405 406 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { 407 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2); 408 trapToHype = ((uint32_t) hstr) & (1 << crn); 409 trapToHype |= hdcr.tpm && (crn == 9) && (crm >= 12); 410 trapToHype |= hcr.tidcp && ( 411 ((crn == 9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) || 412 ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) || 413 ((crn == 11) && ((crm <= 8) || (crm == 15))) ); 414 415 if (!trapToHype) { 416 switch (unflattenMiscReg(miscReg)) { 417 case MISCREG_CPACR: 418 trapToHype = hcptr.tcpac; 419 break; 420 case MISCREG_REVIDR: 421 case MISCREG_TCMTR: 422 case MISCREG_TLBTR: 423 case MISCREG_AIDR: 424 trapToHype = hcr.tid1; 425 break; 426 case MISCREG_CTR: 427 case MISCREG_CCSIDR: 428 case MISCREG_CLIDR: 429 case MISCREG_CSSELR: 430 trapToHype = hcr.tid2; 431 break; 432 case MISCREG_ID_PFR0: 433 case MISCREG_ID_PFR1: 434 case MISCREG_ID_DFR0: 435 case MISCREG_ID_AFR0: 436 case MISCREG_ID_MMFR0: 437 case MISCREG_ID_MMFR1: 438 case MISCREG_ID_MMFR2: 439 case MISCREG_ID_MMFR3: 440 case MISCREG_ID_ISAR0: 441 case MISCREG_ID_ISAR1: 442 case MISCREG_ID_ISAR2: 443 case MISCREG_ID_ISAR3: 444 case MISCREG_ID_ISAR4: 445 case MISCREG_ID_ISAR5: 446 trapToHype = hcr.tid3; 447 break; 448 case MISCREG_DCISW: 449 case MISCREG_DCCSW: 450 case MISCREG_DCCISW: 451 trapToHype = hcr.tsw; 452 break; 453 case MISCREG_DCIMVAC: 454 case MISCREG_DCCIMVAC: 455 case MISCREG_DCCMVAC: 456 trapToHype = hcr.tpc; 457 break; 458 case MISCREG_ICIMVAU: 459 case MISCREG_ICIALLU: 460 case MISCREG_ICIALLUIS: 461 case MISCREG_DCCMVAU: 462 trapToHype = hcr.tpu; 463 break; 464 case MISCREG_TLBIALLIS: 465 case MISCREG_TLBIMVAIS: 466 case MISCREG_TLBIASIDIS: 467 case MISCREG_TLBIMVAAIS: 468 case MISCREG_TLBIMVALIS: 469 case MISCREG_TLBIMVAALIS: 470 case MISCREG_DTLBIALL: 471 case MISCREG_ITLBIALL: 472 case MISCREG_DTLBIMVA: 473 case MISCREG_ITLBIMVA: 474 case MISCREG_DTLBIASID: 475 case MISCREG_ITLBIASID: 476 case MISCREG_TLBIMVAA: 477 case MISCREG_TLBIALL: 478 case MISCREG_TLBIMVA: 479 case MISCREG_TLBIMVAL: 480 case MISCREG_TLBIMVAAL: 481 case MISCREG_TLBIASID: 482 trapToHype = hcr.ttlb; 483 break; 484 case MISCREG_ACTLR: 485 trapToHype = hcr.tac; 486 break; 487 case MISCREG_SCTLR: 488 case MISCREG_TTBR0: 489 case MISCREG_TTBR1: 490 case MISCREG_TTBCR: 491 case MISCREG_DACR: 492 case MISCREG_DFSR: 493 case MISCREG_IFSR: 494 case MISCREG_DFAR: 495 case MISCREG_IFAR: 496 case MISCREG_ADFSR: 497 case MISCREG_AIFSR: 498 case MISCREG_PRRR: 499 case MISCREG_NMRR: 500 case MISCREG_MAIR0: 501 case MISCREG_MAIR1: 502 case MISCREG_CONTEXTIDR: 503 trapToHype = hcr.tvm & !isRead; 504 break; 505 case MISCREG_PMCR: 506 trapToHype = hdcr.tpmcr; 507 break; 508 // No default action needed 509 default: 510 break; 511 } 512 } 513 } 514 return trapToHype; 515} 516 517 518bool 519mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, 520 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss) 521{ 522 bool isRead; 523 uint32_t crm; 524 IntRegIndex rt; 525 uint32_t crn; 526 uint32_t opc1; 527 uint32_t opc2; 528 bool trapToHype = false; 529 530 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { 531 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2); 532 inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n", 533 crm, crn, opc1, opc2, hdcr, hcptr, hstr); 534 trapToHype = hdcr.tda && (opc1 == 0); 535 trapToHype |= hcptr.tta && (opc1 == 1); 536 if (!trapToHype) { 537 switch (unflattenMiscReg(miscReg)) { 538 case MISCREG_DBGOSLSR: 539 case MISCREG_DBGOSLAR: 540 case MISCREG_DBGOSDLR: 541 case MISCREG_DBGPRCR: 542 trapToHype = hdcr.tdosa; 543 break; 544 case MISCREG_DBGDRAR: 545 case MISCREG_DBGDSAR: 546 trapToHype = hdcr.tdra; 547 break; 548 case MISCREG_JIDR: 549 trapToHype = hcr.tid0; 550 break; 551 case MISCREG_JOSCR: 552 case MISCREG_JMCR: 553 trapToHype = hstr.tjdbx; 554 break; 555 case MISCREG_TEECR: 556 case MISCREG_TEEHBR: 557 trapToHype = hstr.ttee; 558 break; 559 // No default action needed 560 default: 561 break; 562 } 563 } 564 } 565 return trapToHype; 566} 567 568bool 569mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr, 570 HCR hcr, uint32_t iss) 571{ 572 uint32_t crm; 573 IntRegIndex rt; 574 uint32_t crn; 575 uint32_t opc1; 576 uint32_t opc2; 577 bool isRead; 578 bool trapToHype = false; 579 580 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { 581 // This is technically the wrong function, but we can re-use it for 582 // the moment because we only need one field, which overlaps with the 583 // mcrmrc layout 584 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2); 585 trapToHype = ((uint32_t) hstr) & (1 << crm); 586 587 if (!trapToHype) { 588 switch (unflattenMiscReg(miscReg)) { 589 case MISCREG_SCTLR: 590 case MISCREG_TTBR0: 591 case MISCREG_TTBR1: 592 case MISCREG_TTBCR: 593 case MISCREG_DACR: 594 case MISCREG_DFSR: 595 case MISCREG_IFSR: 596 case MISCREG_DFAR: 597 case MISCREG_IFAR: 598 case MISCREG_ADFSR: 599 case MISCREG_AIFSR: 600 case MISCREG_PRRR: 601 case MISCREG_NMRR: 602 case MISCREG_MAIR0: 603 case MISCREG_MAIR1: 604 case MISCREG_CONTEXTIDR: 605 trapToHype = hcr.tvm & !isRead; 606 break; 607 // No default action needed 608 default: 609 break; 610 } 611 } 612 } 613 return trapToHype; 614} 615 616bool 617msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el, 618 CPACR cpacr /* CPACR_EL1 */) 619{ 620 bool trapToSup = false; 621 switch (miscReg) { 622 case MISCREG_FPCR: 623 case MISCREG_FPSR: 624 case MISCREG_FPEXC32_EL2: 625 if ((el == EL0 && cpacr.fpen != 0x3) || 626 (el == EL1 && !(cpacr.fpen & 0x1))) 627 trapToSup = true; 628 break; 629 default: 630 break; 631 } 632 return trapToSup; 633} 634 635bool 636msrMrs64TrapToHyp(const MiscRegIndex miscReg, 637 ExceptionLevel el, 638 bool isRead, 639 CPTR cptr /* CPTR_EL2 */, 640 HCR hcr /* HCR_EL2 */, 641 bool * isVfpNeon) 642{ 643 bool trapToHyp = false; 644 *isVfpNeon = false; 645 646 switch (miscReg) { 647 // FP/SIMD regs 648 case MISCREG_FPCR: 649 case MISCREG_FPSR: 650 case MISCREG_FPEXC32_EL2: 651 trapToHyp = cptr.tfp; 652 *isVfpNeon = true; 653 break; 654 // CPACR 655 case MISCREG_CPACR_EL1: 656 trapToHyp = cptr.tcpac && el == EL1; 657 break; 658 // Virtual memory control regs 659 case MISCREG_SCTLR_EL1: 660 case MISCREG_TTBR0_EL1: 661 case MISCREG_TTBR1_EL1: 662 case MISCREG_TCR_EL1: 663 case MISCREG_ESR_EL1: 664 case MISCREG_FAR_EL1: 665 case MISCREG_AFSR0_EL1: 666 case MISCREG_AFSR1_EL1: 667 case MISCREG_MAIR_EL1: 668 case MISCREG_AMAIR_EL1: 669 case MISCREG_CONTEXTIDR_EL1: 670 trapToHyp = ((hcr.trvm && isRead) || (hcr.tvm && !isRead)) 671 && el == EL1; 672 break; 673 // TLB maintenance instructions 674 case MISCREG_TLBI_VMALLE1: 675 case MISCREG_TLBI_VAE1_Xt: 676 case MISCREG_TLBI_ASIDE1_Xt: 677 case MISCREG_TLBI_VAAE1_Xt: 678 case MISCREG_TLBI_VALE1_Xt: 679 case MISCREG_TLBI_VAALE1_Xt: 680 case MISCREG_TLBI_VMALLE1IS: 681 case MISCREG_TLBI_VAE1IS_Xt: 682 case MISCREG_TLBI_ASIDE1IS_Xt: 683 case MISCREG_TLBI_VAAE1IS_Xt: 684 case MISCREG_TLBI_VALE1IS_Xt: 685 case MISCREG_TLBI_VAALE1IS_Xt: 686 trapToHyp = hcr.ttlb && el == EL1; 687 break; 688 // Cache maintenance instructions to the point of unification 689 case MISCREG_IC_IVAU_Xt: 690 case MISCREG_ICIALLU: 691 case MISCREG_ICIALLUIS: 692 case MISCREG_DC_CVAU_Xt: 693 trapToHyp = hcr.tpu && el <= EL1; 694 break; 695 // Data/Unified cache maintenance instructions to the point of coherency 696 case MISCREG_DC_IVAC_Xt: 697 case MISCREG_DC_CIVAC_Xt: 698 case MISCREG_DC_CVAC_Xt: 699 trapToHyp = hcr.tpc && el <= EL1; 700 break; 701 // Data/Unified cache maintenance instructions by set/way 702 case MISCREG_DC_ISW_Xt: 703 case MISCREG_DC_CSW_Xt: 704 case MISCREG_DC_CISW_Xt: 705 trapToHyp = hcr.tsw && el == EL1; 706 break; 707 // ACTLR 708 case MISCREG_ACTLR_EL1: 709 trapToHyp = hcr.tacr && el == EL1; 710 break; 711 712 // @todo: Trap implementation-dependent functionality based on 713 // hcr.tidcp 714 715 // ID regs, group 3 716 case MISCREG_ID_PFR0_EL1: 717 case MISCREG_ID_PFR1_EL1: 718 case MISCREG_ID_DFR0_EL1: 719 case MISCREG_ID_AFR0_EL1: 720 case MISCREG_ID_MMFR0_EL1: 721 case MISCREG_ID_MMFR1_EL1: 722 case MISCREG_ID_MMFR2_EL1: 723 case MISCREG_ID_MMFR3_EL1: 724 case MISCREG_ID_ISAR0_EL1: 725 case MISCREG_ID_ISAR1_EL1: 726 case MISCREG_ID_ISAR2_EL1: 727 case MISCREG_ID_ISAR3_EL1: 728 case MISCREG_ID_ISAR4_EL1: 729 case MISCREG_ID_ISAR5_EL1: 730 case MISCREG_MVFR0_EL1: 731 case MISCREG_MVFR1_EL1: 732 case MISCREG_MVFR2_EL1: 733 case MISCREG_ID_AA64PFR0_EL1: 734 case MISCREG_ID_AA64PFR1_EL1: 735 case MISCREG_ID_AA64DFR0_EL1: 736 case MISCREG_ID_AA64DFR1_EL1: 737 case MISCREG_ID_AA64ISAR0_EL1: 738 case MISCREG_ID_AA64ISAR1_EL1: 739 case MISCREG_ID_AA64MMFR0_EL1: 740 case MISCREG_ID_AA64MMFR1_EL1: 741 case MISCREG_ID_AA64AFR0_EL1: 742 case MISCREG_ID_AA64AFR1_EL1: 743 assert(isRead); 744 trapToHyp = hcr.tid3 && el == EL1; 745 break; 746 // ID regs, group 2 747 case MISCREG_CTR_EL0: 748 case MISCREG_CCSIDR_EL1: 749 case MISCREG_CLIDR_EL1: 750 case MISCREG_CSSELR_EL1: 751 trapToHyp = hcr.tid2 && el <= EL1; 752 break; 753 // ID regs, group 1 754 case MISCREG_AIDR_EL1: 755 case MISCREG_REVIDR_EL1: 756 assert(isRead); 757 trapToHyp = hcr.tid1 && el == EL1; 758 break; 759 default: 760 break; 761 } 762 return trapToHyp; 763} 764 765bool 766msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr /* CPTR_EL3 */, 767 ExceptionLevel el, bool * isVfpNeon) 768{ 769 bool trapToMon = false; 770 *isVfpNeon = false; 771 772 switch (miscReg) { 773 // FP/SIMD regs 774 case MISCREG_FPCR: 775 case MISCREG_FPSR: 776 case MISCREG_FPEXC32_EL2: 777 trapToMon = cptr.tfp; 778 *isVfpNeon = true; 779 break; 780 // CPACR, CPTR 781 case MISCREG_CPACR_EL1: 782 if (el == EL1) { 783 trapToMon = cptr.tcpac; 784 } 785 break; 786 case MISCREG_CPTR_EL2: 787 if (el == EL2) { 788 trapToMon = cptr.tcpac; 789 } 790 break; 791 default: 792 break; 793 } 794 return trapToMon; 795} 796 797bool 798decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx, 799 CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity) 800{ 801 OperatingMode mode = MODE_UNDEFINED; 802 bool ok = true; 803 804 // R mostly indicates if its a int register or a misc reg, we override 805 // below if the few corner cases 806 isIntReg = !r; 807 // Loosely based on ARM ARM issue C section B9.3.10 808 if (r) { 809 switch (sysM) 810 { 811 case 0xE: 812 regIdx = MISCREG_SPSR_FIQ; 813 mode = MODE_FIQ; 814 break; 815 case 0x10: 816 regIdx = MISCREG_SPSR_IRQ; 817 mode = MODE_IRQ; 818 break; 819 case 0x12: 820 regIdx = MISCREG_SPSR_SVC; 821 mode = MODE_SVC; 822 break; 823 case 0x14: 824 regIdx = MISCREG_SPSR_ABT; 825 mode = MODE_ABORT; 826 break; 827 case 0x16: 828 regIdx = MISCREG_SPSR_UND; 829 mode = MODE_UNDEFINED; 830 break; 831 case 0x1C: 832 regIdx = MISCREG_SPSR_MON; 833 mode = MODE_MON; 834 break; 835 case 0x1E: 836 regIdx = MISCREG_SPSR_HYP; 837 mode = MODE_HYP; 838 break; 839 default: 840 ok = false; 841 break; 842 } 843 } else { 844 int sysM4To3 = bits(sysM, 4, 3); 845 846 if (sysM4To3 == 0) { 847 mode = MODE_USER; 848 regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8); 849 } else if (sysM4To3 == 1) { 850 mode = MODE_FIQ; 851 regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8); 852 } else if (sysM4To3 == 3) { 853 if (bits(sysM, 1) == 0) { 854 mode = MODE_MON; 855 regIdx = intRegInMode(mode, 14 - bits(sysM, 0)); 856 } else { 857 mode = MODE_HYP; 858 if (bits(sysM, 0) == 1) { 859 regIdx = intRegInMode(mode, 13); // R13 in HYP 860 } else { 861 isIntReg = false; 862 regIdx = MISCREG_ELR_HYP; 863 } 864 } 865 } else { // Other Banked registers 866 int sysM2 = bits(sysM, 2); 867 int sysM1 = bits(sysM, 1); 868 869 mode = (OperatingMode) ( ((sysM2 || sysM1) << 0) | 870 (1 << 1) | 871 ((sysM2 && !sysM1) << 2) | 872 ((sysM2 && sysM1) << 3) | 873 (1 << 4) ); 874 regIdx = intRegInMode(mode, 14 - bits(sysM, 0)); 875 // Don't flatten the register here. This is going to go through 876 // setIntReg() which will do the flattening 877 ok &= mode != cpsr.mode; 878 } 879 } 880 881 // Check that the requested register is accessable from the current mode 882 if (ok && checkSecurity && mode != cpsr.mode) { 883 switch (cpsr.mode) 884 { 885 case MODE_USER: 886 ok = false; 887 break; 888 case MODE_FIQ: 889 ok &= mode != MODE_HYP; 890 ok &= (mode != MODE_MON) || !scr.ns; 891 break; 892 case MODE_HYP: 893 ok &= mode != MODE_MON; 894 ok &= (mode != MODE_FIQ) || !nsacr.rfr; 895 break; 896 case MODE_IRQ: 897 case MODE_SVC: 898 case MODE_ABORT: 899 case MODE_UNDEFINED: 900 case MODE_SYSTEM: 901 ok &= mode != MODE_HYP; 902 ok &= (mode != MODE_MON) || !scr.ns; 903 ok &= (mode != MODE_FIQ) || !nsacr.rfr; 904 break; 905 // can access everything, no further checks required 906 case MODE_MON: 907 break; 908 default: 909 panic("unknown Mode 0x%x\n", cpsr.mode); 910 break; 911 } 912 } 913 return (ok); 914} 915 916bool 917SPAlignmentCheckEnabled(ThreadContext* tc) 918{ 919 switch (opModeToEL(currOpMode(tc))) { 920 case EL3: 921 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa; 922 case EL2: 923 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa; 924 case EL1: 925 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa; 926 case EL0: 927 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0; 928 default: 929 panic("Invalid exception level"); 930 break; 931 } 932} 933 934int 935decodePhysAddrRange64(uint8_t pa_enc) 936{ 937 switch (pa_enc) { 938 case 0x0: 939 return 32; 940 case 0x1: 941 return 36; 942 case 0x2: 943 return 40; 944 case 0x3: 945 return 42; 946 case 0x4: 947 return 44; 948 case 0x5: 949 case 0x6: 950 case 0x7: 951 return 48; 952 default: 953 panic("Invalid phys. address range encoding"); 954 } 955} 956 957uint8_t 958encodePhysAddrRange64(int pa_size) 959{ 960 switch (pa_size) { 961 case 32: 962 return 0x0; 963 case 36: 964 return 0x1; 965 case 40: 966 return 0x2; 967 case 42: 968 return 0x3; 969 case 44: 970 return 0x4; 971 case 48: 972 return 0x5; 973 default: 974 panic("Invalid phys. address range"); 975 } 976} 977 978} // namespace ArmISA 979