utility.cc revision 9058
16757SAli.Saidi@ARM.com/* 27650SAli.Saidi@ARM.com * Copyright (c) 2009-2010 ARM Limited 36757SAli.Saidi@ARM.com * All rights reserved. 46757SAli.Saidi@ARM.com * 57111Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67111Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77111Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87111Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97111Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107111Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117111Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127111Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137111Sgblack@eecs.umich.edu * 146757SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 156757SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 166757SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 176757SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 186757SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 196757SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 206757SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 216757SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 226757SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 236757SAli.Saidi@ARM.com * this software without specific prior written permission. 246757SAli.Saidi@ARM.com * 256757SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266757SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276757SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286757SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 296757SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 306757SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 316757SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 326757SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336757SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346757SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356757SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366757SAli.Saidi@ARM.com * 376757SAli.Saidi@ARM.com * Authors: Ali Saidi 386757SAli.Saidi@ARM.com */ 396735Sgblack@eecs.umich.edu 406757SAli.Saidi@ARM.com 416757SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 427707Sgblack@eecs.umich.edu#include "arch/arm/isa_traits.hh" 438782Sgblack@eecs.umich.edu#include "arch/arm/tlb.hh" 446757SAli.Saidi@ARM.com#include "arch/arm/utility.hh" 458782Sgblack@eecs.umich.edu#include "arch/arm/vtophys.hh" 468887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 478886SAli.Saidi@ARM.com#include "cpu/base.hh" 486757SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 498706Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh" 508782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 517749SAli.Saidi@ARM.com 526735Sgblack@eecs.umich.edunamespace ArmISA { 536735Sgblack@eecs.umich.edu 546735Sgblack@eecs.umich.eduvoid 556735Sgblack@eecs.umich.eduinitCPU(ThreadContext *tc, int cpuId) 566735Sgblack@eecs.umich.edu{ 576735Sgblack@eecs.umich.edu // Reset CP15?? What does that mean -- ali 589058Satgutier@umich.edu 596735Sgblack@eecs.umich.edu // FPEXC.EN = 0 608886SAli.Saidi@ARM.com 616757SAli.Saidi@ARM.com static Fault reset = new Reset; 628286SAli.Saidi@ARM.com reset->invoke(tc); 636735Sgblack@eecs.umich.edu} 646735Sgblack@eecs.umich.edu 657707Sgblack@eecs.umich.eduuint64_t 667707Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 677707Sgblack@eecs.umich.edu{ 688806Sgblack@eecs.umich.edu if (!FullSystem) { 698806Sgblack@eecs.umich.edu panic("getArgument() only implemented for full system mode.\n"); 708806Sgblack@eecs.umich.edu M5_DUMMY_RETURN 718806Sgblack@eecs.umich.edu } 728706Sandreas.hansson@arm.com 737707Sgblack@eecs.umich.edu if (size == (uint16_t)(-1)) 747707Sgblack@eecs.umich.edu size = ArmISA::MachineBytes; 757693SAli.Saidi@ARM.com if (fp) 767693SAli.Saidi@ARM.com panic("getArgument(): Floating point arguments not implemented\n"); 777693SAli.Saidi@ARM.com 787650SAli.Saidi@ARM.com if (number < NumArgumentRegs) { 798806Sgblack@eecs.umich.edu // If the argument is 64 bits, it must be in an even regiser 808806Sgblack@eecs.umich.edu // number. Increment the number here if it isn't even. 817693SAli.Saidi@ARM.com if (size == sizeof(uint64_t)) { 827693SAli.Saidi@ARM.com if ((number % 2) != 0) 837693SAli.Saidi@ARM.com number++; 848806Sgblack@eecs.umich.edu // Read the two halves of the data. Number is inc here to 858806Sgblack@eecs.umich.edu // get the second half of the 64 bit reg. 867693SAli.Saidi@ARM.com uint64_t tmp; 877693SAli.Saidi@ARM.com tmp = tc->readIntReg(number++); 887693SAli.Saidi@ARM.com tmp |= tc->readIntReg(number) << 32; 897693SAli.Saidi@ARM.com return tmp; 907693SAli.Saidi@ARM.com } else { 917693SAli.Saidi@ARM.com return tc->readIntReg(number); 927693SAli.Saidi@ARM.com } 937693SAli.Saidi@ARM.com } else { 947693SAli.Saidi@ARM.com Addr sp = tc->readIntReg(StackPointerReg); 958852Sandreas.hansson@arm.com FSTranslatingPortProxy &vp = tc->getVirtProxy(); 967693SAli.Saidi@ARM.com uint64_t arg; 977693SAli.Saidi@ARM.com if (size == sizeof(uint64_t)) { 987693SAli.Saidi@ARM.com // If the argument is even it must be aligned 997693SAli.Saidi@ARM.com if ((number % 2) != 0) 1007693SAli.Saidi@ARM.com number++; 1018852Sandreas.hansson@arm.com arg = vp.read<uint64_t>(sp + 1027693SAli.Saidi@ARM.com (number-NumArgumentRegs) * sizeof(uint32_t)); 1037693SAli.Saidi@ARM.com // since two 32 bit args == 1 64 bit arg, increment number 1047693SAli.Saidi@ARM.com number++; 1057693SAli.Saidi@ARM.com } else { 1068852Sandreas.hansson@arm.com arg = vp.read<uint32_t>(sp + 1077693SAli.Saidi@ARM.com (number-NumArgumentRegs) * sizeof(uint32_t)); 1087693SAli.Saidi@ARM.com } 1097693SAli.Saidi@ARM.com return arg; 1107650SAli.Saidi@ARM.com } 1116757SAli.Saidi@ARM.com} 1126757SAli.Saidi@ARM.com 1137693SAli.Saidi@ARM.comvoid 1147693SAli.Saidi@ARM.comskipFunction(ThreadContext *tc) 1157693SAli.Saidi@ARM.com{ 1167720Sgblack@eecs.umich.edu TheISA::PCState newPC = tc->pcState(); 1177720Sgblack@eecs.umich.edu newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1)); 1188887Sgeoffrey.blake@arm.com 1198887Sgeoffrey.blake@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 1208887Sgeoffrey.blake@arm.com if (checker) { 1218887Sgeoffrey.blake@arm.com tc->pcStateNoRecord(newPC); 1228887Sgeoffrey.blake@arm.com } else { 1238887Sgeoffrey.blake@arm.com tc->pcState(newPC); 1248887Sgeoffrey.blake@arm.com } 1257693SAli.Saidi@ARM.com} 1267693SAli.Saidi@ARM.com 1277748SAli.Saidi@ARM.comvoid 1287748SAli.Saidi@ARM.comcopyRegs(ThreadContext *src, ThreadContext *dest) 1297748SAli.Saidi@ARM.com{ 1307748SAli.Saidi@ARM.com int i; 1318208SAli.Saidi@ARM.com 1328208SAli.Saidi@ARM.com int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode; 1338208SAli.Saidi@ARM.com 1348208SAli.Saidi@ARM.com // Make sure we're in user mode, so we can easily see all the registers 1358208SAli.Saidi@ARM.com // in the copy loop 1368208SAli.Saidi@ARM.com src->setMiscReg(MISCREG_CPSR_MODE, MODE_USER); 1378208SAli.Saidi@ARM.com dest->setMiscReg(MISCREG_CPSR_MODE, MODE_USER); 1388208SAli.Saidi@ARM.com 1397748SAli.Saidi@ARM.com for(i = 0; i < TheISA::NumIntRegs; i++) 1407748SAli.Saidi@ARM.com dest->setIntReg(i, src->readIntReg(i)); 1418208SAli.Saidi@ARM.com 1428208SAli.Saidi@ARM.com // Restore us back to the old mode 1438208SAli.Saidi@ARM.com src->setMiscReg(MISCREG_CPSR_MODE, saved_mode); 1448208SAli.Saidi@ARM.com dest->setMiscReg(MISCREG_CPSR_MODE, saved_mode); 1458208SAli.Saidi@ARM.com 1467748SAli.Saidi@ARM.com for(i = 0; i < TheISA::NumFloatRegs; i++) 1477748SAli.Saidi@ARM.com dest->setFloatReg(i, src->readFloatReg(i)); 1487748SAli.Saidi@ARM.com for(i = 0; i < TheISA::NumMiscRegs; i++) 1497748SAli.Saidi@ARM.com dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 1506759SAli.Saidi@ARM.com 1517748SAli.Saidi@ARM.com // setMiscReg "with effect" will set the misc register mapping correctly. 1527748SAli.Saidi@ARM.com // e.g. updateRegMap(val) 1537748SAli.Saidi@ARM.com dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR)); 1547748SAli.Saidi@ARM.com 1557749SAli.Saidi@ARM.com // Copy over the PC State 1567748SAli.Saidi@ARM.com dest->pcState(src->pcState()); 1577749SAli.Saidi@ARM.com 1587749SAli.Saidi@ARM.com // Invalidate the tlb misc register cache 1597749SAli.Saidi@ARM.com dest->getITBPtr()->invalidateMiscReg(); 1607749SAli.Saidi@ARM.com dest->getDTBPtr()->invalidateMiscReg(); 1616759SAli.Saidi@ARM.com} 1627752SWilliam.Wang@arm.com 1637752SWilliam.Wang@arm.comAddr 1647752SWilliam.Wang@arm.comtruncPage(Addr addr) 1657752SWilliam.Wang@arm.com{ 1667752SWilliam.Wang@arm.com return addr & ~(PageBytes - 1); 1677748SAli.Saidi@ARM.com} 1687752SWilliam.Wang@arm.com 1697752SWilliam.Wang@arm.comAddr 1707752SWilliam.Wang@arm.comroundPage(Addr addr) 1717752SWilliam.Wang@arm.com{ 1727752SWilliam.Wang@arm.com return (addr + PageBytes - 1) & ~(PageBytes - 1); 1737752SWilliam.Wang@arm.com} 1747752SWilliam.Wang@arm.com 1757752SWilliam.Wang@arm.com} // namespace ArmISA 176