utility.cc revision 7720
16757SAli.Saidi@ARM.com/* 27650SAli.Saidi@ARM.com * Copyright (c) 2009-2010 ARM Limited 36757SAli.Saidi@ARM.com * All rights reserved. 46757SAli.Saidi@ARM.com * 57111Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67111Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77111Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87111Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97111Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107111Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117111Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127111Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137111Sgblack@eecs.umich.edu * 146757SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 156757SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 166757SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 176757SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 186757SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 196757SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 206757SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 216757SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 226757SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 236757SAli.Saidi@ARM.com * this software without specific prior written permission. 246757SAli.Saidi@ARM.com * 256757SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266757SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276757SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286757SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 296757SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 306757SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 316757SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 326757SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336757SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346757SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356757SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366757SAli.Saidi@ARM.com * 376757SAli.Saidi@ARM.com * Authors: Ali Saidi 386757SAli.Saidi@ARM.com */ 396735Sgblack@eecs.umich.edu 406757SAli.Saidi@ARM.com 416757SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 427707Sgblack@eecs.umich.edu#include "arch/arm/isa_traits.hh" 436757SAli.Saidi@ARM.com#include "arch/arm/utility.hh" 446757SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 456735Sgblack@eecs.umich.edu 467693SAli.Saidi@ARM.com#if FULL_SYSTEM 477693SAli.Saidi@ARM.com#include "arch/arm/vtophys.hh" 487693SAli.Saidi@ARM.com#include "mem/vport.hh" 497693SAli.Saidi@ARM.com#endif 506735Sgblack@eecs.umich.edu 516735Sgblack@eecs.umich.edunamespace ArmISA { 526735Sgblack@eecs.umich.edu 536735Sgblack@eecs.umich.eduvoid 546735Sgblack@eecs.umich.eduinitCPU(ThreadContext *tc, int cpuId) 556735Sgblack@eecs.umich.edu{ 566735Sgblack@eecs.umich.edu // Reset CP15?? What does that mean -- ali 576735Sgblack@eecs.umich.edu 586735Sgblack@eecs.umich.edu // FPEXC.EN = 0 596735Sgblack@eecs.umich.edu 606757SAli.Saidi@ARM.com static Fault reset = new Reset; 616735Sgblack@eecs.umich.edu if (cpuId == 0) 626735Sgblack@eecs.umich.edu reset->invoke(tc); 636735Sgblack@eecs.umich.edu} 646735Sgblack@eecs.umich.edu 657707Sgblack@eecs.umich.eduuint64_t 667707Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 677707Sgblack@eecs.umich.edu{ 686757SAli.Saidi@ARM.com#if FULL_SYSTEM 697707Sgblack@eecs.umich.edu if (size == (uint16_t)(-1)) 707707Sgblack@eecs.umich.edu size = ArmISA::MachineBytes; 717693SAli.Saidi@ARM.com if (fp) 727693SAli.Saidi@ARM.com panic("getArgument(): Floating point arguments not implemented\n"); 737693SAli.Saidi@ARM.com 747650SAli.Saidi@ARM.com if (number < NumArgumentRegs) { 757693SAli.Saidi@ARM.com // If the argument is 64 bits, it must be in an even regiser number 767693SAli.Saidi@ARM.com // Increment the number here if it isn't even 777693SAli.Saidi@ARM.com if (size == sizeof(uint64_t)) { 787693SAli.Saidi@ARM.com if ((number % 2) != 0) 797693SAli.Saidi@ARM.com number++; 807693SAli.Saidi@ARM.com // Read the two halves of the data 817693SAli.Saidi@ARM.com // number is inc here to get the second half of the 64 bit reg 827693SAli.Saidi@ARM.com uint64_t tmp; 837693SAli.Saidi@ARM.com tmp = tc->readIntReg(number++); 847693SAli.Saidi@ARM.com tmp |= tc->readIntReg(number) << 32; 857693SAli.Saidi@ARM.com return tmp; 867693SAli.Saidi@ARM.com } else { 877693SAli.Saidi@ARM.com return tc->readIntReg(number); 887693SAli.Saidi@ARM.com } 897693SAli.Saidi@ARM.com } else { 907693SAli.Saidi@ARM.com Addr sp = tc->readIntReg(StackPointerReg); 917693SAli.Saidi@ARM.com VirtualPort *vp = tc->getVirtPort(); 927693SAli.Saidi@ARM.com uint64_t arg; 937693SAli.Saidi@ARM.com if (size == sizeof(uint64_t)) { 947693SAli.Saidi@ARM.com // If the argument is even it must be aligned 957693SAli.Saidi@ARM.com if ((number % 2) != 0) 967693SAli.Saidi@ARM.com number++; 977693SAli.Saidi@ARM.com arg = vp->read<uint64_t>(sp + 987693SAli.Saidi@ARM.com (number-NumArgumentRegs) * sizeof(uint32_t)); 997693SAli.Saidi@ARM.com // since two 32 bit args == 1 64 bit arg, increment number 1007693SAli.Saidi@ARM.com number++; 1017693SAli.Saidi@ARM.com } else { 1027693SAli.Saidi@ARM.com arg = vp->read<uint32_t>(sp + 1037693SAli.Saidi@ARM.com (number-NumArgumentRegs) * sizeof(uint32_t)); 1047693SAli.Saidi@ARM.com } 1057693SAli.Saidi@ARM.com return arg; 1067650SAli.Saidi@ARM.com } 1076757SAli.Saidi@ARM.com#else 1086757SAli.Saidi@ARM.com panic("getArgument() only implemented for FULL_SYSTEM\n"); 1096757SAli.Saidi@ARM.com M5_DUMMY_RETURN 1106757SAli.Saidi@ARM.com#endif 1116757SAli.Saidi@ARM.com} 1126757SAli.Saidi@ARM.com 1136759SAli.Saidi@ARM.comFault 1146759SAli.Saidi@ARM.comsetCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2) 1156759SAli.Saidi@ARM.com{ 1166759SAli.Saidi@ARM.com return new UnimpFault(csprintf("MCR CP15: CRn: %d opc1: %d CRm: %d opc1: %d\n", 1176759SAli.Saidi@ARM.com CRn, opc1, CRm, opc2)); 1186757SAli.Saidi@ARM.com} 1196759SAli.Saidi@ARM.com 1206759SAli.Saidi@ARM.comFault 1216759SAli.Saidi@ARM.comreadCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2) 1226759SAli.Saidi@ARM.com{ 1236759SAli.Saidi@ARM.com return new UnimpFault(csprintf("MRC CP15: CRn: %d opc1: %d CRm: %d opc1: %d\n", 1246759SAli.Saidi@ARM.com CRn, opc1, CRm, opc2)); 1256759SAli.Saidi@ARM.com 1266759SAli.Saidi@ARM.com} 1276759SAli.Saidi@ARM.com 1287693SAli.Saidi@ARM.comvoid 1297693SAli.Saidi@ARM.comskipFunction(ThreadContext *tc) 1307693SAli.Saidi@ARM.com{ 1317720Sgblack@eecs.umich.edu TheISA::PCState newPC = tc->pcState(); 1327720Sgblack@eecs.umich.edu newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1)); 1337720Sgblack@eecs.umich.edu tc->pcState(newPC); 1347693SAli.Saidi@ARM.com} 1357693SAli.Saidi@ARM.com 1366759SAli.Saidi@ARM.com 1376759SAli.Saidi@ARM.com} 138