types.hh revision 7103:844dbc22e3cb
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_TYPES_HH__ 44#define __ARCH_ARM_TYPES_HH__ 45 46#include "base/bitunion.hh" 47#include "base/types.hh" 48 49namespace ArmISA 50{ 51 typedef uint32_t MachInst; 52 53 BitUnion64(ExtMachInst) 54 // Bitfields to select mode. 55 Bitfield<36> thumb; 56 Bitfield<35> bigThumb; 57 58 // Made up bitfields that make life easier. 59 Bitfield<33> sevenAndFour; 60 Bitfield<32> isMisc; 61 62 uint32_t instBits; 63 64 // All the different types of opcode fields. 65 Bitfield<27, 25> encoding; 66 Bitfield<25> useImm; 67 Bitfield<24, 21> opcode; 68 Bitfield<24, 20> mediaOpcode; 69 Bitfield<24> opcode24; 70 Bitfield<23, 20> opcode23_20; 71 Bitfield<23, 21> opcode23_21; 72 Bitfield<20> opcode20; 73 Bitfield<22> opcode22; 74 Bitfield<19> opcode19; 75 Bitfield<18> opcode18; 76 Bitfield<15, 12> opcode15_12; 77 Bitfield<15> opcode15; 78 Bitfield<7, 4> miscOpcode; 79 Bitfield<7,5> opc2; 80 Bitfield<7> opcode7; 81 Bitfield<4> opcode4; 82 83 Bitfield<31, 28> condCode; 84 Bitfield<20> sField; 85 Bitfield<19, 16> rn; 86 Bitfield<15, 12> rd; 87 Bitfield<11, 7> shiftSize; 88 Bitfield<6, 5> shift; 89 Bitfield<3, 0> rm; 90 91 Bitfield<11, 8> rs; 92 93 SubBitUnion(puswl, 24, 20) 94 Bitfield<24> prepost; 95 Bitfield<23> up; 96 Bitfield<22> psruser; 97 Bitfield<21> writeback; 98 Bitfield<20> loadOp; 99 EndSubBitUnion(puswl) 100 101 Bitfield<24, 20> pubwl; 102 103 Bitfield<7, 0> imm; 104 105 Bitfield<11, 8> rotate; 106 107 Bitfield<11, 0> immed11_0; 108 Bitfield<7, 0> immed7_0; 109 110 Bitfield<11, 8> immedHi11_8; 111 Bitfield<3, 0> immedLo3_0; 112 113 Bitfield<15, 0> regList; 114 115 Bitfield<23, 0> offset; 116 117 Bitfield<23, 0> immed23_0; 118 119 Bitfield<11, 8> cpNum; 120 Bitfield<18, 16> fn; 121 Bitfield<14, 12> fd; 122 Bitfield<3> fpRegImm; 123 Bitfield<3, 0> fm; 124 Bitfield<2, 0> fpImm; 125 Bitfield<24, 20> punwl; 126 127 Bitfield<7, 0> m5Func; 128 129 // 16 bit thumb bitfields 130 Bitfield<15, 13> topcode15_13; 131 Bitfield<13, 11> topcode13_11; 132 Bitfield<12, 11> topcode12_11; 133 Bitfield<12, 10> topcode12_10; 134 Bitfield<11, 9> topcode11_9; 135 Bitfield<11, 8> topcode11_8; 136 Bitfield<10, 9> topcode10_9; 137 Bitfield<10, 8> topcode10_8; 138 Bitfield<9, 6> topcode9_6; 139 Bitfield<7> topcode7; 140 Bitfield<7, 6> topcode7_6; 141 Bitfield<7, 5> topcode7_5; 142 Bitfield<7, 4> topcode7_4; 143 Bitfield<3, 0> topcode3_0; 144 EndBitUnion(ExtMachInst) 145 146 // Shift types for ARM instructions 147 enum ArmShiftType { 148 LSL = 0, 149 LSR, 150 ASR, 151 ROR 152 }; 153 154 typedef uint64_t LargestRead; 155 // Need to use 64 bits to make sure that read requests get handled properly 156 157 typedef int RegContextParam; 158 typedef int RegContextVal; 159 160 //used in FP convert & round function 161 enum ConvertType{ 162 SINGLE_TO_DOUBLE, 163 SINGLE_TO_WORD, 164 SINGLE_TO_LONG, 165 166 DOUBLE_TO_SINGLE, 167 DOUBLE_TO_WORD, 168 DOUBLE_TO_LONG, 169 170 LONG_TO_SINGLE, 171 LONG_TO_DOUBLE, 172 LONG_TO_WORD, 173 LONG_TO_PS, 174 175 WORD_TO_SINGLE, 176 WORD_TO_DOUBLE, 177 WORD_TO_LONG, 178 WORD_TO_PS, 179 180 PL_TO_SINGLE, 181 PU_TO_SINGLE 182 }; 183 184 //used in FP convert & round function 185 enum RoundMode{ 186 RND_ZERO, 187 RND_DOWN, 188 RND_UP, 189 RND_NEAREST 190 }; 191 192 enum OperatingMode { 193 MODE_USER = 16, 194 MODE_FIQ = 17, 195 MODE_IRQ = 18, 196 MODE_SVC = 19, 197 MODE_MON = 22, 198 MODE_ABORT = 23, 199 MODE_UNDEFINED = 27, 200 MODE_SYSTEM = 31 201 }; 202 203 struct CoreSpecific { 204 // Empty for now on the ARM 205 }; 206 207} // namespace ArmISA 208 209#endif 210