types.hh revision 6267:f5edd0f709e4 
1/*
2 * Copyright (c) 2007-2008 The Florida State University
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Stephen Hines
29 */
30
31#ifndef __ARCH_ARM_TYPES_HH__
32#define __ARCH_ARM_TYPES_HH__
33
34#include "base/bitunion.hh"
35#include "base/types.hh"
36
37namespace ArmISA
38{
39    typedef uint32_t MachInst;
40
41    BitUnion64(ExtMachInst)
42        // Made up bitfields that make life easier.
43        Bitfield<33>     sevenAndFour;
44        Bitfield<32>     isMisc;
45
46        // All the different types of opcode fields.
47        Bitfield<27, 25> opcode;
48        Bitfield<27, 25> opcode27_25;
49        Bitfield<24, 21> opcode24_21;
50        Bitfield<24, 23> opcode24_23;
51        Bitfield<24>     opcode24;
52        Bitfield<23, 20> opcode23_20;
53        Bitfield<23, 21> opcode23_21;
54        Bitfield<23>     opcode23;
55        Bitfield<22, 8>  opcode22_8;
56        Bitfield<22, 21> opcode22_21;
57        Bitfield<22>     opcode22;
58        Bitfield<21, 20> opcode21_20;
59        Bitfield<20>     opcode20;
60        Bitfield<19, 18> opcode19_18;
61        Bitfield<19>     opcode19;
62        Bitfield<15, 12> opcode15_12;
63        Bitfield<15>     opcode15;
64        Bitfield<9>      opcode9;
65        Bitfield<7,  4>  opcode7_4;
66        Bitfield<7,  5>  opcode7_5;
67        Bitfield<7,  6>  opcode7_6;
68        Bitfield<7>      opcode7;
69        Bitfield<6,  5>  opcode6_5;
70        Bitfield<6>      opcode6;
71        Bitfield<5>      opcode5;
72        Bitfield<4>      opcode4;
73
74        Bitfield<31, 28> condCode;
75        Bitfield<20>     sField;
76        Bitfield<19, 16> rn;
77        Bitfield<15, 12> rd;
78        Bitfield<11, 7>  shiftSize;
79        Bitfield<6,  5>  shift;
80        Bitfield<3,  0>  rm;
81
82        Bitfield<11, 8>  rs;
83
84        Bitfield<19, 16> rdup;
85        Bitfield<15, 12> rddn;
86
87        Bitfield<15, 12> rdhi;
88        Bitfield<11, 8>  rdlo;
89
90        Bitfield<23>     uField;
91
92        SubBitUnion(puswl, 24, 20)
93            Bitfield<24> prepost;
94            Bitfield<23> up;
95            Bitfield<22> psruser;
96            Bitfield<21> writeback;
97            Bitfield<20> loadOp;
98        EndSubBitUnion(puswl)
99
100        Bitfield<24, 20> pubwl;
101        Bitfield<24, 20> puiwl;
102        Bitfield<22>     byteAccess;
103
104        Bitfield<23, 20> luas;
105
106        SubBitUnion(imm, 7, 0)
107            Bitfield<7, 4> imm7_4;
108            Bitfield<3, 0> imm3_0;
109        EndSubBitUnion(imm)
110
111        SubBitUnion(msr, 19, 16)
112            Bitfield<19> f;
113            Bitfield<18> s;
114            Bitfield<17> x;
115            Bitfield<16> c;
116        EndSubBitUnion(msr)
117
118        Bitfield<6>      y;
119        Bitfield<5>      x;
120
121        Bitfield<15, 4>  immed15_4;
122
123        Bitfield<21>     wField;
124
125        Bitfield<11, 8>  rotate;
126        Bitfield<7,  0>  immed7_0;
127
128        Bitfield<21>     tField;
129        Bitfield<11, 0>  immed11_0;
130
131        Bitfield<20, 16> immed20_16;
132        Bitfield<19, 16> immed19_16;
133
134        Bitfield<11, 8>  immedHi11_8;
135        Bitfield<3,  0>  immedLo3_0;
136
137        Bitfield<11, 10> rot;
138
139        Bitfield<5>      rField;
140
141        Bitfield<22>     caret;
142        Bitfield<15, 0>  regList;
143
144        Bitfield<23, 0>  offset;
145        Bitfield<11, 8>  copro;
146        Bitfield<7,  4>  op1_7_4;
147        Bitfield<3,  0>  cm;
148
149        Bitfield<22>     lField;
150        Bitfield<15, 12> cd;
151        Bitfield<7,  0>  option;
152
153        Bitfield<23, 20> op1_23_20;
154        Bitfield<19, 16> cn;
155        Bitfield<7,  5>  op2_7_5;
156
157        Bitfield<23, 21> op1_23_21;
158
159        Bitfield<23, 0>  immed23_0;
160        Bitfield<17>     mField;
161        Bitfield<8>      aField;
162        Bitfield<7>      iField;
163        Bitfield<6>      fField;
164        Bitfield<4,  0>  mode;
165
166        Bitfield<24>     aBlx;
167
168        Bitfield<11, 8>  cpNum;
169        Bitfield<18, 16> fn;
170        Bitfield<14, 12> fd;
171        Bitfield<3>      fpRegImm;
172        Bitfield<3,  0>  fm;
173        Bitfield<2,  0>  fpImm;
174        Bitfield<24, 20> punwl;
175
176        Bitfield<7,  0>  m5Func;
177    EndBitUnion(ExtMachInst)
178
179    // Shift types for ARM instructions
180    enum ArmShiftType {
181        LSL = 0,
182        LSR,
183        ASR,
184        ROR
185    };
186
187    typedef uint8_t  RegIndex;
188
189    typedef uint64_t IntReg;
190    typedef uint64_t LargestRead;
191    // Need to use 64 bits to make sure that read requests get handled properly
192
193    // floating point register file entry type
194    typedef uint32_t FloatReg32;
195    typedef uint64_t FloatReg64;
196    typedef uint64_t FloatRegBits;
197
198    typedef double FloatRegVal;
199    typedef double FloatReg;
200
201    // cop-0/cop-1 system control register
202    typedef uint64_t MiscReg;
203
204    typedef union {
205        IntReg   intreg;
206        FloatReg fpreg;
207        MiscReg  ctrlreg;
208    } AnyReg;
209
210    typedef int RegContextParam;
211    typedef int RegContextVal;
212
213    //used in FP convert & round function
214    enum ConvertType{
215        SINGLE_TO_DOUBLE,
216        SINGLE_TO_WORD,
217        SINGLE_TO_LONG,
218
219        DOUBLE_TO_SINGLE,
220        DOUBLE_TO_WORD,
221        DOUBLE_TO_LONG,
222
223        LONG_TO_SINGLE,
224        LONG_TO_DOUBLE,
225        LONG_TO_WORD,
226        LONG_TO_PS,
227
228        WORD_TO_SINGLE,
229        WORD_TO_DOUBLE,
230        WORD_TO_LONG,
231        WORD_TO_PS,
232
233        PL_TO_SINGLE,
234        PU_TO_SINGLE
235    };
236
237    //used in FP convert & round function
238    enum RoundMode{
239        RND_ZERO,
240        RND_DOWN,
241        RND_UP,
242        RND_NEAREST
243    };
244
245    enum OperatingMode {
246        MODE_USER = 16,
247        MODE_FIQ = 17,
248        MODE_IRQ = 18,
249        MODE_SVC = 19,
250        MODE_ABORT = 23,
251        MODE_UNDEFINED = 27,
252        MODE_SYSTEM = 31
253    };
254
255    struct CoreSpecific {
256        // Empty for now on the ARM
257    };
258
259} // namespace ArmISA
260
261#endif
262