types.hh revision 12763:37c243ed1112
1/* 2 * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_TYPES_HH__ 44#define __ARCH_ARM_TYPES_HH__ 45 46#include "arch/generic/types.hh" 47#include "base/bitunion.hh" 48#include "base/logging.hh" 49#include "base/types.hh" 50#include "debug/Decoder.hh" 51 52namespace ArmISA 53{ 54 typedef uint32_t MachInst; 55 56 BitUnion8(ITSTATE) 57 /* Note that the split (cond, mask) below is not as in ARM ARM. 58 * But it is more convenient for simulation. The condition 59 * is always the concatenation of the top 3 bits and the next bit, 60 * which applies when one of the bottom 4 bits is set. 61 * Refer to predecoder.cc for the use case. 62 */ 63 Bitfield<7, 4> cond; 64 Bitfield<3, 0> mask; 65 // Bitfields for moving to/from CPSR 66 Bitfield<7, 2> top6; 67 Bitfield<1, 0> bottom2; 68 EndBitUnion(ITSTATE) 69 70 BitUnion64(ExtMachInst) 71 // Decoder state 72 Bitfield<63, 62> decoderFault; // See DecoderFault 73 Bitfield<61> illegalExecution; 74 75 // ITSTATE bits 76 Bitfield<55, 48> itstate; 77 Bitfield<55, 52> itstateCond; 78 Bitfield<51, 48> itstateMask; 79 80 // FPSCR fields 81 Bitfield<41, 40> fpscrStride; 82 Bitfield<39, 37> fpscrLen; 83 84 // Bitfields to select mode. 85 Bitfield<36> thumb; 86 Bitfield<35> bigThumb; 87 Bitfield<34> aarch64; 88 89 // Made up bitfields that make life easier. 90 Bitfield<33> sevenAndFour; 91 Bitfield<32> isMisc; 92 93 uint32_t instBits; 94 95 // All the different types of opcode fields. 96 Bitfield<27, 25> encoding; 97 Bitfield<25> useImm; 98 Bitfield<24, 21> opcode; 99 Bitfield<24, 20> mediaOpcode; 100 Bitfield<24> opcode24; 101 Bitfield<24, 23> opcode24_23; 102 Bitfield<23, 20> opcode23_20; 103 Bitfield<23, 21> opcode23_21; 104 Bitfield<20> opcode20; 105 Bitfield<22> opcode22; 106 Bitfield<19, 16> opcode19_16; 107 Bitfield<19> opcode19; 108 Bitfield<18> opcode18; 109 Bitfield<15, 12> opcode15_12; 110 Bitfield<15> opcode15; 111 Bitfield<7, 4> miscOpcode; 112 Bitfield<7,5> opc2; 113 Bitfield<7> opcode7; 114 Bitfield<6> opcode6; 115 Bitfield<4> opcode4; 116 117 Bitfield<31, 28> condCode; 118 Bitfield<20> sField; 119 Bitfield<19, 16> rn; 120 Bitfield<15, 12> rd; 121 Bitfield<15, 12> rt; 122 Bitfield<11, 7> shiftSize; 123 Bitfield<6, 5> shift; 124 Bitfield<3, 0> rm; 125 126 Bitfield<11, 8> rs; 127 128 SubBitUnion(puswl, 24, 20) 129 Bitfield<24> prepost; 130 Bitfield<23> up; 131 Bitfield<22> psruser; 132 Bitfield<21> writeback; 133 Bitfield<20> loadOp; 134 EndSubBitUnion(puswl) 135 136 Bitfield<24, 20> pubwl; 137 138 Bitfield<7, 0> imm; 139 140 Bitfield<11, 8> rotate; 141 142 Bitfield<11, 0> immed11_0; 143 Bitfield<7, 0> immed7_0; 144 145 Bitfield<11, 8> immedHi11_8; 146 Bitfield<3, 0> immedLo3_0; 147 148 Bitfield<15, 0> regList; 149 150 Bitfield<23, 0> offset; 151 152 Bitfield<23, 0> immed23_0; 153 154 Bitfield<11, 8> cpNum; 155 Bitfield<18, 16> fn; 156 Bitfield<14, 12> fd; 157 Bitfield<3> fpRegImm; 158 Bitfield<3, 0> fm; 159 Bitfield<2, 0> fpImm; 160 Bitfield<24, 20> punwl; 161 162 Bitfield<15, 8> m5Func; 163 164 // 16 bit thumb bitfields 165 Bitfield<15, 13> topcode15_13; 166 Bitfield<13, 11> topcode13_11; 167 Bitfield<12, 11> topcode12_11; 168 Bitfield<12, 10> topcode12_10; 169 Bitfield<11, 9> topcode11_9; 170 Bitfield<11, 8> topcode11_8; 171 Bitfield<10, 9> topcode10_9; 172 Bitfield<10, 8> topcode10_8; 173 Bitfield<9, 6> topcode9_6; 174 Bitfield<7> topcode7; 175 Bitfield<7, 6> topcode7_6; 176 Bitfield<7, 5> topcode7_5; 177 Bitfield<7, 4> topcode7_4; 178 Bitfield<3, 0> topcode3_0; 179 180 // 32 bit thumb bitfields 181 Bitfield<28, 27> htopcode12_11; 182 Bitfield<26, 25> htopcode10_9; 183 Bitfield<25> htopcode9; 184 Bitfield<25, 24> htopcode9_8; 185 Bitfield<25, 21> htopcode9_5; 186 Bitfield<25, 20> htopcode9_4; 187 Bitfield<24> htopcode8; 188 Bitfield<24, 23> htopcode8_7; 189 Bitfield<24, 22> htopcode8_6; 190 Bitfield<24, 21> htopcode8_5; 191 Bitfield<23> htopcode7; 192 Bitfield<23, 21> htopcode7_5; 193 Bitfield<22> htopcode6; 194 Bitfield<22, 21> htopcode6_5; 195 Bitfield<21, 20> htopcode5_4; 196 Bitfield<20> htopcode4; 197 198 Bitfield<19, 16> htrn; 199 Bitfield<20> hts; 200 201 Bitfield<15> ltopcode15; 202 Bitfield<11, 8> ltopcode11_8; 203 Bitfield<7, 6> ltopcode7_6; 204 Bitfield<7, 4> ltopcode7_4; 205 Bitfield<4> ltopcode4; 206 207 Bitfield<11, 8> ltrd; 208 Bitfield<11, 8> ltcoproc; 209 EndBitUnion(ExtMachInst) 210 211 class PCState : public GenericISA::UPCState<MachInst> 212 { 213 protected: 214 215 typedef GenericISA::UPCState<MachInst> Base; 216 217 enum FlagBits { 218 ThumbBit = (1 << 0), 219 JazelleBit = (1 << 1), 220 AArch64Bit = (1 << 2) 221 }; 222 223 uint8_t flags; 224 uint8_t nextFlags; 225 uint8_t _itstate; 226 uint8_t _nextItstate; 227 uint8_t _size; 228 bool _illegalExec; 229 public: 230 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0), 231 _size(0), _illegalExec(false) 232 {} 233 234 void 235 set(Addr val) 236 { 237 Base::set(val); 238 npc(val + (thumb() ? 2 : 4)); 239 } 240 241 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), 242 _nextItstate(0), _size(0), _illegalExec(false) 243 { set(val); } 244 245 bool 246 illegalExec() const 247 { 248 return _illegalExec; 249 } 250 251 void 252 illegalExec(bool val) 253 { 254 _illegalExec = val; 255 } 256 257 bool 258 thumb() const 259 { 260 return flags & ThumbBit; 261 } 262 263 void 264 thumb(bool val) 265 { 266 if (val) 267 flags |= ThumbBit; 268 else 269 flags &= ~ThumbBit; 270 } 271 272 bool 273 nextThumb() const 274 { 275 return nextFlags & ThumbBit; 276 } 277 278 void 279 nextThumb(bool val) 280 { 281 if (val) 282 nextFlags |= ThumbBit; 283 else 284 nextFlags &= ~ThumbBit; 285 } 286 287 void size(uint8_t s) { _size = s; } 288 uint8_t size() const { return _size; } 289 290 bool 291 branching() const 292 { 293 return ((this->pc() + this->size()) != this->npc()); 294 } 295 296 297 bool 298 jazelle() const 299 { 300 return flags & JazelleBit; 301 } 302 303 void 304 jazelle(bool val) 305 { 306 if (val) 307 flags |= JazelleBit; 308 else 309 flags &= ~JazelleBit; 310 } 311 312 bool 313 nextJazelle() const 314 { 315 return nextFlags & JazelleBit; 316 } 317 318 void 319 nextJazelle(bool val) 320 { 321 if (val) 322 nextFlags |= JazelleBit; 323 else 324 nextFlags &= ~JazelleBit; 325 } 326 327 bool 328 aarch64() const 329 { 330 return flags & AArch64Bit; 331 } 332 333 void 334 aarch64(bool val) 335 { 336 if (val) 337 flags |= AArch64Bit; 338 else 339 flags &= ~AArch64Bit; 340 } 341 342 bool 343 nextAArch64() const 344 { 345 return nextFlags & AArch64Bit; 346 } 347 348 void 349 nextAArch64(bool val) 350 { 351 if (val) 352 nextFlags |= AArch64Bit; 353 else 354 nextFlags &= ~AArch64Bit; 355 } 356 357 358 uint8_t 359 itstate() const 360 { 361 return _itstate; 362 } 363 364 void 365 itstate(uint8_t value) 366 { 367 _itstate = value; 368 } 369 370 uint8_t 371 nextItstate() const 372 { 373 return _nextItstate; 374 } 375 376 void 377 nextItstate(uint8_t value) 378 { 379 _nextItstate = value; 380 } 381 382 void 383 advance() 384 { 385 Base::advance(); 386 flags = nextFlags; 387 npc(pc() + (thumb() ? 2 : 4)); 388 389 if (_nextItstate) { 390 _itstate = _nextItstate; 391 _nextItstate = 0; 392 } else if (_itstate) { 393 ITSTATE it = _itstate; 394 uint8_t cond_mask = it.mask; 395 uint8_t thumb_cond = it.cond; 396 DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n", 397 thumb_cond, cond_mask); 398 cond_mask <<= 1; 399 uint8_t new_bit = bits(cond_mask, 4); 400 cond_mask &= mask(4); 401 if (cond_mask == 0) 402 thumb_cond = 0; 403 else 404 replaceBits(thumb_cond, 0, new_bit); 405 DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n", 406 thumb_cond, cond_mask); 407 it.mask = cond_mask; 408 it.cond = thumb_cond; 409 _itstate = it; 410 } 411 } 412 413 void 414 uEnd() 415 { 416 advance(); 417 upc(0); 418 nupc(1); 419 } 420 421 Addr 422 instPC() const 423 { 424 return pc() + (thumb() ? 4 : 8); 425 } 426 427 void 428 instNPC(Addr val) 429 { 430 // @todo: review this when AArch32/64 interprocessing is 431 // supported 432 if (aarch64()) 433 npc(val); // AArch64 doesn't force PC alignment, a PC 434 // Alignment Fault can be raised instead 435 else 436 npc(val &~ mask(nextThumb() ? 1 : 2)); 437 } 438 439 Addr 440 instNPC() const 441 { 442 return npc(); 443 } 444 445 // Perform an interworking branch. 446 void 447 instIWNPC(Addr val) 448 { 449 bool thumbEE = (thumb() && jazelle()); 450 451 Addr newPC = val; 452 if (thumbEE) { 453 if (bits(newPC, 0)) { 454 newPC = newPC & ~mask(1); 455 } // else we have a bad interworking address; do not call 456 // panic() since the instruction could be executed 457 // speculatively 458 } else { 459 if (bits(newPC, 0)) { 460 nextThumb(true); 461 newPC = newPC & ~mask(1); 462 } else if (!bits(newPC, 1)) { 463 nextThumb(false); 464 } else { 465 // This state is UNPREDICTABLE in the ARM architecture 466 // The easy thing to do is just mask off the bit and 467 // stay in the current mode, so we'll do that. 468 newPC &= ~mask(2); 469 } 470 } 471 npc(newPC); 472 } 473 474 // Perform an interworking branch in ARM mode, a regular branch 475 // otherwise. 476 void 477 instAIWNPC(Addr val) 478 { 479 if (!thumb() && !jazelle()) 480 instIWNPC(val); 481 else 482 instNPC(val); 483 } 484 485 bool 486 operator == (const PCState &opc) const 487 { 488 return Base::operator == (opc) && 489 flags == opc.flags && nextFlags == opc.nextFlags && 490 _itstate == opc._itstate && 491 _nextItstate == opc._nextItstate && 492 _illegalExec == opc._illegalExec; 493 } 494 495 bool 496 operator != (const PCState &opc) const 497 { 498 return !(*this == opc); 499 } 500 501 void 502 serialize(CheckpointOut &cp) const override 503 { 504 Base::serialize(cp); 505 SERIALIZE_SCALAR(flags); 506 SERIALIZE_SCALAR(_size); 507 SERIALIZE_SCALAR(nextFlags); 508 SERIALIZE_SCALAR(_itstate); 509 SERIALIZE_SCALAR(_nextItstate); 510 SERIALIZE_SCALAR(_illegalExec); 511 } 512 513 void 514 unserialize(CheckpointIn &cp) override 515 { 516 Base::unserialize(cp); 517 UNSERIALIZE_SCALAR(flags); 518 UNSERIALIZE_SCALAR(_size); 519 UNSERIALIZE_SCALAR(nextFlags); 520 UNSERIALIZE_SCALAR(_itstate); 521 UNSERIALIZE_SCALAR(_nextItstate); 522 UNSERIALIZE_SCALAR(_illegalExec); 523 } 524 }; 525 526 // Shift types for ARM instructions 527 enum ArmShiftType { 528 LSL = 0, 529 LSR, 530 ASR, 531 ROR 532 }; 533 534 // Extension types for ARM instructions 535 enum ArmExtendType { 536 UXTB = 0, 537 UXTH = 1, 538 UXTW = 2, 539 UXTX = 3, 540 SXTB = 4, 541 SXTH = 5, 542 SXTW = 6, 543 SXTX = 7 544 }; 545 546 typedef int RegContextParam; 547 typedef int RegContextVal; 548 549 //used in FP convert & round function 550 enum ConvertType{ 551 SINGLE_TO_DOUBLE, 552 SINGLE_TO_WORD, 553 SINGLE_TO_LONG, 554 555 DOUBLE_TO_SINGLE, 556 DOUBLE_TO_WORD, 557 DOUBLE_TO_LONG, 558 559 LONG_TO_SINGLE, 560 LONG_TO_DOUBLE, 561 LONG_TO_WORD, 562 LONG_TO_PS, 563 564 WORD_TO_SINGLE, 565 WORD_TO_DOUBLE, 566 WORD_TO_LONG, 567 WORD_TO_PS, 568 569 PL_TO_SINGLE, 570 PU_TO_SINGLE 571 }; 572 573 //used in FP convert & round function 574 enum RoundMode{ 575 RND_ZERO, 576 RND_DOWN, 577 RND_UP, 578 RND_NEAREST 579 }; 580 581 enum ExceptionLevel { 582 EL0 = 0, 583 EL1, 584 EL2, 585 EL3 586 }; 587 588 enum OperatingMode { 589 MODE_EL0T = 0x0, 590 MODE_EL1T = 0x4, 591 MODE_EL1H = 0x5, 592 MODE_EL2T = 0x8, 593 MODE_EL2H = 0x9, 594 MODE_EL3T = 0xC, 595 MODE_EL3H = 0xD, 596 MODE_USER = 16, 597 MODE_FIQ = 17, 598 MODE_IRQ = 18, 599 MODE_SVC = 19, 600 MODE_MON = 22, 601 MODE_ABORT = 23, 602 MODE_HYP = 26, 603 MODE_UNDEFINED = 27, 604 MODE_SYSTEM = 31, 605 MODE_MAXMODE = MODE_SYSTEM 606 }; 607 608 enum ExceptionClass { 609 EC_INVALID = -1, 610 EC_UNKNOWN = 0x0, 611 EC_TRAPPED_WFI_WFE = 0x1, 612 EC_TRAPPED_CP15_MCR_MRC = 0x3, 613 EC_TRAPPED_CP15_MCRR_MRRC = 0x4, 614 EC_TRAPPED_CP14_MCR_MRC = 0x5, 615 EC_TRAPPED_CP14_LDC_STC = 0x6, 616 EC_TRAPPED_HCPTR = 0x7, 617 EC_TRAPPED_SIMD_FP = 0x7, // AArch64 alias 618 EC_TRAPPED_CP10_MRC_VMRS = 0x8, 619 EC_TRAPPED_BXJ = 0xA, 620 EC_TRAPPED_CP14_MCRR_MRRC = 0xC, 621 EC_ILLEGAL_INST = 0xE, 622 EC_SVC_TO_HYP = 0x11, 623 EC_SVC = 0x11, // AArch64 alias 624 EC_HVC = 0x12, 625 EC_SMC_TO_HYP = 0x13, 626 EC_SMC = 0x13, // AArch64 alias 627 EC_SVC_64 = 0x15, 628 EC_HVC_64 = 0x16, 629 EC_SMC_64 = 0x17, 630 EC_TRAPPED_MSR_MRS_64 = 0x18, 631 EC_PREFETCH_ABORT_TO_HYP = 0x20, 632 EC_PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias 633 EC_PREFETCH_ABORT_FROM_HYP = 0x21, 634 EC_PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias 635 EC_PC_ALIGNMENT = 0x22, 636 EC_DATA_ABORT_TO_HYP = 0x24, 637 EC_DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias 638 EC_DATA_ABORT_FROM_HYP = 0x25, 639 EC_DATA_ABORT_CURR_EL = 0x25, // AArch64 alias 640 EC_STACK_PTR_ALIGNMENT = 0x26, 641 EC_FP_EXCEPTION = 0x28, 642 EC_FP_EXCEPTION_64 = 0x2C, 643 EC_SERROR = 0x2F, 644 EC_SOFTWARE_BREAKPOINT = 0x38, 645 EC_SOFTWARE_BREAKPOINT_64 = 0x3C, 646 }; 647 648 /** 649 * Instruction decoder fault codes in ExtMachInst. 650 */ 651 enum DecoderFault : std::uint8_t { 652 OK = 0x0, ///< No fault 653 UNALIGNED = 0x1, ///< Unaligned instruction fault 654 655 PANIC = 0x3, ///< Internal gem5 error 656 }; 657 658 BitUnion8(OperatingMode64) 659 Bitfield<0> spX; 660 Bitfield<3, 2> el; 661 Bitfield<4> width; 662 EndBitUnion(OperatingMode64) 663 664 static bool inline 665 opModeIs64(OperatingMode mode) 666 { 667 return ((OperatingMode64)(uint8_t)mode).width == 0; 668 } 669 670 static bool inline 671 opModeIsH(OperatingMode mode) 672 { 673 return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H); 674 } 675 676 static bool inline 677 opModeIsT(OperatingMode mode) 678 { 679 return (mode == MODE_EL0T || mode == MODE_EL1T || mode == MODE_EL2T || 680 mode == MODE_EL3T); 681 } 682 683 static ExceptionLevel inline 684 opModeToEL(OperatingMode mode) 685 { 686 bool aarch32 = ((mode >> 4) & 1) ? true : false; 687 if (aarch32) { 688 switch (mode) { 689 case MODE_USER: 690 return EL0; 691 case MODE_FIQ: 692 case MODE_IRQ: 693 case MODE_SVC: 694 case MODE_ABORT: 695 case MODE_UNDEFINED: 696 case MODE_SYSTEM: 697 return EL1; 698 case MODE_HYP: 699 return EL2; 700 case MODE_MON: 701 return EL3; 702 default: 703 panic("Invalid operating mode: %d", mode); 704 break; 705 } 706 } else { 707 // aarch64 708 return (ExceptionLevel) ((mode >> 2) & 3); 709 } 710 } 711 712 static inline bool 713 badMode(OperatingMode mode) 714 { 715 switch (mode) { 716 case MODE_EL0T: 717 case MODE_EL1T: 718 case MODE_EL1H: 719 case MODE_EL2T: 720 case MODE_EL2H: 721 case MODE_EL3T: 722 case MODE_EL3H: 723 case MODE_USER: 724 case MODE_FIQ: 725 case MODE_IRQ: 726 case MODE_SVC: 727 case MODE_MON: 728 case MODE_ABORT: 729 case MODE_HYP: 730 case MODE_UNDEFINED: 731 case MODE_SYSTEM: 732 return false; 733 default: 734 return true; 735 } 736 } 737 738 739 static inline bool 740 badMode32(OperatingMode mode) 741 { 742 switch (mode) { 743 case MODE_USER: 744 case MODE_FIQ: 745 case MODE_IRQ: 746 case MODE_SVC: 747 case MODE_MON: 748 case MODE_ABORT: 749 case MODE_HYP: 750 case MODE_UNDEFINED: 751 case MODE_SYSTEM: 752 return false; 753 default: 754 return true; 755 } 756 } 757 758} // namespace ArmISA 759 760#endif 761