tarmac_parser.cc revision 12749
112641Sgiacomo.travaglini@arm.com/* 212641Sgiacomo.travaglini@arm.com * Copyright (c) 2011,2017-2018 ARM Limited 312641Sgiacomo.travaglini@arm.com * All rights reserved 412641Sgiacomo.travaglini@arm.com * 512641Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 612641Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 712641Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 812641Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 912641Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1012641Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1112641Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1212641Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1312641Sgiacomo.travaglini@arm.com * 1412641Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1512641Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1612641Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 1712641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 1812641Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1912641Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2012641Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2112641Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2212641Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2312641Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2412641Sgiacomo.travaglini@arm.com * 2512641Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612641Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712641Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812641Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912641Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012641Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112641Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212641Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312641Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412641Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512641Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612641Sgiacomo.travaglini@arm.com * 3712641Sgiacomo.travaglini@arm.com * Authors: Giacomo Gabrielli 3812641Sgiacomo.travaglini@arm.com */ 3912641Sgiacomo.travaglini@arm.com 4012641Sgiacomo.travaglini@arm.com#include <algorithm> 4112641Sgiacomo.travaglini@arm.com#include <cctype> 4212641Sgiacomo.travaglini@arm.com#include <cstring> 4312641Sgiacomo.travaglini@arm.com#include <iomanip> 4412641Sgiacomo.travaglini@arm.com#include <string> 4512641Sgiacomo.travaglini@arm.com 4612641Sgiacomo.travaglini@arm.com#include "arch/arm/tracers/tarmac_parser.hh" 4712641Sgiacomo.travaglini@arm.com 4812641Sgiacomo.travaglini@arm.com#include "arch/arm/tlb.hh" 4912641Sgiacomo.travaglini@arm.com#include "arch/arm/insts/static_inst.hh" 5012641Sgiacomo.travaglini@arm.com#include "config/the_isa.hh" 5112641Sgiacomo.travaglini@arm.com#include "cpu/static_inst.hh" 5212641Sgiacomo.travaglini@arm.com#include "cpu/thread_context.hh" 5312641Sgiacomo.travaglini@arm.com#include "mem/fs_translating_port_proxy.hh" 5412641Sgiacomo.travaglini@arm.com#include "mem/packet.hh" 5512641Sgiacomo.travaglini@arm.com#include "sim/core.hh" 5612641Sgiacomo.travaglini@arm.com#include "sim/faults.hh" 5712641Sgiacomo.travaglini@arm.com#include "sim/sim_exit.hh" 5812641Sgiacomo.travaglini@arm.com 5912641Sgiacomo.travaglini@arm.comusing namespace std; 6012641Sgiacomo.travaglini@arm.comusing namespace TheISA; 6112641Sgiacomo.travaglini@arm.com 6212641Sgiacomo.travaglini@arm.comnamespace Trace { 6312641Sgiacomo.travaglini@arm.com 6412641Sgiacomo.travaglini@arm.com// TARMAC Parser static variables 6512641Sgiacomo.travaglini@arm.comconst int TarmacParserRecord::MaxLineLength; 6612641Sgiacomo.travaglini@arm.com 6712641Sgiacomo.travaglini@arm.comTarmacParserRecord::ParserInstEntry TarmacParserRecord::instRecord; 6812641Sgiacomo.travaglini@arm.comTarmacParserRecord::ParserRegEntry TarmacParserRecord::regRecord; 6912641Sgiacomo.travaglini@arm.comTarmacParserRecord::ParserMemEntry TarmacParserRecord::memRecord; 7012641Sgiacomo.travaglini@arm.comTarmacBaseRecord::TarmacRecordType TarmacParserRecord::currRecordType; 7112641Sgiacomo.travaglini@arm.com 7212641Sgiacomo.travaglini@arm.comlist<TarmacParserRecord::ParserRegEntry> TarmacParserRecord::destRegRecords; 7312641Sgiacomo.travaglini@arm.comchar TarmacParserRecord::buf[TarmacParserRecord::MaxLineLength]; 7412641Sgiacomo.travaglini@arm.comTarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = { 7512641Sgiacomo.travaglini@arm.com 7612641Sgiacomo.travaglini@arm.com { "cpsr", MISCREG_CPSR }, 7712641Sgiacomo.travaglini@arm.com { "nzcv", MISCREG_NZCV }, 7812641Sgiacomo.travaglini@arm.com 7912641Sgiacomo.travaglini@arm.com // AArch32 CP14 registers 8012641Sgiacomo.travaglini@arm.com { "dbgdidr", MISCREG_DBGDIDR }, 8112641Sgiacomo.travaglini@arm.com { "dbgdscrint", MISCREG_DBGDSCRint }, 8212641Sgiacomo.travaglini@arm.com { "dbgdccint", MISCREG_DBGDCCINT }, 8312641Sgiacomo.travaglini@arm.com { "dbgdtrtxint", MISCREG_DBGDTRTXint }, 8412641Sgiacomo.travaglini@arm.com { "dbgdtrrxint", MISCREG_DBGDTRRXint }, 8512641Sgiacomo.travaglini@arm.com { "dbgwfar", MISCREG_DBGWFAR }, 8612641Sgiacomo.travaglini@arm.com { "dbgvcr", MISCREG_DBGVCR }, 8712641Sgiacomo.travaglini@arm.com { "dbgdtrrxext", MISCREG_DBGDTRRXext }, 8812641Sgiacomo.travaglini@arm.com { "dbgdscrext", MISCREG_DBGDSCRext }, 8912641Sgiacomo.travaglini@arm.com { "dbgdtrtxext", MISCREG_DBGDTRTXext }, 9012641Sgiacomo.travaglini@arm.com { "dbgoseccr", MISCREG_DBGOSECCR }, 9112641Sgiacomo.travaglini@arm.com { "dbgbvr0", MISCREG_DBGBVR0 }, 9212641Sgiacomo.travaglini@arm.com { "dbgbvr1", MISCREG_DBGBVR1 }, 9312641Sgiacomo.travaglini@arm.com { "dbgbvr2", MISCREG_DBGBVR2 }, 9412641Sgiacomo.travaglini@arm.com { "dbgbvr3", MISCREG_DBGBVR3 }, 9512641Sgiacomo.travaglini@arm.com { "dbgbvr4", MISCREG_DBGBVR4 }, 9612641Sgiacomo.travaglini@arm.com { "dbgbvr5", MISCREG_DBGBVR5 }, 9712641Sgiacomo.travaglini@arm.com { "dbgbcr0", MISCREG_DBGBCR0 }, 9812641Sgiacomo.travaglini@arm.com { "dbgbcr1", MISCREG_DBGBCR1 }, 9912641Sgiacomo.travaglini@arm.com { "dbgbcr2", MISCREG_DBGBCR2 }, 10012641Sgiacomo.travaglini@arm.com { "dbgbcr3", MISCREG_DBGBCR3 }, 10112641Sgiacomo.travaglini@arm.com { "dbgbcr4", MISCREG_DBGBCR4 }, 10212641Sgiacomo.travaglini@arm.com { "dbgbcr5", MISCREG_DBGBCR5 }, 10312641Sgiacomo.travaglini@arm.com { "dbgwvr0", MISCREG_DBGWVR0 }, 10412641Sgiacomo.travaglini@arm.com { "dbgwvr1", MISCREG_DBGWVR1 }, 10512641Sgiacomo.travaglini@arm.com { "dbgwvr2", MISCREG_DBGWVR2 }, 10612641Sgiacomo.travaglini@arm.com { "dbgwvr3", MISCREG_DBGWVR3 }, 10712641Sgiacomo.travaglini@arm.com { "dbgwcr0", MISCREG_DBGWCR0 }, 10812641Sgiacomo.travaglini@arm.com { "dbgwcr1", MISCREG_DBGWCR1 }, 10912641Sgiacomo.travaglini@arm.com { "dbgwcr2", MISCREG_DBGWCR2 }, 11012641Sgiacomo.travaglini@arm.com { "dbgwcr3", MISCREG_DBGWCR3 }, 11112641Sgiacomo.travaglini@arm.com { "dbgdrar", MISCREG_DBGDRAR }, 11212641Sgiacomo.travaglini@arm.com { "dbgbxvr4", MISCREG_DBGBXVR4 }, 11312641Sgiacomo.travaglini@arm.com { "dbgbxvr5", MISCREG_DBGBXVR5 }, 11412641Sgiacomo.travaglini@arm.com { "dbgoslar", MISCREG_DBGOSLAR }, 11512641Sgiacomo.travaglini@arm.com { "dbgoslsr", MISCREG_DBGOSLSR }, 11612641Sgiacomo.travaglini@arm.com { "dbgosdlr", MISCREG_DBGOSDLR }, 11712641Sgiacomo.travaglini@arm.com { "dbgprcr", MISCREG_DBGPRCR }, 11812641Sgiacomo.travaglini@arm.com { "dbgdsar", MISCREG_DBGDSAR }, 11912641Sgiacomo.travaglini@arm.com { "dbgclaimset", MISCREG_DBGCLAIMSET }, 12012641Sgiacomo.travaglini@arm.com { "dbgclaimclr", MISCREG_DBGCLAIMCLR }, 12112641Sgiacomo.travaglini@arm.com { "dbgauthstatus", MISCREG_DBGAUTHSTATUS }, 12212641Sgiacomo.travaglini@arm.com { "dbgdevid2", MISCREG_DBGDEVID2 }, 12312641Sgiacomo.travaglini@arm.com { "dbgdevid1", MISCREG_DBGDEVID1 }, 12412641Sgiacomo.travaglini@arm.com { "dbgdevid0", MISCREG_DBGDEVID0 }, 12512641Sgiacomo.travaglini@arm.com { "teecr", MISCREG_TEECR }, 12612641Sgiacomo.travaglini@arm.com { "jidr", MISCREG_JIDR }, 12712641Sgiacomo.travaglini@arm.com { "teehbr", MISCREG_TEEHBR }, 12812641Sgiacomo.travaglini@arm.com { "joscr", MISCREG_JOSCR }, 12912641Sgiacomo.travaglini@arm.com { "jmcr", MISCREG_JMCR }, 13012641Sgiacomo.travaglini@arm.com 13112641Sgiacomo.travaglini@arm.com // AArch32 CP15 registers 13212641Sgiacomo.travaglini@arm.com { "midr", MISCREG_MIDR }, 13312641Sgiacomo.travaglini@arm.com { "ctr", MISCREG_CTR }, 13412641Sgiacomo.travaglini@arm.com { "tcmtr", MISCREG_TCMTR }, 13512641Sgiacomo.travaglini@arm.com { "tlbtr", MISCREG_TLBTR }, 13612641Sgiacomo.travaglini@arm.com { "mpidr", MISCREG_MPIDR }, 13712641Sgiacomo.travaglini@arm.com { "revidr", MISCREG_REVIDR }, 13812641Sgiacomo.travaglini@arm.com { "id_pfr0", MISCREG_ID_PFR0 }, 13912641Sgiacomo.travaglini@arm.com { "id_pfr1", MISCREG_ID_PFR1 }, 14012641Sgiacomo.travaglini@arm.com { "id_dfr0", MISCREG_ID_DFR0 }, 14112641Sgiacomo.travaglini@arm.com { "id_afr0", MISCREG_ID_AFR0 }, 14212641Sgiacomo.travaglini@arm.com { "id_mmfr0", MISCREG_ID_MMFR0 }, 14312641Sgiacomo.travaglini@arm.com { "id_mmfr1", MISCREG_ID_MMFR1 }, 14412641Sgiacomo.travaglini@arm.com { "id_mmfr2", MISCREG_ID_MMFR2 }, 14512641Sgiacomo.travaglini@arm.com { "id_mmfr3", MISCREG_ID_MMFR3 }, 14612641Sgiacomo.travaglini@arm.com { "id_isar0", MISCREG_ID_ISAR0 }, 14712641Sgiacomo.travaglini@arm.com { "id_isar1", MISCREG_ID_ISAR1 }, 14812641Sgiacomo.travaglini@arm.com { "id_isar2", MISCREG_ID_ISAR2 }, 14912641Sgiacomo.travaglini@arm.com { "id_isar3", MISCREG_ID_ISAR3 }, 15012641Sgiacomo.travaglini@arm.com { "id_isar4", MISCREG_ID_ISAR4 }, 15112641Sgiacomo.travaglini@arm.com { "id_isar5", MISCREG_ID_ISAR5 }, 15212641Sgiacomo.travaglini@arm.com { "ccsidr", MISCREG_CCSIDR }, 15312641Sgiacomo.travaglini@arm.com { "clidr", MISCREG_CLIDR }, 15412641Sgiacomo.travaglini@arm.com { "aidr", MISCREG_AIDR }, 15512641Sgiacomo.travaglini@arm.com { "csselr_ns", MISCREG_CSSELR_NS }, 15612641Sgiacomo.travaglini@arm.com { "csselr_s", MISCREG_CSSELR_S }, 15712641Sgiacomo.travaglini@arm.com { "vpidr", MISCREG_VPIDR }, 15812641Sgiacomo.travaglini@arm.com { "vmpidr", MISCREG_VMPIDR }, 15912641Sgiacomo.travaglini@arm.com { "sctlr_ns", MISCREG_SCTLR_NS }, 16012641Sgiacomo.travaglini@arm.com { "sctlr_s", MISCREG_SCTLR_S }, 16112641Sgiacomo.travaglini@arm.com { "actlr_ns", MISCREG_ACTLR_NS }, 16212641Sgiacomo.travaglini@arm.com { "actlr_s", MISCREG_ACTLR_S }, 16312641Sgiacomo.travaglini@arm.com { "cpacr", MISCREG_CPACR }, 16412641Sgiacomo.travaglini@arm.com { "scr", MISCREG_SCR }, 16512641Sgiacomo.travaglini@arm.com { "sder", MISCREG_SDER }, 16612641Sgiacomo.travaglini@arm.com { "nsacr", MISCREG_NSACR }, 16712641Sgiacomo.travaglini@arm.com { "hsctlr", MISCREG_HSCTLR }, 16812641Sgiacomo.travaglini@arm.com { "hactlr", MISCREG_HACTLR }, 16912641Sgiacomo.travaglini@arm.com { "hcr", MISCREG_HCR }, 17012641Sgiacomo.travaglini@arm.com { "hdcr", MISCREG_HDCR }, 17112641Sgiacomo.travaglini@arm.com { "hcptr", MISCREG_HCPTR }, 17212641Sgiacomo.travaglini@arm.com { "hstr", MISCREG_HSTR }, 17312641Sgiacomo.travaglini@arm.com { "hacr", MISCREG_HACR }, 17412641Sgiacomo.travaglini@arm.com { "ttbr0_ns", MISCREG_TTBR0_NS }, 17512641Sgiacomo.travaglini@arm.com { "ttbr0_s", MISCREG_TTBR0_S }, 17612641Sgiacomo.travaglini@arm.com { "ttbr1_ns", MISCREG_TTBR1_NS }, 17712641Sgiacomo.travaglini@arm.com { "ttbr1_s", MISCREG_TTBR1_S }, 17812641Sgiacomo.travaglini@arm.com { "ttbcr_ns", MISCREG_TTBCR_NS }, 17912641Sgiacomo.travaglini@arm.com { "ttbcr_s", MISCREG_TTBCR_S }, 18012641Sgiacomo.travaglini@arm.com { "htcr", MISCREG_HTCR }, 18112641Sgiacomo.travaglini@arm.com { "vtcr", MISCREG_VTCR }, 18212641Sgiacomo.travaglini@arm.com { "dacr_ns", MISCREG_DACR_NS }, 18312641Sgiacomo.travaglini@arm.com { "dacr_s", MISCREG_DACR_S }, 18412641Sgiacomo.travaglini@arm.com { "dfsr_ns", MISCREG_DFSR_NS }, 18512641Sgiacomo.travaglini@arm.com { "dfsr_s", MISCREG_DFSR_S }, 18612641Sgiacomo.travaglini@arm.com { "ifsr_ns", MISCREG_IFSR_NS }, 18712641Sgiacomo.travaglini@arm.com { "ifsr_s", MISCREG_IFSR_S }, 18812641Sgiacomo.travaglini@arm.com { "adfsr_ns", MISCREG_ADFSR_NS }, 18912641Sgiacomo.travaglini@arm.com { "adfsr_s", MISCREG_ADFSR_S }, 19012641Sgiacomo.travaglini@arm.com { "aifsr_ns", MISCREG_AIFSR_NS }, 19112641Sgiacomo.travaglini@arm.com { "aifsr_s", MISCREG_AIFSR_S }, 19212641Sgiacomo.travaglini@arm.com { "hadfsr", MISCREG_HADFSR }, 19312641Sgiacomo.travaglini@arm.com { "haifsr", MISCREG_HAIFSR }, 19412641Sgiacomo.travaglini@arm.com { "hsr", MISCREG_HSR }, 19512641Sgiacomo.travaglini@arm.com { "dfar_ns", MISCREG_DFAR_NS }, 19612641Sgiacomo.travaglini@arm.com { "dfar_s", MISCREG_DFAR_S }, 19712641Sgiacomo.travaglini@arm.com { "ifar_ns", MISCREG_IFAR_NS }, 19812641Sgiacomo.travaglini@arm.com { "ifar_s", MISCREG_IFAR_S }, 19912641Sgiacomo.travaglini@arm.com { "hdfar", MISCREG_HDFAR }, 20012641Sgiacomo.travaglini@arm.com { "hifar", MISCREG_HIFAR }, 20112641Sgiacomo.travaglini@arm.com { "hpfar", MISCREG_HPFAR }, 20212641Sgiacomo.travaglini@arm.com { "icialluis", MISCREG_ICIALLUIS }, 20312641Sgiacomo.travaglini@arm.com { "bpiallis", MISCREG_BPIALLIS }, 20412641Sgiacomo.travaglini@arm.com { "par_ns", MISCREG_PAR_NS }, 20512641Sgiacomo.travaglini@arm.com { "par_s", MISCREG_PAR_S }, 20612641Sgiacomo.travaglini@arm.com { "iciallu", MISCREG_ICIALLU }, 20712641Sgiacomo.travaglini@arm.com { "icimvau", MISCREG_ICIMVAU }, 20812641Sgiacomo.travaglini@arm.com { "cp15isb", MISCREG_CP15ISB }, 20912641Sgiacomo.travaglini@arm.com { "bpiall", MISCREG_BPIALL }, 21012641Sgiacomo.travaglini@arm.com { "bpimva", MISCREG_BPIMVA }, 21112641Sgiacomo.travaglini@arm.com { "dcimvac", MISCREG_DCIMVAC }, 21212641Sgiacomo.travaglini@arm.com { "dcisw", MISCREG_DCISW }, 21312641Sgiacomo.travaglini@arm.com { "ats1cpr", MISCREG_ATS1CPR }, 21412641Sgiacomo.travaglini@arm.com { "ats1cpw", MISCREG_ATS1CPW }, 21512641Sgiacomo.travaglini@arm.com { "ats1cur", MISCREG_ATS1CUR }, 21612641Sgiacomo.travaglini@arm.com { "ats1cuw", MISCREG_ATS1CUW }, 21712641Sgiacomo.travaglini@arm.com { "ats12nsopr", MISCREG_ATS12NSOPR }, 21812641Sgiacomo.travaglini@arm.com { "ats12nsopw", MISCREG_ATS12NSOPW }, 21912641Sgiacomo.travaglini@arm.com { "ats12nsour", MISCREG_ATS12NSOUR }, 22012641Sgiacomo.travaglini@arm.com { "ats12nsouw", MISCREG_ATS12NSOUW }, 22112641Sgiacomo.travaglini@arm.com { "dccmvac", MISCREG_DCCMVAC }, 22212641Sgiacomo.travaglini@arm.com { "dccsw", MISCREG_DCCSW }, 22312641Sgiacomo.travaglini@arm.com { "cp15dsb", MISCREG_CP15DSB }, 22412641Sgiacomo.travaglini@arm.com { "cp15dmb", MISCREG_CP15DMB }, 22512641Sgiacomo.travaglini@arm.com { "dccmvau", MISCREG_DCCMVAU }, 22612641Sgiacomo.travaglini@arm.com { "dccimvac", MISCREG_DCCIMVAC }, 22712641Sgiacomo.travaglini@arm.com { "dccisw", MISCREG_DCCISW }, 22812641Sgiacomo.travaglini@arm.com { "ats1hr", MISCREG_ATS1HR }, 22912641Sgiacomo.travaglini@arm.com { "ats1hw", MISCREG_ATS1HW }, 23012641Sgiacomo.travaglini@arm.com { "tlbiallis", MISCREG_TLBIALLIS }, 23112641Sgiacomo.travaglini@arm.com { "tlbimvais", MISCREG_TLBIMVAIS }, 23212641Sgiacomo.travaglini@arm.com { "tlbiasidis", MISCREG_TLBIASIDIS }, 23312641Sgiacomo.travaglini@arm.com { "tlbimvaais", MISCREG_TLBIMVAAIS }, 23412641Sgiacomo.travaglini@arm.com { "tlbimvalis", MISCREG_TLBIMVALIS }, 23512641Sgiacomo.travaglini@arm.com { "tlbimvaalis", MISCREG_TLBIMVAALIS }, 23612641Sgiacomo.travaglini@arm.com { "itlbiall", MISCREG_ITLBIALL }, 23712641Sgiacomo.travaglini@arm.com { "itlbimva", MISCREG_ITLBIMVA }, 23812641Sgiacomo.travaglini@arm.com { "itlbiasid", MISCREG_ITLBIASID }, 23912641Sgiacomo.travaglini@arm.com { "dtlbiall", MISCREG_DTLBIALL }, 24012641Sgiacomo.travaglini@arm.com { "dtlbimva", MISCREG_DTLBIMVA }, 24112641Sgiacomo.travaglini@arm.com { "dtlbiasid", MISCREG_DTLBIASID }, 24212641Sgiacomo.travaglini@arm.com { "tlbiall", MISCREG_TLBIALL }, 24312641Sgiacomo.travaglini@arm.com { "tlbimva", MISCREG_TLBIMVA }, 24412641Sgiacomo.travaglini@arm.com { "tlbiasid", MISCREG_TLBIASID }, 24512641Sgiacomo.travaglini@arm.com { "tlbimvaa", MISCREG_TLBIMVAA }, 24612641Sgiacomo.travaglini@arm.com { "tlbimval", MISCREG_TLBIMVAL }, 24712641Sgiacomo.travaglini@arm.com { "tlbimvaal", MISCREG_TLBIMVAAL }, 24812641Sgiacomo.travaglini@arm.com { "tlbiipas2is", MISCREG_TLBIIPAS2IS }, 24912641Sgiacomo.travaglini@arm.com { "tlbiipas2lis", MISCREG_TLBIIPAS2LIS }, 25012641Sgiacomo.travaglini@arm.com { "tlbiallhis", MISCREG_TLBIALLHIS }, 25112641Sgiacomo.travaglini@arm.com { "tlbimvahis", MISCREG_TLBIMVAHIS }, 25212641Sgiacomo.travaglini@arm.com { "tlbiallnsnhis", MISCREG_TLBIALLNSNHIS }, 25312641Sgiacomo.travaglini@arm.com { "tlbimvalhis", MISCREG_TLBIMVALHIS }, 25412641Sgiacomo.travaglini@arm.com { "tlbiipas2", MISCREG_TLBIIPAS2 }, 25512641Sgiacomo.travaglini@arm.com { "tlbiipas2l", MISCREG_TLBIIPAS2L }, 25612641Sgiacomo.travaglini@arm.com { "tlbiallh", MISCREG_TLBIALLH }, 25712641Sgiacomo.travaglini@arm.com { "tlbimvah", MISCREG_TLBIMVAH }, 25812641Sgiacomo.travaglini@arm.com { "tlbiallnsnh", MISCREG_TLBIALLNSNH }, 25912641Sgiacomo.travaglini@arm.com { "tlbimvalh", MISCREG_TLBIMVALH }, 26012641Sgiacomo.travaglini@arm.com { "pmcr", MISCREG_PMCR }, 26112641Sgiacomo.travaglini@arm.com { "pmcntenset", MISCREG_PMCNTENSET }, 26212641Sgiacomo.travaglini@arm.com { "pmcntenclr", MISCREG_PMCNTENCLR }, 26312641Sgiacomo.travaglini@arm.com { "pmovsr", MISCREG_PMOVSR }, 26412641Sgiacomo.travaglini@arm.com { "pmswinc", MISCREG_PMSWINC }, 26512641Sgiacomo.travaglini@arm.com { "pmselr", MISCREG_PMSELR }, 26612641Sgiacomo.travaglini@arm.com { "pmceid0", MISCREG_PMCEID0 }, 26712641Sgiacomo.travaglini@arm.com { "pmceid1", MISCREG_PMCEID1 }, 26812641Sgiacomo.travaglini@arm.com { "pmccntr", MISCREG_PMCCNTR }, 26912641Sgiacomo.travaglini@arm.com { "pmxevtyper", MISCREG_PMXEVTYPER }, 27012641Sgiacomo.travaglini@arm.com { "pmccfiltr", MISCREG_PMCCFILTR }, 27112641Sgiacomo.travaglini@arm.com { "pmxevcntr", MISCREG_PMXEVCNTR }, 27212641Sgiacomo.travaglini@arm.com { "pmuserenr", MISCREG_PMUSERENR }, 27312641Sgiacomo.travaglini@arm.com { "pmintenset", MISCREG_PMINTENSET }, 27412641Sgiacomo.travaglini@arm.com { "pmintenclr", MISCREG_PMINTENCLR }, 27512641Sgiacomo.travaglini@arm.com { "pmovsset", MISCREG_PMOVSSET }, 27612641Sgiacomo.travaglini@arm.com { "l2ctlr", MISCREG_L2CTLR }, 27712641Sgiacomo.travaglini@arm.com { "l2ectlr", MISCREG_L2ECTLR }, 27812641Sgiacomo.travaglini@arm.com { "prrr_ns", MISCREG_PRRR_NS }, 27912641Sgiacomo.travaglini@arm.com { "prrr_s", MISCREG_PRRR_S }, 28012641Sgiacomo.travaglini@arm.com { "mair0_ns", MISCREG_MAIR0_NS }, 28112641Sgiacomo.travaglini@arm.com { "mair0_s", MISCREG_MAIR0_S }, 28212641Sgiacomo.travaglini@arm.com { "nmrr_ns", MISCREG_NMRR_NS }, 28312641Sgiacomo.travaglini@arm.com { "nmrr_s", MISCREG_NMRR_S }, 28412641Sgiacomo.travaglini@arm.com { "mair1_ns", MISCREG_MAIR1_NS }, 28512641Sgiacomo.travaglini@arm.com { "mair1_s", MISCREG_MAIR1_S }, 28612641Sgiacomo.travaglini@arm.com { "amair0_ns", MISCREG_AMAIR0_NS }, 28712641Sgiacomo.travaglini@arm.com { "amair0_s", MISCREG_AMAIR0_S }, 28812641Sgiacomo.travaglini@arm.com { "amair1_ns", MISCREG_AMAIR1_NS }, 28912641Sgiacomo.travaglini@arm.com { "amair1_s", MISCREG_AMAIR1_S }, 29012641Sgiacomo.travaglini@arm.com { "hmair0", MISCREG_HMAIR0 }, 29112641Sgiacomo.travaglini@arm.com { "hmair1", MISCREG_HMAIR1 }, 29212641Sgiacomo.travaglini@arm.com { "hamair0", MISCREG_HAMAIR0 }, 29312641Sgiacomo.travaglini@arm.com { "hamair1", MISCREG_HAMAIR1 }, 29412641Sgiacomo.travaglini@arm.com { "vbar_ns", MISCREG_VBAR_NS }, 29512641Sgiacomo.travaglini@arm.com { "vbar_s", MISCREG_VBAR_S }, 29612641Sgiacomo.travaglini@arm.com { "mvbar", MISCREG_MVBAR }, 29712641Sgiacomo.travaglini@arm.com { "rmr", MISCREG_RMR }, 29812641Sgiacomo.travaglini@arm.com { "isr", MISCREG_ISR }, 29912641Sgiacomo.travaglini@arm.com { "hvbar", MISCREG_HVBAR }, 30012641Sgiacomo.travaglini@arm.com { "fcseidr", MISCREG_FCSEIDR }, 30112641Sgiacomo.travaglini@arm.com { "contextidr_ns", MISCREG_CONTEXTIDR_NS }, 30212641Sgiacomo.travaglini@arm.com { "contextidr_s", MISCREG_CONTEXTIDR_S }, 30312641Sgiacomo.travaglini@arm.com { "tpidrurw_ns", MISCREG_TPIDRURW_NS }, 30412641Sgiacomo.travaglini@arm.com { "tpidrurw_s", MISCREG_TPIDRURW_S }, 30512641Sgiacomo.travaglini@arm.com { "tpidruro_ns", MISCREG_TPIDRURO_NS }, 30612641Sgiacomo.travaglini@arm.com { "tpidruro_s", MISCREG_TPIDRURO_S }, 30712641Sgiacomo.travaglini@arm.com { "tpidrprw_ns", MISCREG_TPIDRPRW_NS }, 30812641Sgiacomo.travaglini@arm.com { "tpidrprw_s", MISCREG_TPIDRPRW_S }, 30912641Sgiacomo.travaglini@arm.com { "htpidr", MISCREG_HTPIDR }, 31012641Sgiacomo.travaglini@arm.com { "cntfrq", MISCREG_CNTFRQ }, 31112641Sgiacomo.travaglini@arm.com { "cntkctl", MISCREG_CNTKCTL }, 31212641Sgiacomo.travaglini@arm.com { "cntp_tval_ns", MISCREG_CNTP_TVAL_NS }, 31312641Sgiacomo.travaglini@arm.com { "cntp_tval_s", MISCREG_CNTP_TVAL_S }, 31412641Sgiacomo.travaglini@arm.com { "cntp_ctl_ns", MISCREG_CNTP_CTL_NS }, 31512641Sgiacomo.travaglini@arm.com { "cntp_ctl_s", MISCREG_CNTP_CTL_S }, 31612641Sgiacomo.travaglini@arm.com { "cntv_tval", MISCREG_CNTV_TVAL }, 31712641Sgiacomo.travaglini@arm.com { "cntv_ctl", MISCREG_CNTV_CTL }, 31812641Sgiacomo.travaglini@arm.com { "cnthctl", MISCREG_CNTHCTL }, 31912641Sgiacomo.travaglini@arm.com { "cnthp_tval", MISCREG_CNTHP_TVAL }, 32012641Sgiacomo.travaglini@arm.com { "cnthp_ctl", MISCREG_CNTHP_CTL }, 32112641Sgiacomo.travaglini@arm.com { "il1data0", MISCREG_IL1DATA0 }, 32212641Sgiacomo.travaglini@arm.com { "il1data1", MISCREG_IL1DATA1 }, 32312641Sgiacomo.travaglini@arm.com { "il1data2", MISCREG_IL1DATA2 }, 32412641Sgiacomo.travaglini@arm.com { "il1data3", MISCREG_IL1DATA3 }, 32512641Sgiacomo.travaglini@arm.com { "dl1data0", MISCREG_DL1DATA0 }, 32612641Sgiacomo.travaglini@arm.com { "dl1data1", MISCREG_DL1DATA1 }, 32712641Sgiacomo.travaglini@arm.com { "dl1data2", MISCREG_DL1DATA2 }, 32812641Sgiacomo.travaglini@arm.com { "dl1data3", MISCREG_DL1DATA3 }, 32912641Sgiacomo.travaglini@arm.com { "dl1data4", MISCREG_DL1DATA4 }, 33012641Sgiacomo.travaglini@arm.com { "ramindex", MISCREG_RAMINDEX }, 33112641Sgiacomo.travaglini@arm.com { "l2actlr", MISCREG_L2ACTLR }, 33212641Sgiacomo.travaglini@arm.com { "cbar", MISCREG_CBAR }, 33312641Sgiacomo.travaglini@arm.com { "httbr", MISCREG_HTTBR }, 33412641Sgiacomo.travaglini@arm.com { "vttbr", MISCREG_VTTBR }, 33512641Sgiacomo.travaglini@arm.com { "cntpct", MISCREG_CNTPCT }, 33612641Sgiacomo.travaglini@arm.com { "cntvct", MISCREG_CNTVCT }, 33712641Sgiacomo.travaglini@arm.com { "cntp_cval_ns", MISCREG_CNTP_CVAL_NS }, 33812641Sgiacomo.travaglini@arm.com { "cntp_cval_s", MISCREG_CNTP_CVAL_S }, 33912641Sgiacomo.travaglini@arm.com { "cntv_cval", MISCREG_CNTV_CVAL }, 34012641Sgiacomo.travaglini@arm.com { "cntvoff", MISCREG_CNTVOFF }, 34112641Sgiacomo.travaglini@arm.com { "cnthp_cval", MISCREG_CNTHP_CVAL }, 34212641Sgiacomo.travaglini@arm.com { "cpumerrsr", MISCREG_CPUMERRSR }, 34312641Sgiacomo.travaglini@arm.com { "l2merrsr", MISCREG_L2MERRSR }, 34412641Sgiacomo.travaglini@arm.com 34512641Sgiacomo.travaglini@arm.com // AArch64 registers (Op0=2) 34612641Sgiacomo.travaglini@arm.com { "mdccint_el1", MISCREG_MDCCINT_EL1 }, 34712641Sgiacomo.travaglini@arm.com { "osdtrrx_el1", MISCREG_OSDTRRX_EL1 }, 34812641Sgiacomo.travaglini@arm.com { "mdscr_el1", MISCREG_MDSCR_EL1 }, 34912641Sgiacomo.travaglini@arm.com { "osdtrtx_el1", MISCREG_OSDTRTX_EL1 }, 35012641Sgiacomo.travaglini@arm.com { "oseccr_el1", MISCREG_OSECCR_EL1 }, 35112641Sgiacomo.travaglini@arm.com { "dbgbvr0_el1", MISCREG_DBGBVR0_EL1 }, 35212641Sgiacomo.travaglini@arm.com { "dbgbvr1_el1", MISCREG_DBGBVR1_EL1 }, 35312641Sgiacomo.travaglini@arm.com { "dbgbvr2_el1", MISCREG_DBGBVR2_EL1 }, 35412641Sgiacomo.travaglini@arm.com { "dbgbvr3_el1", MISCREG_DBGBVR3_EL1 }, 35512641Sgiacomo.travaglini@arm.com { "dbgbvr4_el1", MISCREG_DBGBVR4_EL1 }, 35612641Sgiacomo.travaglini@arm.com { "dbgbvr5_el1", MISCREG_DBGBVR5_EL1 }, 35712641Sgiacomo.travaglini@arm.com { "dbgbcr0_el1", MISCREG_DBGBCR0_EL1 }, 35812641Sgiacomo.travaglini@arm.com { "dbgbcr1_el1", MISCREG_DBGBCR1_EL1 }, 35912641Sgiacomo.travaglini@arm.com { "dbgbcr2_el1", MISCREG_DBGBCR2_EL1 }, 36012641Sgiacomo.travaglini@arm.com { "dbgbcr3_el1", MISCREG_DBGBCR3_EL1 }, 36112641Sgiacomo.travaglini@arm.com { "dbgbcr4_el1", MISCREG_DBGBCR4_EL1 }, 36212641Sgiacomo.travaglini@arm.com { "dbgbcr5_el1", MISCREG_DBGBCR5_EL1 }, 36312641Sgiacomo.travaglini@arm.com { "dbgwvr0_el1", MISCREG_DBGWVR0_EL1 }, 36412641Sgiacomo.travaglini@arm.com { "dbgwvr1_el1", MISCREG_DBGWVR1_EL1 }, 36512641Sgiacomo.travaglini@arm.com { "dbgwvr2_el1", MISCREG_DBGWVR2_EL1 }, 36612641Sgiacomo.travaglini@arm.com { "dbgwvr3_el1", MISCREG_DBGWVR3_EL1 }, 36712641Sgiacomo.travaglini@arm.com { "dbgwcr0_el1", MISCREG_DBGWCR0_EL1 }, 36812641Sgiacomo.travaglini@arm.com { "dbgwcr1_el1", MISCREG_DBGWCR1_EL1 }, 36912641Sgiacomo.travaglini@arm.com { "dbgwcr2_el1", MISCREG_DBGWCR2_EL1 }, 37012641Sgiacomo.travaglini@arm.com { "dbgwcr3_el1", MISCREG_DBGWCR3_EL1 }, 37112641Sgiacomo.travaglini@arm.com { "mdccsr_el0", MISCREG_MDCCSR_EL0 }, 37212641Sgiacomo.travaglini@arm.com { "mddtr_el0", MISCREG_MDDTR_EL0 }, 37312641Sgiacomo.travaglini@arm.com { "mddtrtx_el0", MISCREG_MDDTRTX_EL0 }, 37412641Sgiacomo.travaglini@arm.com { "mddtrrx_el0", MISCREG_MDDTRRX_EL0 }, 37512641Sgiacomo.travaglini@arm.com { "dbgvcr32_el2", MISCREG_DBGVCR32_EL2 }, 37612641Sgiacomo.travaglini@arm.com { "mdrar_el1", MISCREG_MDRAR_EL1 }, 37712641Sgiacomo.travaglini@arm.com { "oslar_el1", MISCREG_OSLAR_EL1 }, 37812641Sgiacomo.travaglini@arm.com { "oslsr_el1", MISCREG_OSLSR_EL1 }, 37912641Sgiacomo.travaglini@arm.com { "osdlr_el1", MISCREG_OSDLR_EL1 }, 38012641Sgiacomo.travaglini@arm.com { "dbgprcr_el1", MISCREG_DBGPRCR_EL1 }, 38112641Sgiacomo.travaglini@arm.com { "dbgclaimset_el1", MISCREG_DBGCLAIMSET_EL1 }, 38212641Sgiacomo.travaglini@arm.com { "dbgclaimclr_el1", MISCREG_DBGCLAIMCLR_EL1 }, 38312641Sgiacomo.travaglini@arm.com { "dbgauthstatus_el1", MISCREG_DBGAUTHSTATUS_EL1 }, 38412641Sgiacomo.travaglini@arm.com { "teecr32_el1", MISCREG_TEECR32_EL1 }, 38512641Sgiacomo.travaglini@arm.com { "teehbr32_el1", MISCREG_TEEHBR32_EL1 }, 38612641Sgiacomo.travaglini@arm.com 38712641Sgiacomo.travaglini@arm.com // AArch64 registers (Op0=1,3) 38812641Sgiacomo.travaglini@arm.com { "midr_el1", MISCREG_MIDR_EL1 }, 38912641Sgiacomo.travaglini@arm.com { "mpidr_el1", MISCREG_MPIDR_EL1 }, 39012641Sgiacomo.travaglini@arm.com { "revidr_el1", MISCREG_REVIDR_EL1 }, 39112641Sgiacomo.travaglini@arm.com { "id_pfr0_el1", MISCREG_ID_PFR0_EL1 }, 39212641Sgiacomo.travaglini@arm.com { "id_pfr1_el1", MISCREG_ID_PFR1_EL1 }, 39312641Sgiacomo.travaglini@arm.com { "id_dfr0_el1", MISCREG_ID_DFR0_EL1 }, 39412641Sgiacomo.travaglini@arm.com { "id_afr0_el1", MISCREG_ID_AFR0_EL1 }, 39512641Sgiacomo.travaglini@arm.com { "id_mmfr0_el1", MISCREG_ID_MMFR0_EL1 }, 39612641Sgiacomo.travaglini@arm.com { "id_mmfr1_el1", MISCREG_ID_MMFR1_EL1 }, 39712641Sgiacomo.travaglini@arm.com { "id_mmfr2_el1", MISCREG_ID_MMFR2_EL1 }, 39812641Sgiacomo.travaglini@arm.com { "id_mmfr3_el1", MISCREG_ID_MMFR3_EL1 }, 39912641Sgiacomo.travaglini@arm.com { "id_isar0_el1", MISCREG_ID_ISAR0_EL1 }, 40012641Sgiacomo.travaglini@arm.com { "id_isar1_el1", MISCREG_ID_ISAR1_EL1 }, 40112641Sgiacomo.travaglini@arm.com { "id_isar2_el1", MISCREG_ID_ISAR2_EL1 }, 40212641Sgiacomo.travaglini@arm.com { "id_isar3_el1", MISCREG_ID_ISAR3_EL1 }, 40312641Sgiacomo.travaglini@arm.com { "id_isar4_el1", MISCREG_ID_ISAR4_EL1 }, 40412641Sgiacomo.travaglini@arm.com { "id_isar5_el1", MISCREG_ID_ISAR5_EL1 }, 40512641Sgiacomo.travaglini@arm.com { "mvfr0_el1", MISCREG_MVFR0_EL1 }, 40612641Sgiacomo.travaglini@arm.com { "mvfr1_el1", MISCREG_MVFR1_EL1 }, 40712641Sgiacomo.travaglini@arm.com { "mvfr2_el1", MISCREG_MVFR2_EL1 }, 40812641Sgiacomo.travaglini@arm.com { "id_aa64pfr0_el1", MISCREG_ID_AA64PFR0_EL1 }, 40912641Sgiacomo.travaglini@arm.com { "id_aa64pfr1_el1", MISCREG_ID_AA64PFR1_EL1 }, 41012641Sgiacomo.travaglini@arm.com { "id_aa64dfr0_el1", MISCREG_ID_AA64DFR0_EL1 }, 41112641Sgiacomo.travaglini@arm.com { "id_aa64dfr1_el1", MISCREG_ID_AA64DFR1_EL1 }, 41212641Sgiacomo.travaglini@arm.com { "id_aa64afr0_el1", MISCREG_ID_AA64AFR0_EL1 }, 41312641Sgiacomo.travaglini@arm.com { "id_aa64afr1_el1", MISCREG_ID_AA64AFR1_EL1 }, 41412641Sgiacomo.travaglini@arm.com { "id_aa64isar0_el1", MISCREG_ID_AA64ISAR0_EL1 }, 41512641Sgiacomo.travaglini@arm.com { "id_aa64isar1_el1", MISCREG_ID_AA64ISAR1_EL1 }, 41612641Sgiacomo.travaglini@arm.com { "id_aa64mmfr0_el1", MISCREG_ID_AA64MMFR0_EL1 }, 41712641Sgiacomo.travaglini@arm.com { "id_aa64mmfr1_el1", MISCREG_ID_AA64MMFR1_EL1 }, 41812641Sgiacomo.travaglini@arm.com { "ccsidr_el1", MISCREG_CCSIDR_EL1 }, 41912641Sgiacomo.travaglini@arm.com { "clidr_el1", MISCREG_CLIDR_EL1 }, 42012641Sgiacomo.travaglini@arm.com { "aidr_el1", MISCREG_AIDR_EL1 }, 42112641Sgiacomo.travaglini@arm.com { "csselr_el1", MISCREG_CSSELR_EL1 }, 42212641Sgiacomo.travaglini@arm.com { "ctr_el0", MISCREG_CTR_EL0 }, 42312641Sgiacomo.travaglini@arm.com { "dczid_el0", MISCREG_DCZID_EL0 }, 42412641Sgiacomo.travaglini@arm.com { "vpidr_el2", MISCREG_VPIDR_EL2 }, 42512641Sgiacomo.travaglini@arm.com { "vmpidr_el2", MISCREG_VMPIDR_EL2 }, 42612641Sgiacomo.travaglini@arm.com { "sctlr_el1", MISCREG_SCTLR_EL1 }, 42712641Sgiacomo.travaglini@arm.com { "actlr_el1", MISCREG_ACTLR_EL1 }, 42812641Sgiacomo.travaglini@arm.com { "cpacr_el1", MISCREG_CPACR_EL1 }, 42912641Sgiacomo.travaglini@arm.com { "sctlr_el2", MISCREG_SCTLR_EL2 }, 43012641Sgiacomo.travaglini@arm.com { "actlr_el2", MISCREG_ACTLR_EL2 }, 43112641Sgiacomo.travaglini@arm.com { "hcr_el2", MISCREG_HCR_EL2 }, 43212641Sgiacomo.travaglini@arm.com { "mdcr_el2", MISCREG_MDCR_EL2 }, 43312641Sgiacomo.travaglini@arm.com { "cptr_el2", MISCREG_CPTR_EL2 }, 43412641Sgiacomo.travaglini@arm.com { "hstr_el2", MISCREG_HSTR_EL2 }, 43512641Sgiacomo.travaglini@arm.com { "hacr_el2", MISCREG_HACR_EL2 }, 43612641Sgiacomo.travaglini@arm.com { "sctlr_el3", MISCREG_SCTLR_EL3 }, 43712641Sgiacomo.travaglini@arm.com { "actlr_el3", MISCREG_ACTLR_EL3 }, 43812641Sgiacomo.travaglini@arm.com { "scr_el3", MISCREG_SCR_EL3 }, 43912641Sgiacomo.travaglini@arm.com { "sder32_el3", MISCREG_SDER32_EL3 }, 44012641Sgiacomo.travaglini@arm.com { "cptr_el3", MISCREG_CPTR_EL3 }, 44112641Sgiacomo.travaglini@arm.com { "mdcr_el3", MISCREG_MDCR_EL3 }, 44212641Sgiacomo.travaglini@arm.com { "ttbr0_el1", MISCREG_TTBR0_EL1 }, 44312641Sgiacomo.travaglini@arm.com { "ttbr1_el1", MISCREG_TTBR1_EL1 }, 44412641Sgiacomo.travaglini@arm.com { "tcr_el1", MISCREG_TCR_EL1 }, 44512641Sgiacomo.travaglini@arm.com { "ttbr0_el2", MISCREG_TTBR0_EL2 }, 44612641Sgiacomo.travaglini@arm.com { "tcr_el2", MISCREG_TCR_EL2 }, 44712641Sgiacomo.travaglini@arm.com { "vttbr_el2", MISCREG_VTTBR_EL2 }, 44812641Sgiacomo.travaglini@arm.com { "vtcr_el2", MISCREG_VTCR_EL2 }, 44912641Sgiacomo.travaglini@arm.com { "ttbr0_el3", MISCREG_TTBR0_EL3 }, 45012641Sgiacomo.travaglini@arm.com { "tcr_el3", MISCREG_TCR_EL3 }, 45112641Sgiacomo.travaglini@arm.com { "dacr32_el2", MISCREG_DACR32_EL2 }, 45212641Sgiacomo.travaglini@arm.com { "spsr_el1", MISCREG_SPSR_EL1 }, 45312641Sgiacomo.travaglini@arm.com { "elr_el1", MISCREG_ELR_EL1 }, 45412641Sgiacomo.travaglini@arm.com { "sp_el0", MISCREG_SP_EL0 }, 45512641Sgiacomo.travaglini@arm.com { "spsel", MISCREG_SPSEL }, 45612641Sgiacomo.travaglini@arm.com { "currentel", MISCREG_CURRENTEL }, 45712641Sgiacomo.travaglini@arm.com { "nzcv", MISCREG_NZCV }, 45812641Sgiacomo.travaglini@arm.com { "daif", MISCREG_DAIF }, 45912641Sgiacomo.travaglini@arm.com { "fpcr", MISCREG_FPCR }, 46012641Sgiacomo.travaglini@arm.com { "fpsr", MISCREG_FPSR }, 46112641Sgiacomo.travaglini@arm.com { "dspsr_el0", MISCREG_DSPSR_EL0 }, 46212641Sgiacomo.travaglini@arm.com { "dlr_el0", MISCREG_DLR_EL0 }, 46312641Sgiacomo.travaglini@arm.com { "spsr_el2", MISCREG_SPSR_EL2 }, 46412641Sgiacomo.travaglini@arm.com { "elr_el2", MISCREG_ELR_EL2 }, 46512641Sgiacomo.travaglini@arm.com { "sp_el1", MISCREG_SP_EL1 }, 46612641Sgiacomo.travaglini@arm.com { "spsr_irq", MISCREG_SPSR_IRQ_AA64 }, 46712641Sgiacomo.travaglini@arm.com { "spsr_abt", MISCREG_SPSR_ABT_AA64 }, 46812641Sgiacomo.travaglini@arm.com { "spsr_und", MISCREG_SPSR_UND_AA64 }, 46912641Sgiacomo.travaglini@arm.com { "spsr_fiq", MISCREG_SPSR_FIQ_AA64 }, 47012641Sgiacomo.travaglini@arm.com { "spsr_el3", MISCREG_SPSR_EL3 }, 47112641Sgiacomo.travaglini@arm.com { "elr_el3", MISCREG_ELR_EL3 }, 47212641Sgiacomo.travaglini@arm.com { "sp_el2", MISCREG_SP_EL2 }, 47312641Sgiacomo.travaglini@arm.com { "afsr0_el1", MISCREG_AFSR0_EL1 }, 47412641Sgiacomo.travaglini@arm.com { "afsr1_el1", MISCREG_AFSR1_EL1 }, 47512641Sgiacomo.travaglini@arm.com { "esr_el1", MISCREG_ESR_EL1 }, 47612641Sgiacomo.travaglini@arm.com { "ifsr32_el2", MISCREG_IFSR32_EL2 }, 47712641Sgiacomo.travaglini@arm.com { "afsr0_el2", MISCREG_AFSR0_EL2 }, 47812641Sgiacomo.travaglini@arm.com { "afsr1_el2", MISCREG_AFSR1_EL2 }, 47912641Sgiacomo.travaglini@arm.com { "esr_el2", MISCREG_ESR_EL2 }, 48012641Sgiacomo.travaglini@arm.com { "fpexc32_el2", MISCREG_FPEXC32_EL2 }, 48112641Sgiacomo.travaglini@arm.com { "afsr0_el3", MISCREG_AFSR0_EL3 }, 48212641Sgiacomo.travaglini@arm.com { "afsr1_el3", MISCREG_AFSR1_EL3 }, 48312641Sgiacomo.travaglini@arm.com { "esr_el3", MISCREG_ESR_EL3 }, 48412641Sgiacomo.travaglini@arm.com { "far_el1", MISCREG_FAR_EL1 }, 48512641Sgiacomo.travaglini@arm.com { "far_el2", MISCREG_FAR_EL2 }, 48612641Sgiacomo.travaglini@arm.com { "hpfar_el2", MISCREG_HPFAR_EL2 }, 48712641Sgiacomo.travaglini@arm.com { "far_el3", MISCREG_FAR_EL3 }, 48812641Sgiacomo.travaglini@arm.com { "ic_ialluis", MISCREG_IC_IALLUIS }, 48912641Sgiacomo.travaglini@arm.com { "par_el1", MISCREG_PAR_EL1 }, 49012641Sgiacomo.travaglini@arm.com { "ic_iallu", MISCREG_IC_IALLU }, 49112641Sgiacomo.travaglini@arm.com { "dc_ivac_xt", MISCREG_DC_IVAC_Xt }, 49212641Sgiacomo.travaglini@arm.com { "dc_isw_xt", MISCREG_DC_ISW_Xt }, 49312641Sgiacomo.travaglini@arm.com { "at_s1e1r_xt", MISCREG_AT_S1E1R_Xt }, 49412641Sgiacomo.travaglini@arm.com { "at_s1e1w_xt", MISCREG_AT_S1E1W_Xt }, 49512641Sgiacomo.travaglini@arm.com { "at_s1e0r_xt", MISCREG_AT_S1E0R_Xt }, 49612641Sgiacomo.travaglini@arm.com { "at_s1e0w_xt", MISCREG_AT_S1E0W_Xt }, 49712641Sgiacomo.travaglini@arm.com { "dc_csw_xt", MISCREG_DC_CSW_Xt }, 49812641Sgiacomo.travaglini@arm.com { "dc_cisw_xt", MISCREG_DC_CISW_Xt }, 49912641Sgiacomo.travaglini@arm.com { "dc_zva_xt", MISCREG_DC_ZVA_Xt }, 50012641Sgiacomo.travaglini@arm.com { "ic_ivau_xt", MISCREG_IC_IVAU_Xt }, 50112641Sgiacomo.travaglini@arm.com { "dc_cvac_xt", MISCREG_DC_CVAC_Xt }, 50212641Sgiacomo.travaglini@arm.com { "dc_cvau_xt", MISCREG_DC_CVAU_Xt }, 50312641Sgiacomo.travaglini@arm.com { "dc_civac_xt", MISCREG_DC_CIVAC_Xt }, 50412641Sgiacomo.travaglini@arm.com { "at_s1e2r_xt", MISCREG_AT_S1E2R_Xt }, 50512641Sgiacomo.travaglini@arm.com { "at_s1e2w_xt", MISCREG_AT_S1E2W_Xt }, 50612641Sgiacomo.travaglini@arm.com { "at_s12e1r_xt", MISCREG_AT_S12E1R_Xt }, 50712641Sgiacomo.travaglini@arm.com { "at_s12e1w_xt", MISCREG_AT_S12E1W_Xt }, 50812641Sgiacomo.travaglini@arm.com { "at_s12e0r_xt", MISCREG_AT_S12E0R_Xt }, 50912641Sgiacomo.travaglini@arm.com { "at_s12e0w_xt", MISCREG_AT_S12E0W_Xt }, 51012641Sgiacomo.travaglini@arm.com { "at_s1e3r_xt", MISCREG_AT_S1E3R_Xt }, 51112641Sgiacomo.travaglini@arm.com { "at_s1e3w_xt", MISCREG_AT_S1E3W_Xt }, 51212641Sgiacomo.travaglini@arm.com { "tlbi_vmalle1is", MISCREG_TLBI_VMALLE1IS }, 51312641Sgiacomo.travaglini@arm.com { "tlbi_vae1is_xt", MISCREG_TLBI_VAE1IS_Xt }, 51412641Sgiacomo.travaglini@arm.com { "tlbi_aside1is_xt", MISCREG_TLBI_ASIDE1IS_Xt }, 51512641Sgiacomo.travaglini@arm.com { "tlbi_vaae1is_xt", MISCREG_TLBI_VAAE1IS_Xt }, 51612641Sgiacomo.travaglini@arm.com { "tlbi_vale1is_xt", MISCREG_TLBI_VALE1IS_Xt }, 51712641Sgiacomo.travaglini@arm.com { "tlbi_vaale1is_xt", MISCREG_TLBI_VAALE1IS_Xt }, 51812641Sgiacomo.travaglini@arm.com { "tlbi_vmalle1", MISCREG_TLBI_VMALLE1 }, 51912641Sgiacomo.travaglini@arm.com { "tlbi_vae1_xt", MISCREG_TLBI_VAE1_Xt }, 52012641Sgiacomo.travaglini@arm.com { "tlbi_aside1_xt", MISCREG_TLBI_ASIDE1_Xt }, 52112641Sgiacomo.travaglini@arm.com { "tlbi_vaae1_xt", MISCREG_TLBI_VAAE1_Xt }, 52212641Sgiacomo.travaglini@arm.com { "tlbi_vale1_xt", MISCREG_TLBI_VALE1_Xt }, 52312641Sgiacomo.travaglini@arm.com { "tlbi_vaale1_xt", MISCREG_TLBI_VAALE1_Xt }, 52412641Sgiacomo.travaglini@arm.com { "tlbi_ipas2e1is_xt", MISCREG_TLBI_IPAS2E1IS_Xt }, 52512641Sgiacomo.travaglini@arm.com { "tlbi_ipas2le1is_xt", MISCREG_TLBI_IPAS2LE1IS_Xt }, 52612641Sgiacomo.travaglini@arm.com { "tlbi_alle2is", MISCREG_TLBI_ALLE2IS }, 52712641Sgiacomo.travaglini@arm.com { "tlbi_vae2is_xt", MISCREG_TLBI_VAE2IS_Xt }, 52812641Sgiacomo.travaglini@arm.com { "tlbi_alle1is", MISCREG_TLBI_ALLE1IS }, 52912641Sgiacomo.travaglini@arm.com { "tlbi_vale2is_xt", MISCREG_TLBI_VALE2IS_Xt }, 53012641Sgiacomo.travaglini@arm.com { "tlbi_vmalls12e1is", MISCREG_TLBI_VMALLS12E1IS }, 53112641Sgiacomo.travaglini@arm.com { "tlbi_ipas2e1_xt", MISCREG_TLBI_IPAS2E1_Xt }, 53212641Sgiacomo.travaglini@arm.com { "tlbi_ipas2le1_xt", MISCREG_TLBI_IPAS2LE1_Xt }, 53312641Sgiacomo.travaglini@arm.com { "tlbi_alle2", MISCREG_TLBI_ALLE2 }, 53412641Sgiacomo.travaglini@arm.com { "tlbi_vae2_xt", MISCREG_TLBI_VAE2_Xt }, 53512641Sgiacomo.travaglini@arm.com { "tlbi_alle1", MISCREG_TLBI_ALLE1 }, 53612641Sgiacomo.travaglini@arm.com { "tlbi_vale2_xt", MISCREG_TLBI_VALE2_Xt }, 53712641Sgiacomo.travaglini@arm.com { "tlbi_vmalls12e1", MISCREG_TLBI_VMALLS12E1 }, 53812641Sgiacomo.travaglini@arm.com { "tlbi_alle3is", MISCREG_TLBI_ALLE3IS }, 53912641Sgiacomo.travaglini@arm.com { "tlbi_vae3is_xt", MISCREG_TLBI_VAE3IS_Xt }, 54012641Sgiacomo.travaglini@arm.com { "tlbi_vale3is_xt", MISCREG_TLBI_VALE3IS_Xt }, 54112641Sgiacomo.travaglini@arm.com { "tlbi_alle3", MISCREG_TLBI_ALLE3 }, 54212641Sgiacomo.travaglini@arm.com { "tlbi_vae3_xt", MISCREG_TLBI_VAE3_Xt }, 54312641Sgiacomo.travaglini@arm.com { "tlbi_vale3_xt", MISCREG_TLBI_VALE3_Xt }, 54412641Sgiacomo.travaglini@arm.com { "pmintenset_el1", MISCREG_PMINTENSET_EL1 }, 54512641Sgiacomo.travaglini@arm.com { "pmintenclr_el1", MISCREG_PMINTENCLR_EL1 }, 54612641Sgiacomo.travaglini@arm.com { "pmcr_el0", MISCREG_PMCR_EL0 }, 54712641Sgiacomo.travaglini@arm.com { "pmcntenset_el0", MISCREG_PMCNTENSET_EL0 }, 54812641Sgiacomo.travaglini@arm.com { "pmcntenclr_el0", MISCREG_PMCNTENCLR_EL0 }, 54912641Sgiacomo.travaglini@arm.com { "pmovsclr_el0", MISCREG_PMOVSCLR_EL0 }, 55012641Sgiacomo.travaglini@arm.com { "pmswinc_el0", MISCREG_PMSWINC_EL0 }, 55112641Sgiacomo.travaglini@arm.com { "pmselr_el0", MISCREG_PMSELR_EL0 }, 55212641Sgiacomo.travaglini@arm.com { "pmceid0_el0", MISCREG_PMCEID0_EL0 }, 55312641Sgiacomo.travaglini@arm.com { "pmceid1_el0", MISCREG_PMCEID1_EL0 }, 55412641Sgiacomo.travaglini@arm.com { "pmccntr_el0", MISCREG_PMCCNTR_EL0 }, 55512641Sgiacomo.travaglini@arm.com { "pmxevtyper_el0", MISCREG_PMXEVTYPER_EL0 }, 55612641Sgiacomo.travaglini@arm.com { "pmccfiltr_el0", MISCREG_PMCCFILTR_EL0 }, 55712641Sgiacomo.travaglini@arm.com { "pmxevcntr_el0", MISCREG_PMXEVCNTR_EL0 }, 55812641Sgiacomo.travaglini@arm.com { "pmuserenr_el0", MISCREG_PMUSERENR_EL0 }, 55912641Sgiacomo.travaglini@arm.com { "pmovsset_el0", MISCREG_PMOVSSET_EL0 }, 56012641Sgiacomo.travaglini@arm.com { "mair_el1", MISCREG_MAIR_EL1 }, 56112641Sgiacomo.travaglini@arm.com { "amair_el1", MISCREG_AMAIR_EL1 }, 56212641Sgiacomo.travaglini@arm.com { "mair_el2", MISCREG_MAIR_EL2 }, 56312641Sgiacomo.travaglini@arm.com { "amair_el2", MISCREG_AMAIR_EL2 }, 56412641Sgiacomo.travaglini@arm.com { "mair_el3", MISCREG_MAIR_EL3 }, 56512641Sgiacomo.travaglini@arm.com { "amair_el3", MISCREG_AMAIR_EL3 }, 56612641Sgiacomo.travaglini@arm.com { "l2ctlr_el1", MISCREG_L2CTLR_EL1 }, 56712641Sgiacomo.travaglini@arm.com { "l2ectlr_el1", MISCREG_L2ECTLR_EL1 }, 56812641Sgiacomo.travaglini@arm.com { "vbar_el1", MISCREG_VBAR_EL1 }, 56912641Sgiacomo.travaglini@arm.com { "rvbar_el1", MISCREG_RVBAR_EL1 }, 57012641Sgiacomo.travaglini@arm.com { "isr_el1", MISCREG_ISR_EL1 }, 57112641Sgiacomo.travaglini@arm.com { "vbar_el2", MISCREG_VBAR_EL2 }, 57212641Sgiacomo.travaglini@arm.com { "rvbar_el2", MISCREG_RVBAR_EL2 }, 57312641Sgiacomo.travaglini@arm.com { "vbar_el3", MISCREG_VBAR_EL3 }, 57412641Sgiacomo.travaglini@arm.com { "rvbar_el3", MISCREG_RVBAR_EL3 }, 57512641Sgiacomo.travaglini@arm.com { "rmr_el3", MISCREG_RMR_EL3 }, 57612641Sgiacomo.travaglini@arm.com { "contextidr_el1", MISCREG_CONTEXTIDR_EL1 }, 57712641Sgiacomo.travaglini@arm.com { "contextidr_el2", MISCREG_CONTEXTIDR_EL2 }, 57812641Sgiacomo.travaglini@arm.com { "tpidr_el1", MISCREG_TPIDR_EL1 }, 57912641Sgiacomo.travaglini@arm.com { "tpidr_el0", MISCREG_TPIDR_EL0 }, 58012641Sgiacomo.travaglini@arm.com { "tpidrro_el0", MISCREG_TPIDRRO_EL0 }, 58112641Sgiacomo.travaglini@arm.com { "tpidr_el2", MISCREG_TPIDR_EL2 }, 58212641Sgiacomo.travaglini@arm.com { "tpidr_el3", MISCREG_TPIDR_EL3 }, 58312641Sgiacomo.travaglini@arm.com { "cntkctl_el1", MISCREG_CNTKCTL_EL1 }, 58412641Sgiacomo.travaglini@arm.com { "cntfrq_el0", MISCREG_CNTFRQ_EL0 }, 58512641Sgiacomo.travaglini@arm.com { "cntpct_el0", MISCREG_CNTPCT_EL0 }, 58612641Sgiacomo.travaglini@arm.com { "cntvct_el0", MISCREG_CNTVCT_EL0 }, 58712641Sgiacomo.travaglini@arm.com { "cntp_tval_el0", MISCREG_CNTP_TVAL_EL0 }, 58812641Sgiacomo.travaglini@arm.com { "cntp_ctl_el0", MISCREG_CNTP_CTL_EL0 }, 58912641Sgiacomo.travaglini@arm.com { "cntp_cval_el0", MISCREG_CNTP_CVAL_EL0 }, 59012641Sgiacomo.travaglini@arm.com { "cntv_tval_el0", MISCREG_CNTV_TVAL_EL0 }, 59112641Sgiacomo.travaglini@arm.com { "cntv_ctl_el0", MISCREG_CNTV_CTL_EL0 }, 59212641Sgiacomo.travaglini@arm.com { "cntv_cval_el0", MISCREG_CNTV_CVAL_EL0 }, 59312641Sgiacomo.travaglini@arm.com { "pmevcntr0_el0", MISCREG_PMEVCNTR0_EL0 }, 59412641Sgiacomo.travaglini@arm.com { "pmevcntr1_el0", MISCREG_PMEVCNTR1_EL0 }, 59512641Sgiacomo.travaglini@arm.com { "pmevcntr2_el0", MISCREG_PMEVCNTR2_EL0 }, 59612641Sgiacomo.travaglini@arm.com { "pmevcntr3_el0", MISCREG_PMEVCNTR3_EL0 }, 59712641Sgiacomo.travaglini@arm.com { "pmevcntr4_el0", MISCREG_PMEVCNTR4_EL0 }, 59812641Sgiacomo.travaglini@arm.com { "pmevcntr5_el0", MISCREG_PMEVCNTR5_EL0 }, 59912641Sgiacomo.travaglini@arm.com { "pmevtyper0_el0", MISCREG_PMEVTYPER0_EL0 }, 60012641Sgiacomo.travaglini@arm.com { "pmevtyper1_el0", MISCREG_PMEVTYPER1_EL0 }, 60112641Sgiacomo.travaglini@arm.com { "pmevtyper2_el0", MISCREG_PMEVTYPER2_EL0 }, 60212641Sgiacomo.travaglini@arm.com { "pmevtyper3_el0", MISCREG_PMEVTYPER3_EL0 }, 60312641Sgiacomo.travaglini@arm.com { "pmevtyper4_el0", MISCREG_PMEVTYPER4_EL0 }, 60412641Sgiacomo.travaglini@arm.com { "pmevtyper5_el0", MISCREG_PMEVTYPER5_EL0 }, 60512641Sgiacomo.travaglini@arm.com { "cntvoff_el2", MISCREG_CNTVOFF_EL2 }, 60612641Sgiacomo.travaglini@arm.com { "cnthctl_el2", MISCREG_CNTHCTL_EL2 }, 60712641Sgiacomo.travaglini@arm.com { "cnthp_tval_el2", MISCREG_CNTHP_TVAL_EL2 }, 60812641Sgiacomo.travaglini@arm.com { "cnthp_ctl_el2", MISCREG_CNTHP_CTL_EL2 }, 60912641Sgiacomo.travaglini@arm.com { "cnthp_cval_el2", MISCREG_CNTHP_CVAL_EL2 }, 61012641Sgiacomo.travaglini@arm.com { "cntps_tval_el1", MISCREG_CNTPS_TVAL_EL1 }, 61112641Sgiacomo.travaglini@arm.com { "cntps_ctl_el1", MISCREG_CNTPS_CTL_EL1 }, 61212641Sgiacomo.travaglini@arm.com { "cntps_cval_el1", MISCREG_CNTPS_CVAL_EL1 }, 61312641Sgiacomo.travaglini@arm.com { "il1data0_el1", MISCREG_IL1DATA0_EL1 }, 61412641Sgiacomo.travaglini@arm.com { "il1data1_el1", MISCREG_IL1DATA1_EL1 }, 61512641Sgiacomo.travaglini@arm.com { "il1data2_el1", MISCREG_IL1DATA2_EL1 }, 61612641Sgiacomo.travaglini@arm.com { "il1data3_el1", MISCREG_IL1DATA3_EL1 }, 61712641Sgiacomo.travaglini@arm.com { "dl1data0_el1", MISCREG_DL1DATA0_EL1 }, 61812641Sgiacomo.travaglini@arm.com { "dl1data1_el1", MISCREG_DL1DATA1_EL1 }, 61912641Sgiacomo.travaglini@arm.com { "dl1data2_el1", MISCREG_DL1DATA2_EL1 }, 62012641Sgiacomo.travaglini@arm.com { "dl1data3_el1", MISCREG_DL1DATA3_EL1 }, 62112641Sgiacomo.travaglini@arm.com { "dl1data4_el1", MISCREG_DL1DATA4_EL1 }, 62212641Sgiacomo.travaglini@arm.com { "l2actlr_el1", MISCREG_L2ACTLR_EL1 }, 62312641Sgiacomo.travaglini@arm.com { "cpuactlr_el1", MISCREG_CPUACTLR_EL1 }, 62412641Sgiacomo.travaglini@arm.com { "cpuectlr_el1", MISCREG_CPUECTLR_EL1 }, 62512641Sgiacomo.travaglini@arm.com { "cpumerrsr_el1", MISCREG_CPUMERRSR_EL1 }, 62612641Sgiacomo.travaglini@arm.com { "l2merrsr_el1", MISCREG_L2MERRSR_EL1 }, 62712641Sgiacomo.travaglini@arm.com { "cbar_el1", MISCREG_CBAR_EL1 }, 62812641Sgiacomo.travaglini@arm.com}; 62912641Sgiacomo.travaglini@arm.com 63012641Sgiacomo.travaglini@arm.comvoid 63112641Sgiacomo.travaglini@arm.comTarmacParserRecord::TarmacParserRecordEvent::process() 63212641Sgiacomo.travaglini@arm.com{ 63312641Sgiacomo.travaglini@arm.com ostream &outs = Trace::output(); 63412641Sgiacomo.travaglini@arm.com 63512641Sgiacomo.travaglini@arm.com list<ParserRegEntry>::iterator it = destRegRecords.begin(), 63612641Sgiacomo.travaglini@arm.com end = destRegRecords.end(); 63712641Sgiacomo.travaglini@arm.com 63812641Sgiacomo.travaglini@arm.com uint64_t value_hi, value_lo; 63912641Sgiacomo.travaglini@arm.com bool check_value_hi = false; 64012641Sgiacomo.travaglini@arm.com 64112641Sgiacomo.travaglini@arm.com for (; it != end; ++it) { 64212641Sgiacomo.travaglini@arm.com switch (it->type) { 64312641Sgiacomo.travaglini@arm.com case REG_R: 64412641Sgiacomo.travaglini@arm.com case REG_X: 64512641Sgiacomo.travaglini@arm.com value_lo = thread->readIntReg(it->index); 64612641Sgiacomo.travaglini@arm.com break; 64712641Sgiacomo.travaglini@arm.com case REG_S: 64812641Sgiacomo.travaglini@arm.com if (instRecord.isetstate == ISET_A64) 64912641Sgiacomo.travaglini@arm.com value_lo = thread->readFloatRegBits(it->index * 4); 65012641Sgiacomo.travaglini@arm.com else 65112641Sgiacomo.travaglini@arm.com value_lo = thread->readFloatRegBits(it->index); 65212641Sgiacomo.travaglini@arm.com break; 65312641Sgiacomo.travaglini@arm.com case REG_D: 65412641Sgiacomo.travaglini@arm.com if (instRecord.isetstate == ISET_A64) 65512641Sgiacomo.travaglini@arm.com value_lo = thread->readFloatRegBits(it->index * 4) | 65612641Sgiacomo.travaglini@arm.com (uint64_t) thread->readFloatRegBits(it->index * 4 + 1) << 65712641Sgiacomo.travaglini@arm.com 32; 65812641Sgiacomo.travaglini@arm.com else 65912641Sgiacomo.travaglini@arm.com value_lo = thread->readFloatRegBits(it->index * 2) | 66012641Sgiacomo.travaglini@arm.com (uint64_t) thread->readFloatRegBits(it->index * 2 + 1) << 66112641Sgiacomo.travaglini@arm.com 32; 66212641Sgiacomo.travaglini@arm.com break; 66312641Sgiacomo.travaglini@arm.com case REG_Q: 66412641Sgiacomo.travaglini@arm.com check_value_hi = true; 66512641Sgiacomo.travaglini@arm.com if (instRecord.isetstate == ISET_A64) { 66612641Sgiacomo.travaglini@arm.com value_lo = thread->readFloatRegBits(it->index * 4) | 66712641Sgiacomo.travaglini@arm.com (uint64_t) thread->readFloatRegBits(it->index * 4 + 1) << 66812641Sgiacomo.travaglini@arm.com 32; 66912641Sgiacomo.travaglini@arm.com value_hi = thread->readFloatRegBits(it->index * 4 + 2) | 67012641Sgiacomo.travaglini@arm.com (uint64_t) thread->readFloatRegBits(it->index * 4 + 3) << 67112641Sgiacomo.travaglini@arm.com 32; 67212641Sgiacomo.travaglini@arm.com } else { 67312641Sgiacomo.travaglini@arm.com value_lo = thread->readFloatRegBits(it->index * 2) | 67412641Sgiacomo.travaglini@arm.com (uint64_t) thread->readFloatRegBits(it->index * 2 + 1) << 67512641Sgiacomo.travaglini@arm.com 32; 67612641Sgiacomo.travaglini@arm.com value_hi = thread->readFloatRegBits(it->index * 2 + 2) | 67712641Sgiacomo.travaglini@arm.com (uint64_t) thread->readFloatRegBits(it->index * 2 + 3) << 67812641Sgiacomo.travaglini@arm.com 32; 67912641Sgiacomo.travaglini@arm.com } 68012641Sgiacomo.travaglini@arm.com break; 68112641Sgiacomo.travaglini@arm.com case REG_MISC: 68212641Sgiacomo.travaglini@arm.com if (it->index == MISCREG_CPSR) { 68312641Sgiacomo.travaglini@arm.com // Read condition codes from aliased integer regs 68412641Sgiacomo.travaglini@arm.com CPSR cpsr = thread->readMiscRegNoEffect(it->index); 68512641Sgiacomo.travaglini@arm.com cpsr.nz = thread->readCCReg(CCREG_NZ); 68612641Sgiacomo.travaglini@arm.com cpsr.c = thread->readCCReg(CCREG_C); 68712641Sgiacomo.travaglini@arm.com cpsr.v = thread->readCCReg(CCREG_V); 68812641Sgiacomo.travaglini@arm.com cpsr.ge = thread->readCCReg(CCREG_GE); 68912641Sgiacomo.travaglini@arm.com value_lo = cpsr; 69012641Sgiacomo.travaglini@arm.com } else if (it->index == MISCREG_NZCV) { 69112641Sgiacomo.travaglini@arm.com CPSR cpsr = 0; 69212641Sgiacomo.travaglini@arm.com cpsr.nz = thread->readCCReg(CCREG_NZ); 69312641Sgiacomo.travaglini@arm.com cpsr.c = thread->readCCReg(CCREG_C); 69412641Sgiacomo.travaglini@arm.com cpsr.v = thread->readCCReg(CCREG_V); 69512641Sgiacomo.travaglini@arm.com value_lo = cpsr; 69612641Sgiacomo.travaglini@arm.com } else { 69712641Sgiacomo.travaglini@arm.com value_lo = thread->readMiscRegNoEffect(it->index); 69812641Sgiacomo.travaglini@arm.com } 69912641Sgiacomo.travaglini@arm.com break; 70012641Sgiacomo.travaglini@arm.com default: 70112641Sgiacomo.travaglini@arm.com panic("Unknown TARMAC trace record type!"); 70212641Sgiacomo.travaglini@arm.com } 70312641Sgiacomo.travaglini@arm.com 70412641Sgiacomo.travaglini@arm.com if (value_lo != it->valueLo || 70512641Sgiacomo.travaglini@arm.com (check_value_hi && (value_hi != it->valueHi))) { 70612641Sgiacomo.travaglini@arm.com if (!mismatch) 70712641Sgiacomo.travaglini@arm.com TarmacParserRecord::printMismatchHeader(inst, pc); 70812641Sgiacomo.travaglini@arm.com outs << "diff> [" << it->repr << "] gem5: 0x"; 70912641Sgiacomo.travaglini@arm.com if (check_value_hi) 71012641Sgiacomo.travaglini@arm.com outs << hex << setfill('0') << setw(16) << value_hi 71112641Sgiacomo.travaglini@arm.com << setfill('0') << setw(16) << value_lo; 71212641Sgiacomo.travaglini@arm.com else 71312641Sgiacomo.travaglini@arm.com outs << hex << value_lo; 71412641Sgiacomo.travaglini@arm.com outs << ", TARMAC: 0x"; 71512641Sgiacomo.travaglini@arm.com if (check_value_hi) 71612641Sgiacomo.travaglini@arm.com outs << hex << setfill('0') << setw(16) << it->valueHi 71712641Sgiacomo.travaglini@arm.com << setfill('0') << setw(16) << it->valueLo << endl; 71812641Sgiacomo.travaglini@arm.com else 71912641Sgiacomo.travaglini@arm.com outs << it->valueLo << endl; 72012641Sgiacomo.travaglini@arm.com mismatch = true; 72112641Sgiacomo.travaglini@arm.com } 72212641Sgiacomo.travaglini@arm.com 72312641Sgiacomo.travaglini@arm.com check_value_hi = false; 72412641Sgiacomo.travaglini@arm.com } 72512641Sgiacomo.travaglini@arm.com destRegRecords.clear(); 72612641Sgiacomo.travaglini@arm.com 72712641Sgiacomo.travaglini@arm.com if (mismatchOnPcOrOpcode && (parent.exitOnDiff || 72812641Sgiacomo.travaglini@arm.com parent.exitOnInsnDiff)) 72912641Sgiacomo.travaglini@arm.com exitSimLoop("a mismatch with the TARMAC trace has been detected " 73012641Sgiacomo.travaglini@arm.com "on PC or opcode", 1); 73112641Sgiacomo.travaglini@arm.com if (mismatch && parent.exitOnDiff) 73212641Sgiacomo.travaglini@arm.com exitSimLoop("a mismatch with the TARMAC trace has been detected " 73312641Sgiacomo.travaglini@arm.com "on data value", 1); 73412641Sgiacomo.travaglini@arm.com} 73512641Sgiacomo.travaglini@arm.com 73612641Sgiacomo.travaglini@arm.comconst char * 73712641Sgiacomo.travaglini@arm.comTarmacParserRecord::TarmacParserRecordEvent::description() const 73812641Sgiacomo.travaglini@arm.com{ 73912641Sgiacomo.travaglini@arm.com return "TARMAC parser record event"; 74012641Sgiacomo.travaglini@arm.com} 74112641Sgiacomo.travaglini@arm.com 74212641Sgiacomo.travaglini@arm.com 74312641Sgiacomo.travaglini@arm.comvoid 74412641Sgiacomo.travaglini@arm.comTarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst, 74512641Sgiacomo.travaglini@arm.com TheISA::PCState pc) 74612641Sgiacomo.travaglini@arm.com{ 74712641Sgiacomo.travaglini@arm.com ostream &outs = Trace::output(); 74812641Sgiacomo.travaglini@arm.com outs << "\nMismatch between gem5 and TARMAC trace @ " << dec << curTick() 74912641Sgiacomo.travaglini@arm.com << " ticks\n" 75012641Sgiacomo.travaglini@arm.com << "[seq_num: " << dec << instRecord.seq_num 75112641Sgiacomo.travaglini@arm.com << ", opcode: 0x" << hex << (staticInst->machInst & 0xffffffff) 75212641Sgiacomo.travaglini@arm.com << ", PC: 0x" << pc.pc() 75312641Sgiacomo.travaglini@arm.com << ", disasm: " << staticInst->disassemble(pc.pc()) << "]" 75412641Sgiacomo.travaglini@arm.com << endl; 75512641Sgiacomo.travaglini@arm.com} 75612641Sgiacomo.travaglini@arm.com 75712641Sgiacomo.travaglini@arm.comTarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread, 75812641Sgiacomo.travaglini@arm.com const StaticInstPtr _staticInst, 75912641Sgiacomo.travaglini@arm.com PCState _pc, 76012641Sgiacomo.travaglini@arm.com TarmacParser& _parent, 76112641Sgiacomo.travaglini@arm.com const StaticInstPtr _macroStaticInst) 76212641Sgiacomo.travaglini@arm.com : TarmacBaseRecord(_when, _thread, _staticInst, 76312641Sgiacomo.travaglini@arm.com _pc, _macroStaticInst), 76412641Sgiacomo.travaglini@arm.com parsingStarted(false), mismatch(false), 76512641Sgiacomo.travaglini@arm.com mismatchOnPcOrOpcode(false), parent(_parent) 76612641Sgiacomo.travaglini@arm.com{ 76712749Sgiacomo.travaglini@arm.com memReq = std::make_shared<Request>(); 76812641Sgiacomo.travaglini@arm.com} 76912641Sgiacomo.travaglini@arm.com 77012641Sgiacomo.travaglini@arm.comvoid 77112641Sgiacomo.travaglini@arm.comTarmacParserRecord::dump() 77212641Sgiacomo.travaglini@arm.com{ 77312641Sgiacomo.travaglini@arm.com ostream &outs = Trace::output(); 77412641Sgiacomo.travaglini@arm.com 77512641Sgiacomo.travaglini@arm.com // By default TARMAC splits memory accesses into 4-byte chunks (see 77612641Sgiacomo.travaglini@arm.com // 'loadstore-display-width' option in TARMAC plugin) 77712641Sgiacomo.travaglini@arm.com uint32_t written_data = 0; 77812641Sgiacomo.travaglini@arm.com unsigned mem_flags = TheISA::TLB::MustBeOne | 3 | 77912641Sgiacomo.travaglini@arm.com TheISA::TLB::AllowUnaligned; 78012641Sgiacomo.travaglini@arm.com 78112641Sgiacomo.travaglini@arm.com ISetState isetstate; 78212641Sgiacomo.travaglini@arm.com 78312641Sgiacomo.travaglini@arm.com if (!staticInst->isMicroop() || staticInst->isLastMicroop()) { 78412641Sgiacomo.travaglini@arm.com 78512641Sgiacomo.travaglini@arm.com if (parent.macroopInProgress && !staticInst->isLastMicroop()) { 78612641Sgiacomo.travaglini@arm.com // A microop faulted and it was not the last microop -> advance 78712641Sgiacomo.travaglini@arm.com // TARMAC trace to next instruction 78812641Sgiacomo.travaglini@arm.com advanceTrace(); 78912641Sgiacomo.travaglini@arm.com } 79012641Sgiacomo.travaglini@arm.com 79112641Sgiacomo.travaglini@arm.com parent.macroopInProgress = false; 79212641Sgiacomo.travaglini@arm.com 79312641Sgiacomo.travaglini@arm.com auto arm_inst = static_cast<const ArmStaticInst*>( 79412641Sgiacomo.travaglini@arm.com staticInst.get() 79512641Sgiacomo.travaglini@arm.com ); 79612641Sgiacomo.travaglini@arm.com 79712641Sgiacomo.travaglini@arm.com while (advanceTrace()) { 79812641Sgiacomo.travaglini@arm.com switch (currRecordType) { 79912641Sgiacomo.travaglini@arm.com 80012641Sgiacomo.travaglini@arm.com case TARMAC_INST: 80112641Sgiacomo.travaglini@arm.com parsingStarted = true; 80212641Sgiacomo.travaglini@arm.com if (pc.instAddr() != instRecord.addr) { 80312641Sgiacomo.travaglini@arm.com if (!mismatch) 80412641Sgiacomo.travaglini@arm.com printMismatchHeader(staticInst, pc); 80512641Sgiacomo.travaglini@arm.com outs << "diff> [PC] gem5: 0x" << hex << pc.instAddr() 80612641Sgiacomo.travaglini@arm.com << ", TARMAC: 0x" << instRecord.addr << endl; 80712641Sgiacomo.travaglini@arm.com mismatch = true; 80812641Sgiacomo.travaglini@arm.com mismatchOnPcOrOpcode = true; 80912641Sgiacomo.travaglini@arm.com } 81012641Sgiacomo.travaglini@arm.com 81112641Sgiacomo.travaglini@arm.com if (arm_inst->encoding() != instRecord.opcode) { 81212641Sgiacomo.travaglini@arm.com if (!mismatch) 81312641Sgiacomo.travaglini@arm.com printMismatchHeader(staticInst, pc); 81412641Sgiacomo.travaglini@arm.com outs << "diff> [opcode] gem5: 0x" << hex 81512641Sgiacomo.travaglini@arm.com << arm_inst->encoding() 81612641Sgiacomo.travaglini@arm.com << ", TARMAC: 0x" << instRecord.opcode << endl; 81712641Sgiacomo.travaglini@arm.com mismatch = true; 81812641Sgiacomo.travaglini@arm.com mismatchOnPcOrOpcode = true; 81912641Sgiacomo.travaglini@arm.com } 82012641Sgiacomo.travaglini@arm.com 82112641Sgiacomo.travaglini@arm.com // Set the Instruction set state. 82212641Sgiacomo.travaglini@arm.com isetstate = pcToISetState(pc); 82312641Sgiacomo.travaglini@arm.com 82412641Sgiacomo.travaglini@arm.com if (instRecord.isetstate != isetstate && 82512641Sgiacomo.travaglini@arm.com isetstate != ISET_UNSUPPORTED) { 82612641Sgiacomo.travaglini@arm.com if (!mismatch) 82712641Sgiacomo.travaglini@arm.com printMismatchHeader(staticInst, pc); 82812641Sgiacomo.travaglini@arm.com outs << "diff> [iset_state] gem5: " 82912641Sgiacomo.travaglini@arm.com << iSetStateToStr(isetstate) 83012641Sgiacomo.travaglini@arm.com << ", TARMAC: " 83112641Sgiacomo.travaglini@arm.com << iSetStateToStr(instRecord.isetstate); 83212641Sgiacomo.travaglini@arm.com mismatch = true; 83312641Sgiacomo.travaglini@arm.com } 83412641Sgiacomo.travaglini@arm.com 83512641Sgiacomo.travaglini@arm.com // TODO(Giacomo): add support for predicate and mode checking 83612641Sgiacomo.travaglini@arm.com break; 83712641Sgiacomo.travaglini@arm.com 83812641Sgiacomo.travaglini@arm.com case TARMAC_REG: 83912641Sgiacomo.travaglini@arm.com destRegRecords.push_back(regRecord); 84012641Sgiacomo.travaglini@arm.com break; 84112641Sgiacomo.travaglini@arm.com 84212641Sgiacomo.travaglini@arm.com case TARMAC_MEM: 84312641Sgiacomo.travaglini@arm.com if (!readMemNoEffect(memRecord.addr, (uint8_t*) &written_data, 84412641Sgiacomo.travaglini@arm.com memRecord.size, mem_flags)) 84512641Sgiacomo.travaglini@arm.com break; 84612641Sgiacomo.travaglini@arm.com if (written_data != memRecord.data) { 84712641Sgiacomo.travaglini@arm.com if (!mismatch) 84812641Sgiacomo.travaglini@arm.com printMismatchHeader(staticInst, pc); 84912641Sgiacomo.travaglini@arm.com outs << "diff> [mem(0x" << hex << memRecord.addr 85012641Sgiacomo.travaglini@arm.com << ")] gem5: 0x" << written_data 85112641Sgiacomo.travaglini@arm.com << ", TARMAC: 0x" << memRecord.data 85212641Sgiacomo.travaglini@arm.com << endl; 85312641Sgiacomo.travaglini@arm.com } 85412641Sgiacomo.travaglini@arm.com break; 85512641Sgiacomo.travaglini@arm.com 85612641Sgiacomo.travaglini@arm.com case TARMAC_UNSUPPORTED: 85712641Sgiacomo.travaglini@arm.com break; 85812641Sgiacomo.travaglini@arm.com 85912641Sgiacomo.travaglini@arm.com default: 86012641Sgiacomo.travaglini@arm.com panic("Unknown TARMAC trace record type!"); 86112641Sgiacomo.travaglini@arm.com } 86212641Sgiacomo.travaglini@arm.com } 86312641Sgiacomo.travaglini@arm.com // We are done with the current instruction, i.e. all the corresponding 86412641Sgiacomo.travaglini@arm.com // entries in the TARMAC trace have been parsed 86512641Sgiacomo.travaglini@arm.com if (destRegRecords.size()) { 86612641Sgiacomo.travaglini@arm.com TarmacParserRecordEvent *event = new TarmacParserRecordEvent( 86712641Sgiacomo.travaglini@arm.com parent, thread, staticInst, pc, mismatch, 86812641Sgiacomo.travaglini@arm.com mismatchOnPcOrOpcode); 86912641Sgiacomo.travaglini@arm.com mainEventQueue[0]->schedule(event, curTick()); 87012641Sgiacomo.travaglini@arm.com } else if (mismatchOnPcOrOpcode && (parent.exitOnDiff || 87112641Sgiacomo.travaglini@arm.com parent.exitOnInsnDiff)) { 87212641Sgiacomo.travaglini@arm.com exitSimLoop("a mismatch with the TARMAC trace has been detected " 87312641Sgiacomo.travaglini@arm.com "on PC or opcode", 1); 87412641Sgiacomo.travaglini@arm.com } 87512641Sgiacomo.travaglini@arm.com } else { 87612641Sgiacomo.travaglini@arm.com parent.macroopInProgress = true; 87712641Sgiacomo.travaglini@arm.com } 87812641Sgiacomo.travaglini@arm.com} 87912641Sgiacomo.travaglini@arm.com 88012641Sgiacomo.travaglini@arm.combool 88112641Sgiacomo.travaglini@arm.comTarmacParserRecord::advanceTrace() 88212641Sgiacomo.travaglini@arm.com{ 88312641Sgiacomo.travaglini@arm.com ifstream& trace = parent.trace; 88412641Sgiacomo.travaglini@arm.com trace >> hex; // All integer values are in hex base 88512641Sgiacomo.travaglini@arm.com 88612641Sgiacomo.travaglini@arm.com if (buf[0] != 'I') { 88712641Sgiacomo.travaglini@arm.com trace >> buf; 88812641Sgiacomo.travaglini@arm.com if (trace.eof()) 88912641Sgiacomo.travaglini@arm.com return false; 89012641Sgiacomo.travaglini@arm.com trace >> buf >> buf; 89112641Sgiacomo.travaglini@arm.com if (parent.cpuId) { 89212641Sgiacomo.travaglini@arm.com assert((buf[0] == 'c') && (buf[1] == 'p') && (buf[2] == 'u')); 89312641Sgiacomo.travaglini@arm.com trace >> buf; 89412641Sgiacomo.travaglini@arm.com } 89512641Sgiacomo.travaglini@arm.com } 89612641Sgiacomo.travaglini@arm.com 89712641Sgiacomo.travaglini@arm.com if (trace.eof()) 89812641Sgiacomo.travaglini@arm.com return false; 89912641Sgiacomo.travaglini@arm.com 90012641Sgiacomo.travaglini@arm.com if (buf[0] == 'I') { 90112641Sgiacomo.travaglini@arm.com // Instruction trace record 90212641Sgiacomo.travaglini@arm.com if (parsingStarted) 90312641Sgiacomo.travaglini@arm.com return false; 90412641Sgiacomo.travaglini@arm.com currRecordType = TARMAC_INST; 90512641Sgiacomo.travaglini@arm.com instRecord.taken = (buf[1] == 'T'); 90612641Sgiacomo.travaglini@arm.com trace >> buf; 90712641Sgiacomo.travaglini@arm.com instRecord.seq_num = atoi(&buf[1]); 90812641Sgiacomo.travaglini@arm.com trace >> instRecord.addr; 90912641Sgiacomo.travaglini@arm.com char c = trace.peek(); 91012641Sgiacomo.travaglini@arm.com if (c == ':') { 91112641Sgiacomo.travaglini@arm.com // Skip phys. address and _S/_NS suffix 91212641Sgiacomo.travaglini@arm.com trace >> c >> buf; 91312641Sgiacomo.travaglini@arm.com } 91412641Sgiacomo.travaglini@arm.com trace >> instRecord.opcode; 91512641Sgiacomo.travaglini@arm.com trace >> buf; 91612641Sgiacomo.travaglini@arm.com switch (buf[0]) { 91712641Sgiacomo.travaglini@arm.com case 'A': 91812641Sgiacomo.travaglini@arm.com instRecord.isetstate = ISET_ARM; 91912641Sgiacomo.travaglini@arm.com break; 92012641Sgiacomo.travaglini@arm.com case 'T': 92112641Sgiacomo.travaglini@arm.com instRecord.isetstate = ISET_THUMB; 92212641Sgiacomo.travaglini@arm.com break; 92312641Sgiacomo.travaglini@arm.com case 'O': 92412641Sgiacomo.travaglini@arm.com instRecord.isetstate = ISET_A64; 92512641Sgiacomo.travaglini@arm.com break; 92612641Sgiacomo.travaglini@arm.com default: 92712641Sgiacomo.travaglini@arm.com warn("Invalid TARMAC trace record (seq_num: %lld)", 92812641Sgiacomo.travaglini@arm.com instRecord.seq_num); 92912641Sgiacomo.travaglini@arm.com instRecord.isetstate = ISET_UNSUPPORTED; 93012641Sgiacomo.travaglini@arm.com currRecordType = TARMAC_UNSUPPORTED; 93112641Sgiacomo.travaglini@arm.com break; 93212641Sgiacomo.travaglini@arm.com } 93312641Sgiacomo.travaglini@arm.com trace.ignore(MaxLineLength, '\n'); 93412641Sgiacomo.travaglini@arm.com buf[0] = 0; 93512641Sgiacomo.travaglini@arm.com } else if (buf[0] == 'R') { 93612641Sgiacomo.travaglini@arm.com // Register trace record 93712641Sgiacomo.travaglini@arm.com currRecordType = TARMAC_REG; 93812641Sgiacomo.travaglini@arm.com trace >> buf; 93912641Sgiacomo.travaglini@arm.com strcpy(regRecord.repr, buf); 94012641Sgiacomo.travaglini@arm.com if (buf[0] == 'r' && isdigit(buf[1])) { 94112641Sgiacomo.travaglini@arm.com // R register 94212641Sgiacomo.travaglini@arm.com regRecord.type = REG_R; 94312641Sgiacomo.travaglini@arm.com int base_index = atoi(&buf[1]); 94412641Sgiacomo.travaglini@arm.com char* pch = strchr(buf, '_'); 94512641Sgiacomo.travaglini@arm.com if (pch == NULL) { 94612641Sgiacomo.travaglini@arm.com regRecord.index = INTREG_USR(base_index); 94712641Sgiacomo.travaglini@arm.com } else { 94812641Sgiacomo.travaglini@arm.com ++pch; 94912641Sgiacomo.travaglini@arm.com if (strncmp(pch, "usr", 3) == 0) 95012641Sgiacomo.travaglini@arm.com regRecord.index = INTREG_USR(base_index); 95112641Sgiacomo.travaglini@arm.com else if (strncmp(pch, "fiq", 3) == 0) 95212641Sgiacomo.travaglini@arm.com regRecord.index = INTREG_FIQ(base_index); 95312641Sgiacomo.travaglini@arm.com else if (strncmp(pch, "irq", 3) == 0) 95412641Sgiacomo.travaglini@arm.com regRecord.index = INTREG_IRQ(base_index); 95512641Sgiacomo.travaglini@arm.com else if (strncmp(pch, "svc", 3) == 0) 95612641Sgiacomo.travaglini@arm.com regRecord.index = INTREG_SVC(base_index); 95712641Sgiacomo.travaglini@arm.com else if (strncmp(pch, "mon", 3) == 0) 95812641Sgiacomo.travaglini@arm.com regRecord.index = INTREG_MON(base_index); 95912641Sgiacomo.travaglini@arm.com else if (strncmp(pch, "abt", 3) == 0) 96012641Sgiacomo.travaglini@arm.com regRecord.index = INTREG_ABT(base_index); 96112641Sgiacomo.travaglini@arm.com else if (strncmp(pch, "und", 3) == 0) 96212641Sgiacomo.travaglini@arm.com regRecord.index = INTREG_UND(base_index); 96312641Sgiacomo.travaglini@arm.com else if (strncmp(pch, "hyp", 3) == 0) 96412641Sgiacomo.travaglini@arm.com regRecord.index = INTREG_HYP(base_index); 96512641Sgiacomo.travaglini@arm.com } 96612641Sgiacomo.travaglini@arm.com // A64 register names are capitalized in AEM TARMAC, unlike A32 96712641Sgiacomo.travaglini@arm.com } else if (buf[0] == 'X' && isdigit(buf[1])) { 96812641Sgiacomo.travaglini@arm.com // X register (A64) 96912641Sgiacomo.travaglini@arm.com regRecord.type = REG_X; 97012641Sgiacomo.travaglini@arm.com regRecord.index = atoi(&buf[1]); 97112641Sgiacomo.travaglini@arm.com } else if (buf[0] == 's' && isdigit(buf[1])) { 97212641Sgiacomo.travaglini@arm.com // S register 97312641Sgiacomo.travaglini@arm.com regRecord.type = REG_S; 97412641Sgiacomo.travaglini@arm.com regRecord.index = atoi(&buf[1]); 97512641Sgiacomo.travaglini@arm.com } else if (buf[0] == 'd' && isdigit(buf[1])) { 97612641Sgiacomo.travaglini@arm.com // D register 97712641Sgiacomo.travaglini@arm.com regRecord.type = REG_D; 97812641Sgiacomo.travaglini@arm.com regRecord.index = atoi(&buf[1]); 97912641Sgiacomo.travaglini@arm.com } else if (buf[0] == 'q' && isdigit(buf[1])) { 98012641Sgiacomo.travaglini@arm.com // Q register 98112641Sgiacomo.travaglini@arm.com regRecord.type = REG_Q; 98212641Sgiacomo.travaglini@arm.com regRecord.index = atoi(&buf[1]); 98312641Sgiacomo.travaglini@arm.com } else if (strncmp(buf, "SP_EL", 5) == 0) { 98412641Sgiacomo.travaglini@arm.com // A64 stack pointer 98512641Sgiacomo.travaglini@arm.com regRecord.type = REG_X; 98612641Sgiacomo.travaglini@arm.com regRecord.index = INTREG_SP0 + atoi(&buf[5]); 98712641Sgiacomo.travaglini@arm.com } else if (miscRegMap.count(buf)) { 98812641Sgiacomo.travaglini@arm.com // Misc. register 98912641Sgiacomo.travaglini@arm.com regRecord.type = REG_MISC; 99012641Sgiacomo.travaglini@arm.com regRecord.index = miscRegMap[buf]; 99112641Sgiacomo.travaglini@arm.com } else { 99212641Sgiacomo.travaglini@arm.com // Try match with upper case name (misc. register) 99312641Sgiacomo.travaglini@arm.com string reg_name = buf; 99412641Sgiacomo.travaglini@arm.com transform(reg_name.begin(), reg_name.end(), reg_name.begin(), 99512641Sgiacomo.travaglini@arm.com ::tolower); 99612641Sgiacomo.travaglini@arm.com if (miscRegMap.count(reg_name.c_str())) { 99712641Sgiacomo.travaglini@arm.com regRecord.type = REG_MISC; 99812641Sgiacomo.travaglini@arm.com regRecord.index = miscRegMap[reg_name.c_str()]; 99912641Sgiacomo.travaglini@arm.com } else { 100012641Sgiacomo.travaglini@arm.com warn("Unknown register in TARMAC trace (%s).\n", buf); 100112641Sgiacomo.travaglini@arm.com currRecordType = TARMAC_UNSUPPORTED; 100212641Sgiacomo.travaglini@arm.com trace.ignore(MaxLineLength, '\n'); 100312641Sgiacomo.travaglini@arm.com buf[0] = 0; 100412641Sgiacomo.travaglini@arm.com return true; 100512641Sgiacomo.travaglini@arm.com } 100612641Sgiacomo.travaglini@arm.com } 100712641Sgiacomo.travaglini@arm.com if (regRecord.type == REG_Q) { 100812641Sgiacomo.travaglini@arm.com trace.ignore(); 100912641Sgiacomo.travaglini@arm.com trace.get(buf, 17); 101012641Sgiacomo.travaglini@arm.com // buf[16] = '\0'; 101112641Sgiacomo.travaglini@arm.com regRecord.valueHi = strtoull(buf, NULL, 16); 101212641Sgiacomo.travaglini@arm.com trace.get(buf, 17); 101312641Sgiacomo.travaglini@arm.com // buf[16] = '\0'; 101412641Sgiacomo.travaglini@arm.com regRecord.valueLo = strtoull(buf, NULL, 16); 101512641Sgiacomo.travaglini@arm.com } else { 101612641Sgiacomo.travaglini@arm.com trace >> regRecord.valueLo; 101712641Sgiacomo.travaglini@arm.com char c = trace.peek(); 101812641Sgiacomo.travaglini@arm.com if (c == ':') { 101912641Sgiacomo.travaglini@arm.com // 64-bit value with colon in the middle 102012641Sgiacomo.travaglini@arm.com uint64_t lsw = 0; 102112641Sgiacomo.travaglini@arm.com trace >> c >> lsw; 102212641Sgiacomo.travaglini@arm.com regRecord.valueLo = (regRecord.valueLo << 32) | lsw; 102312641Sgiacomo.travaglini@arm.com } 102412641Sgiacomo.travaglini@arm.com } 102512641Sgiacomo.travaglini@arm.com trace.ignore(MaxLineLength, '\n'); 102612641Sgiacomo.travaglini@arm.com buf[0] = 0; 102712641Sgiacomo.travaglini@arm.com } else if (buf[0] == 'M' && (parent.memWrCheck && buf[1] == 'W')) { 102812641Sgiacomo.travaglini@arm.com currRecordType = TARMAC_MEM; 102912641Sgiacomo.travaglini@arm.com memRecord.size = atoi(&buf[2]); 103012641Sgiacomo.travaglini@arm.com trace >> memRecord.addr; 103112641Sgiacomo.travaglini@arm.com char c = trace.peek(); 103212641Sgiacomo.travaglini@arm.com if (c == ':') { 103312641Sgiacomo.travaglini@arm.com // Skip phys. address and _S/_NS suffix 103412641Sgiacomo.travaglini@arm.com trace >> c >> buf; 103512641Sgiacomo.travaglini@arm.com } 103612641Sgiacomo.travaglini@arm.com trace >> memRecord.data; 103712641Sgiacomo.travaglini@arm.com trace.ignore(MaxLineLength, '\n'); 103812641Sgiacomo.travaglini@arm.com buf[0] = 0; 103912641Sgiacomo.travaglini@arm.com } else { 104012641Sgiacomo.travaglini@arm.com currRecordType = TARMAC_UNSUPPORTED; 104112641Sgiacomo.travaglini@arm.com trace.ignore(MaxLineLength, '\n'); 104212641Sgiacomo.travaglini@arm.com buf[0] = 0; 104312641Sgiacomo.travaglini@arm.com } 104412641Sgiacomo.travaglini@arm.com 104512641Sgiacomo.travaglini@arm.com return true; 104612641Sgiacomo.travaglini@arm.com} 104712641Sgiacomo.travaglini@arm.com 104812641Sgiacomo.travaglini@arm.combool 104912641Sgiacomo.travaglini@arm.comTarmacParserRecord::readMemNoEffect(Addr addr, uint8_t *data, unsigned size, 105012641Sgiacomo.travaglini@arm.com unsigned flags) 105112641Sgiacomo.travaglini@arm.com{ 105212749Sgiacomo.travaglini@arm.com const RequestPtr &req = memReq; 105312641Sgiacomo.travaglini@arm.com TheISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr()); 105412641Sgiacomo.travaglini@arm.com 105512641Sgiacomo.travaglini@arm.com req->setVirt(0, addr, size, flags, thread->pcState().instAddr(), 105612641Sgiacomo.travaglini@arm.com Request::funcMasterId); 105712641Sgiacomo.travaglini@arm.com 105812641Sgiacomo.travaglini@arm.com // Translate to physical address 105912641Sgiacomo.travaglini@arm.com Fault fault = dtb->translateAtomic(req, thread, BaseTLB::Read); 106012641Sgiacomo.travaglini@arm.com 106112641Sgiacomo.travaglini@arm.com // Ignore read if the address falls into the ignored range 106212641Sgiacomo.travaglini@arm.com if (parent.ignoredAddrRange.contains(addr)) 106312641Sgiacomo.travaglini@arm.com return false; 106412641Sgiacomo.travaglini@arm.com 106512641Sgiacomo.travaglini@arm.com // Now do the access 106612641Sgiacomo.travaglini@arm.com if (fault == NoFault && 106712641Sgiacomo.travaglini@arm.com !req->getFlags().isSet(Request::NO_ACCESS)) { 106812641Sgiacomo.travaglini@arm.com if (req->isLLSC() || req->isMmappedIpr()) 106912641Sgiacomo.travaglini@arm.com // LLSCs and mem. mapped IPRs are ignored 107012641Sgiacomo.travaglini@arm.com return false; 107112641Sgiacomo.travaglini@arm.com // the translating proxy will perform the virtual to physical 107212641Sgiacomo.travaglini@arm.com // translation again 107312641Sgiacomo.travaglini@arm.com thread->getVirtProxy().readBlob(addr, data, size); 107412641Sgiacomo.travaglini@arm.com } else { 107512641Sgiacomo.travaglini@arm.com return false; 107612641Sgiacomo.travaglini@arm.com } 107712641Sgiacomo.travaglini@arm.com 107812641Sgiacomo.travaglini@arm.com if (fault != NoFault) { 107912641Sgiacomo.travaglini@arm.com return false; 108012641Sgiacomo.travaglini@arm.com } 108112641Sgiacomo.travaglini@arm.com 108212641Sgiacomo.travaglini@arm.com return true; 108312641Sgiacomo.travaglini@arm.com} 108412641Sgiacomo.travaglini@arm.com 108512641Sgiacomo.travaglini@arm.comvoid 108612641Sgiacomo.travaglini@arm.comTarmacParser::advanceTraceToStartPc() 108712641Sgiacomo.travaglini@arm.com{ 108812641Sgiacomo.travaglini@arm.com char buf[TarmacParserRecord::MaxLineLength]; 108912641Sgiacomo.travaglini@arm.com Addr pc; 109012641Sgiacomo.travaglini@arm.com int saved_offset; 109112641Sgiacomo.travaglini@arm.com 109212641Sgiacomo.travaglini@arm.com trace >> hex; // All integer values are in hex base 109312641Sgiacomo.travaglini@arm.com 109412641Sgiacomo.travaglini@arm.com while (true) { 109512641Sgiacomo.travaglini@arm.com saved_offset = trace.tellg(); 109612641Sgiacomo.travaglini@arm.com trace >> buf >> buf >> buf; 109712641Sgiacomo.travaglini@arm.com if (cpuId) 109812641Sgiacomo.travaglini@arm.com trace >> buf; 109912641Sgiacomo.travaglini@arm.com if (buf[0] == 'I') { 110012641Sgiacomo.travaglini@arm.com trace >> buf >> pc; 110112641Sgiacomo.travaglini@arm.com if (pc == startPc) { 110212641Sgiacomo.travaglini@arm.com // Set file pointer to the beginning of this line 110312641Sgiacomo.travaglini@arm.com trace.seekg(saved_offset, ios::beg); 110412641Sgiacomo.travaglini@arm.com return; 110512641Sgiacomo.travaglini@arm.com } else { 110612641Sgiacomo.travaglini@arm.com trace.ignore(TarmacParserRecord::MaxLineLength, '\n'); 110712641Sgiacomo.travaglini@arm.com } 110812641Sgiacomo.travaglini@arm.com } else { 110912641Sgiacomo.travaglini@arm.com trace.ignore(TarmacParserRecord::MaxLineLength, '\n'); 111012641Sgiacomo.travaglini@arm.com } 111112641Sgiacomo.travaglini@arm.com if (trace.eof()) 111212641Sgiacomo.travaglini@arm.com panic("End of TARMAC trace reached before start PC\n"); 111312641Sgiacomo.travaglini@arm.com } 111412641Sgiacomo.travaglini@arm.com} 111512641Sgiacomo.travaglini@arm.com 111612641Sgiacomo.travaglini@arm.comconst char* 111712641Sgiacomo.travaglini@arm.comTarmacParserRecord::iSetStateToStr(ISetState isetstate) const 111812641Sgiacomo.travaglini@arm.com{ 111912641Sgiacomo.travaglini@arm.com switch (isetstate) { 112012641Sgiacomo.travaglini@arm.com case ISET_ARM: 112112641Sgiacomo.travaglini@arm.com return "ARM (A32)"; 112212641Sgiacomo.travaglini@arm.com case ISET_THUMB: 112312641Sgiacomo.travaglini@arm.com return "Thumb (A32)"; 112412641Sgiacomo.travaglini@arm.com case ISET_A64: 112512641Sgiacomo.travaglini@arm.com return "A64"; 112612641Sgiacomo.travaglini@arm.com default: 112712641Sgiacomo.travaglini@arm.com return "UNSUPPORTED"; 112812641Sgiacomo.travaglini@arm.com } 112912641Sgiacomo.travaglini@arm.com} 113012641Sgiacomo.travaglini@arm.com 113112641Sgiacomo.travaglini@arm.com} // namespace Trace 113212641Sgiacomo.travaglini@arm.com 113312641Sgiacomo.travaglini@arm.comTrace::TarmacParser * 113412641Sgiacomo.travaglini@arm.comTarmacParserParams::create() 113512641Sgiacomo.travaglini@arm.com{ 113612641Sgiacomo.travaglini@arm.com return new Trace::TarmacParser(this); 113712641Sgiacomo.travaglini@arm.com} 1138