tlb.hh revision 9294 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46#include <map>
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/utility.hh"
51#include "arch/arm/vtophys.hh"
52#include "base/statistics.hh"
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/fault_fwd.hh"
56#include "sim/tlb.hh"
57
58class ThreadContext;
59
60namespace ArmISA {
61
62class TableWalker;
63
64class TLB : public BaseTLB
65{
66  public:
67    enum ArmFlags {
68        AlignmentMask = 0x1f,
69
70        AlignByte = 0x0,
71        AlignHalfWord = 0x1,
72        AlignWord = 0x3,
73        AlignDoubleWord = 0x7,
74        AlignQuadWord = 0xf,
75        AlignOctWord = 0x1f,
76
77        AllowUnaligned = 0x20,
78        // Priv code operating as if it wasn't
79        UserMode = 0x40,
80        // Because zero otherwise looks like a valid setting and may be used
81        // accidentally, this bit must be non-zero to show it was used on
82        // purpose.
83        MustBeOne = 0x80
84    };
85  protected:
86
87    TlbEntry *table;    // the Page Table
88    int size;           // TLB Size
89
90    uint32_t _attr;     // Memory attributes for last accessed TLB entry
91
92    TableWalker *tableWalker;
93
94    /** Lookup an entry in the TLB
95     * @param vpn virtual address
96     * @param asn context id/address space id to use
97     * @param functional if the lookup should modify state
98     * @return pointer to TLB entrry if it exists
99     */
100    TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
101
102    // Access Stats
103    mutable Stats::Scalar instHits;
104    mutable Stats::Scalar instMisses;
105    mutable Stats::Scalar readHits;
106    mutable Stats::Scalar readMisses;
107    mutable Stats::Scalar writeHits;
108    mutable Stats::Scalar writeMisses;
109    mutable Stats::Scalar inserts;
110    mutable Stats::Scalar flushTlb;
111    mutable Stats::Scalar flushTlbMva;
112    mutable Stats::Scalar flushTlbMvaAsid;
113    mutable Stats::Scalar flushTlbAsid;
114    mutable Stats::Scalar flushedEntries;
115    mutable Stats::Scalar alignFaults;
116    mutable Stats::Scalar prefetchFaults;
117    mutable Stats::Scalar domainFaults;
118    mutable Stats::Scalar permsFaults;
119
120    Stats::Formula readAccesses;
121    Stats::Formula writeAccesses;
122    Stats::Formula instAccesses;
123    Stats::Formula hits;
124    Stats::Formula misses;
125    Stats::Formula accesses;
126
127    int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
128
129    bool bootUncacheability;
130
131  public:
132    typedef ArmTLBParams Params;
133    TLB(const Params *p);
134
135    virtual ~TLB();
136    int getsize() const { return size; }
137
138    void insert(Addr vaddr, TlbEntry &pte);
139
140    /** Reset the entire TLB */
141    void flushAll();
142
143    /** Remove any entries that match both a va and asn
144     * @param mva virtual address to flush
145     * @param asn contextid/asn to flush on match
146     */
147    void flushMvaAsid(Addr mva, uint64_t asn);
148
149    /** Remove any entries that match the asn
150     * @param asn contextid/asn to flush on match
151     */
152    void flushAsid(uint64_t asn);
153
154    /** Remove all entries that match the va regardless of asn
155     * @param mva address to flush from cache
156     */
157    void flushMva(Addr mva);
158
159    Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
160    Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
161            bool is_write, uint8_t domain, bool sNp);
162
163    void printTlb();
164
165    void allCpusCaching() { bootUncacheability = true; }
166    void demapPage(Addr vaddr, uint64_t asn)
167    {
168        flushMvaAsid(vaddr, asn);
169    }
170
171    static bool validVirtualAddress(Addr vaddr);
172
173    /**
174     * Do a functional lookup on the TLB (for debugging)
175     * and don't modify any internal state
176     * @param tc thread context to get the context id from
177     * @param vaddr virtual address to translate
178     * @param pa returned physical address
179     * @return if the translation was successful
180     */
181    bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
182
183    /**
184     * Do a functional lookup on the TLB (for checker cpu) that
185     * behaves like a normal lookup without modifying any page table state.
186     */
187    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
188
189    /** Accessor functions for memory attributes for last accessed TLB entry
190     */
191    void
192    setAttr(uint32_t attr)
193    {
194        _attr = attr;
195    }
196    uint32_t
197    getAttr() const
198    {
199        return _attr;
200    }
201
202    Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
203            Translation *translation, bool &delay,
204            bool timing, bool functional = false);
205    Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
206            Translation *translation, bool &delay, bool timing);
207    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
208    Fault translateTiming(RequestPtr req, ThreadContext *tc,
209            Translation *translation, Mode mode);
210
211    // Checkpointing
212    void serialize(std::ostream &os);
213    void unserialize(Checkpoint *cp, const std::string &section);
214
215    void regStats();
216
217    /**
218     * Get the table walker master port. This is used for migrating
219     * port connections during a CPU takeOverFrom() call. For
220     * architectures that do not have a table walker, NULL is
221     * returned, hence the use of a pointer rather than a
222     * reference. For ARM this method will always return a valid port
223     * pointer.
224     *
225     * @return A pointer to the walker master port
226     */
227    virtual BaseMasterPort* getMasterPort();
228
229    // Caching misc register values here.
230    // Writing to misc registers needs to invalidate them.
231    // translateFunctional/translateSe/translateFs checks if they are
232    // invalid and call updateMiscReg if necessary.
233protected:
234    SCTLR sctlr;
235    bool isPriv;
236    CONTEXTIDR contextId;
237    PRRR prrr;
238    NMRR nmrr;
239    uint32_t dacr;
240    bool miscRegValid;
241    void updateMiscReg(ThreadContext *tc)
242    {
243        sctlr = tc->readMiscReg(MISCREG_SCTLR);
244        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
245        isPriv = cpsr.mode != MODE_USER;
246        contextId = tc->readMiscReg(MISCREG_CONTEXTIDR);
247        prrr = tc->readMiscReg(MISCREG_PRRR);
248        nmrr = tc->readMiscReg(MISCREG_NMRR);
249        dacr = tc->readMiscReg(MISCREG_DACR);
250        miscRegValid = true;
251    }
252public:
253    const Params *
254    params() const
255    {
256        return dynamic_cast<const Params *>(_params);
257    }
258    inline void invalidateMiscReg() { miscRegValid = false; }
259};
260
261} // namespace ArmISA
262
263#endif // __ARCH_ARM_TLB_HH__
264