tlb.hh revision 8733 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46#include <map>
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/utility.hh"
51#include "arch/arm/vtophys.hh"
52#include "base/statistics.hh"
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/fault_fwd.hh"
56#include "sim/tlb.hh"
57
58class ThreadContext;
59
60namespace ArmISA {
61
62class TableWalker;
63
64class TLB : public BaseTLB
65{
66  public:
67    enum ArmFlags {
68        AlignmentMask = 0x1f,
69
70        AlignByte = 0x0,
71        AlignHalfWord = 0x1,
72        AlignWord = 0x3,
73        AlignDoubleWord = 0x7,
74        AlignQuadWord = 0xf,
75        AlignOctWord = 0x1f,
76
77        AllowUnaligned = 0x20,
78        // Priv code operating as if it wasn't
79        UserMode = 0x40,
80        // Because zero otherwise looks like a valid setting and may be used
81        // accidentally, this bit must be non-zero to show it was used on
82        // purpose.
83        MustBeOne = 0x80
84    };
85  protected:
86
87    TlbEntry *table;    // the Page Table
88    int size;           // TLB Size
89
90    uint32_t _attr;     // Memory attributes for last accessed TLB entry
91
92#if FULL_SYSTEM
93    TableWalker *tableWalker;
94#endif
95
96    /** Lookup an entry in the TLB
97     * @param vpn virtual address
98     * @param asn context id/address space id to use
99     * @param functional if the lookup should modify state
100     * @return pointer to TLB entrry if it exists
101     */
102    TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
103
104    // Access Stats
105    mutable Stats::Scalar instHits;
106    mutable Stats::Scalar instMisses;
107    mutable Stats::Scalar readHits;
108    mutable Stats::Scalar readMisses;
109    mutable Stats::Scalar writeHits;
110    mutable Stats::Scalar writeMisses;
111    mutable Stats::Scalar inserts;
112    mutable Stats::Scalar flushTlb;
113    mutable Stats::Scalar flushTlbMva;
114    mutable Stats::Scalar flushTlbMvaAsid;
115    mutable Stats::Scalar flushTlbAsid;
116    mutable Stats::Scalar flushedEntries;
117    mutable Stats::Scalar alignFaults;
118    mutable Stats::Scalar prefetchFaults;
119    mutable Stats::Scalar domainFaults;
120    mutable Stats::Scalar permsFaults;
121
122    Stats::Formula readAccesses;
123    Stats::Formula writeAccesses;
124    Stats::Formula instAccesses;
125    Stats::Formula hits;
126    Stats::Formula misses;
127    Stats::Formula accesses;
128
129    int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
130
131    bool bootUncacheability;
132
133  public:
134    typedef ArmTLBParams Params;
135    TLB(const Params *p);
136
137    virtual ~TLB();
138    int getsize() const { return size; }
139
140    void insert(Addr vaddr, TlbEntry &pte);
141
142    /** Reset the entire TLB */
143    void flushAll();
144
145    /** Remove any entries that match both a va and asn
146     * @param mva virtual address to flush
147     * @param asn contextid/asn to flush on match
148     */
149    void flushMvaAsid(Addr mva, uint64_t asn);
150
151    /** Remove any entries that match the asn
152     * @param asn contextid/asn to flush on match
153     */
154    void flushAsid(uint64_t asn);
155
156    /** Remove all entries that match the va regardless of asn
157     * @param mva address to flush from cache
158     */
159    void flushMva(Addr mva);
160
161    Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
162    Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
163            bool is_write, uint8_t domain, bool sNp);
164
165    void printTlb();
166
167    void allCpusCaching() { bootUncacheability = true; }
168    void demapPage(Addr vaddr, uint64_t asn)
169    {
170        flushMvaAsid(vaddr, asn);
171    }
172
173    static bool validVirtualAddress(Addr vaddr);
174
175    /**
176     * Do a functional lookup on the TLB (for debugging)
177     * and don't modify any internal state
178     * @param tc thread context to get the context id from
179     * @param vaddr virtual address to translate
180     * @param pa returned physical address
181     * @return if the translation was successful
182     */
183    bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
184
185    /**
186     * Do a functional lookup on the TLB (for checker cpu) that
187     * behaves like a normal lookup without modifying any page table state.
188     */
189    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
190
191    /** Accessor functions for memory attributes for last accessed TLB entry
192     */
193    void
194    setAttr(uint32_t attr)
195    {
196        _attr = attr;
197    }
198    uint32_t
199    getAttr() const
200    {
201        return _attr;
202    }
203
204#if FULL_SYSTEM
205    Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
206            Translation *translation, bool &delay,
207            bool timing, bool functional = false);
208#else
209    Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
210            Translation *translation, bool &delay, bool timing);
211#endif
212    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
213    Fault translateTiming(RequestPtr req, ThreadContext *tc,
214            Translation *translation, Mode mode);
215
216    // Checkpointing
217    void serialize(std::ostream &os);
218    void unserialize(Checkpoint *cp, const std::string &section);
219
220    void regStats();
221
222    // Get the port from the table walker and return it
223    virtual Port *getPort();
224
225    // Caching misc register values here.
226    // Writing to misc registers needs to invalidate them.
227    // translateFunctional/translateSe/translateFs checks if they are
228    // invalid and call updateMiscReg if necessary.
229protected:
230    SCTLR sctlr;
231    bool isPriv;
232    CONTEXTIDR contextId;
233    PRRR prrr;
234    NMRR nmrr;
235    uint32_t dacr;
236    bool miscRegValid;
237    void updateMiscReg(ThreadContext *tc)
238    {
239        sctlr = tc->readMiscReg(MISCREG_SCTLR);
240        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
241        isPriv = cpsr.mode != MODE_USER;
242        contextId = tc->readMiscReg(MISCREG_CONTEXTIDR);
243        prrr = tc->readMiscReg(MISCREG_PRRR);
244        nmrr = tc->readMiscReg(MISCREG_NMRR);
245        dacr = tc->readMiscReg(MISCREG_DACR);
246        miscRegValid = true;
247    }
248public:
249    const Params *
250    params() const
251    {
252        return dynamic_cast<const Params *>(_params);
253    }
254    inline void invalidateMiscReg() { miscRegValid = false; }
255};
256
257} // namespace ArmISA
258
259#endif // __ARCH_ARM_TLB_HH__
260