tlb.hh revision 7406 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46#include <map>
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/utility.hh"
50#include "arch/arm/vtophys.hh"
51#include "arch/arm/pagetable.hh"
52#include "base/statistics.hh"
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/faults.hh"
56#include "sim/tlb.hh"
57
58class ThreadContext;
59
60namespace ArmISA {
61
62class TableWalker;
63
64class TLB : public BaseTLB
65{
66  public:
67    enum ArmFlags {
68        AlignmentMask = 0x7,
69
70        AlignByte = 0x0,
71        AlignHalfWord = 0x1,
72        AlignWord = 0x3,
73        AlignDoubleWord = 0x7,
74
75        AllowUnaligned = 0x8,
76        // Priv code operating as if it wasn't
77        UserMode = 0x10,
78        // Because zero otherwise looks like a valid setting and may be used
79        // accidentally, this bit must be non-zero to show it was used on
80        // purpose.
81        MustBeOne = 0x20
82    };
83  protected:
84    typedef std::multimap<Addr, int> PageTable;
85    PageTable lookupTable;	// Quick lookup into page table
86
87    TlbEntry *table;	// the Page Table
88    int size;			// TLB Size
89    int nlu;			// not last used entry (for replacement)
90
91#if FULL_SYSTEM
92    TableWalker *tableWalker;
93#endif
94
95    void nextnlu() { if (++nlu >= size) nlu = 0; }
96    TlbEntry *lookup(Addr vpn, uint8_t asn);
97
98    // Access Stats
99    mutable Stats::Scalar read_hits;
100    mutable Stats::Scalar read_misses;
101    mutable Stats::Scalar read_acv;
102    mutable Stats::Scalar read_accesses;
103    mutable Stats::Scalar write_hits;
104    mutable Stats::Scalar write_misses;
105    mutable Stats::Scalar write_acv;
106    mutable Stats::Scalar write_accesses;
107    Stats::Formula hits;
108    Stats::Formula misses;
109    Stats::Formula invalids;
110    Stats::Formula accesses;
111
112
113  public:
114    typedef ArmTLBParams Params;
115    TLB(const Params *p);
116
117    virtual ~TLB();
118    int getsize() const { return size; }
119
120    void insert(Addr vaddr, TlbEntry &pte);
121
122    /** Reset the entire TLB */
123    void flushAll();
124
125    /** Remove any entries that match both a va and asn
126     * @param mva virtual address to flush
127     * @param asn contextid/asn to flush on match
128     */
129    void flushMvaAsid(Addr mva, uint64_t asn);
130
131    /** Remove any entries that match the asn
132     * @param asn contextid/asn to flush on match
133     */
134    void flushAsid(uint64_t asn);
135
136    /** Remove all entries that match the va regardless of asn
137     * @param mva address to flush from cache
138     */
139    void flushMva(Addr mva);
140
141    Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
142    Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
143            bool is_write, uint8_t domain, bool sNp);
144
145    void printTlb();
146
147    void demapPage(Addr vaddr, uint64_t asn)
148    {
149        flushMvaAsid(vaddr, asn);
150    }
151
152    static bool validVirtualAddress(Addr vaddr);
153
154#if FULL_SYSTEM
155    Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
156            Translation *translation, bool &delay, bool timing);
157#else
158    Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
159            Translation *translation, bool &delay, bool timing);
160#endif
161    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
162    Fault translateTiming(RequestPtr req, ThreadContext *tc,
163            Translation *translation, Mode mode);
164
165    // Checkpointing
166    void serialize(std::ostream &os);
167    void unserialize(Checkpoint *cp, const std::string &section);
168
169    void regStats();
170};
171
172/* namespace ArmISA */ }
173
174#endif // __ARCH_ARM_TLB_HH__
175