tlb.hh revision 7399 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46#include <map>
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/utility.hh"
50#include "arch/arm/vtophys.hh"
51#include "arch/arm/pagetable.hh"
52#include "base/statistics.hh"
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/faults.hh"
56#include "sim/tlb.hh"
57
58class ThreadContext;
59
60namespace ArmISA {
61
62class TLB : public BaseTLB
63{
64  public:
65    enum ArmFlags {
66        AlignmentMask = 0x7,
67
68        AlignByte = 0x0,
69        AlignHalfWord = 0x1,
70        AlignWord = 0x3,
71        AlignDoubleWord = 0x7,
72
73        AllowUnaligned = 0x8,
74        // Because zero otherwise looks like a valid setting and may be used
75        // accidentally, this bit must be non-zero to show it was used on
76        // purpose.
77        MustBeOne = 0x10
78    };
79  protected:
80    typedef std::multimap<Addr, int> PageTable;
81    PageTable lookupTable;	// Quick lookup into page table
82
83    ArmISA::PTE *table;	// the Page Table
84    int size;			// TLB Size
85    int nlu;			// not last used entry (for replacement)
86
87    void nextnlu() { if (++nlu >= size) nlu = 0; }
88    ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const;
89
90    // Access Stats
91    mutable Stats::Scalar read_hits;
92    mutable Stats::Scalar read_misses;
93    mutable Stats::Scalar read_acv;
94    mutable Stats::Scalar read_accesses;
95    mutable Stats::Scalar write_hits;
96    mutable Stats::Scalar write_misses;
97    mutable Stats::Scalar write_acv;
98    mutable Stats::Scalar write_accesses;
99    Stats::Formula hits;
100    Stats::Formula misses;
101    Stats::Formula invalids;
102    Stats::Formula accesses;
103
104  public:
105    typedef ArmTLBParams Params;
106    TLB(const Params *p);
107
108    virtual ~TLB();
109    int getsize() const { return size; }
110
111    void insert(Addr vaddr, ArmISA::PTE &pte);
112    void flushAll();
113    void demapPage(Addr vaddr, uint64_t asn)
114    {
115        panic("demapPage unimplemented.\n");
116    }
117
118    static bool validVirtualAddress(Addr vaddr);
119
120    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
121    void translateTiming(RequestPtr req, ThreadContext *tc,
122            Translation *translation, Mode mode);
123
124    // Checkpointing
125    void serialize(std::ostream &os);
126    void unserialize(Checkpoint *cp, const std::string &section);
127
128    void regStats();
129};
130
131/* namespace ArmISA */ }
132
133#endif // __ARCH_ARM_TLB_HH__
134