tlb.hh revision 12005 
1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/pagetable.hh"
49#include "arch/arm/utility.hh"
50#include "arch/arm/vtophys.hh"
51#include "arch/generic/tlb.hh"
52#include "base/statistics.hh"
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/probe/pmu.hh"
56
57class ThreadContext;
58
59namespace ArmISA {
60
61class TableWalker;
62class Stage2LookUp;
63class Stage2MMU;
64class TLB;
65
66class TlbTestInterface
67{
68  public:
69    TlbTestInterface() {}
70    virtual ~TlbTestInterface() {}
71
72    /**
73     * Check if a TLB translation should be forced to fail.
74     *
75     * @param req Request requiring a translation.
76     * @param is_priv Access from a privileged mode (i.e., not EL0)
77     * @param mode Access type
78     * @param domain Domain type
79     */
80    virtual Fault translationCheck(RequestPtr req, bool is_priv,
81                                   BaseTLB::Mode mode,
82                                   TlbEntry::DomainType domain) = 0;
83
84    /**
85     * Check if a page table walker access should be forced to fail.
86     *
87     * @param pa Physical address the walker is accessing
88     * @param size Walker access size
89     * @param va Virtual address that initiated the walk
90     * @param is_secure Access from secure state
91     * @param is_priv Access from a privileged mode (i.e., not EL0)
92     * @param mode Access type
93     * @param domain Domain type
94     * @param lookup_level Page table walker level
95     */
96    virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure,
97                            Addr is_priv, BaseTLB::Mode mode,
98                            TlbEntry::DomainType domain,
99                            LookupLevel lookup_level) = 0;
100};
101
102class TLB : public BaseTLB
103{
104  public:
105    enum ArmFlags {
106        AlignmentMask = 0x7,
107
108        AlignByte = 0x0,
109        AlignHalfWord = 0x1,
110        AlignWord = 0x2,
111        AlignDoubleWord = 0x3,
112        AlignQuadWord = 0x4,
113        AlignOctWord = 0x5,
114
115        AllowUnaligned = 0x8,
116        // Priv code operating as if it wasn't
117        UserMode = 0x10,
118        // Because zero otherwise looks like a valid setting and may be used
119        // accidentally, this bit must be non-zero to show it was used on
120        // purpose.
121        MustBeOne = 0x40
122    };
123
124    enum ArmTranslationType {
125        NormalTran = 0,
126        S1CTran = 0x1,
127        HypMode = 0x2,
128        // Secure code operating as if it wasn't (required by some Address
129        // Translate operations)
130        S1S2NsTran = 0x4,
131        // Address translation instructions (eg AT S1E0R_Xt) need to be handled
132        // in special ways during translation because they could need to act
133        // like a different EL than the current EL. The following flags are
134        // for these instructions
135        S1E0Tran = 0x8,
136        S1E1Tran = 0x10,
137        S1E2Tran = 0x20,
138        S1E3Tran = 0x40,
139        S12E0Tran = 0x80,
140        S12E1Tran = 0x100
141    };
142  protected:
143    TlbEntry* table;     // the Page Table
144    int size;            // TLB Size
145    bool isStage2;       // Indicates this TLB is part of the second stage MMU
146    bool stage2Req;      // Indicates whether a stage 2 lookup is also required
147    uint64_t _attr;      // Memory attributes for last accessed TLB entry
148    bool directToStage2; // Indicates whether all translation requests should
149                         // be routed directly to the stage 2 TLB
150
151    TableWalker *tableWalker;
152    TLB *stage2Tlb;
153    Stage2MMU *stage2Mmu;
154
155    TlbTestInterface *test;
156
157    // Access Stats
158    mutable Stats::Scalar instHits;
159    mutable Stats::Scalar instMisses;
160    mutable Stats::Scalar readHits;
161    mutable Stats::Scalar readMisses;
162    mutable Stats::Scalar writeHits;
163    mutable Stats::Scalar writeMisses;
164    mutable Stats::Scalar inserts;
165    mutable Stats::Scalar flushTlb;
166    mutable Stats::Scalar flushTlbMva;
167    mutable Stats::Scalar flushTlbMvaAsid;
168    mutable Stats::Scalar flushTlbAsid;
169    mutable Stats::Scalar flushedEntries;
170    mutable Stats::Scalar alignFaults;
171    mutable Stats::Scalar prefetchFaults;
172    mutable Stats::Scalar domainFaults;
173    mutable Stats::Scalar permsFaults;
174
175    Stats::Formula readAccesses;
176    Stats::Formula writeAccesses;
177    Stats::Formula instAccesses;
178    Stats::Formula hits;
179    Stats::Formula misses;
180    Stats::Formula accesses;
181
182    /** PMU probe for TLB refills */
183    ProbePoints::PMUUPtr ppRefills;
184
185    int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
186
187  public:
188    TLB(const ArmTLBParams *p);
189    TLB(const Params *p, int _size, TableWalker *_walker);
190
191    /** Lookup an entry in the TLB
192     * @param vpn virtual address
193     * @param asn context id/address space id to use
194     * @param vmid The virtual machine ID used for stage 2 translation
195     * @param secure if the lookup is secure
196     * @param hyp if the lookup is done from hyp mode
197     * @param functional if the lookup should modify state
198     * @param ignore_asn if on lookup asn should be ignored
199     * @return pointer to TLB entry if it exists
200     */
201    TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
202                     bool secure, bool functional,
203                     bool ignore_asn, uint8_t target_el);
204
205    virtual ~TLB();
206
207    void takeOverFrom(BaseTLB *otlb) override;
208
209    /// setup all the back pointers
210    void init() override;
211
212    void setTestInterface(SimObject *ti);
213
214    TableWalker *getTableWalker() { return tableWalker; }
215
216    void setMMU(Stage2MMU *m, MasterID master_id);
217
218    int getsize() const { return size; }
219
220    void insert(Addr vaddr, TlbEntry &pte);
221
222    Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
223                Translation *translation, bool timing, bool functional,
224                bool is_secure, ArmTranslationType tranType);
225
226    Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
227                      Mode mode, Translation *translation, bool timing,
228                      bool functional, TlbEntry *mergeTe);
229
230    Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
231    Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
232                             ThreadContext *tc);
233
234
235    /** Reset the entire TLB
236     * @param secure_lookup if the operation affects the secure world
237     */
238    void flushAllSecurity(bool secure_lookup, uint8_t target_el,
239                          bool ignore_el = false);
240
241    /** Remove all entries in the non secure world, depending on whether they
242     *  were allocated in hyp mode or not
243     * @param hyp if the opperation affects hyp mode
244     */
245    void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
246
247
248    /** Reset the entire TLB. Used for CPU switching to prevent stale
249     * translations after multiple switches
250     */
251    void flushAll() override
252    {
253        flushAllSecurity(false, 0, true);
254        flushAllSecurity(true, 0, true);
255    }
256
257    /** Remove any entries that match both a va and asn
258     * @param mva virtual address to flush
259     * @param asn contextid/asn to flush on match
260     * @param secure_lookup if the operation affects the secure world
261     */
262    void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
263                      uint8_t target_el);
264
265    /** Remove any entries that match the asn
266     * @param asn contextid/asn to flush on match
267     * @param secure_lookup if the operation affects the secure world
268     */
269    void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
270
271    /** Remove all entries that match the va regardless of asn
272     * @param mva address to flush from cache
273     * @param secure_lookup if the operation affects the secure world
274     * @param hyp if the operation affects hyp mode
275     */
276    void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
277
278    /**
279     * Invalidate all entries in the stage 2 TLB that match the given ipa
280     * and the current VMID
281     * @param ipa the address to invalidate
282     * @param secure_lookup if the operation affects the secure world
283     * @param hyp if the operation affects hyp mode
284     */
285    void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el);
286
287    Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
288    Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
289            bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
290
291    void printTlb() const;
292
293    void demapPage(Addr vaddr, uint64_t asn) override
294    {
295        // needed for x86 only
296        panic("demapPage() is not implemented.\n");
297    }
298
299    /**
300     * Do a functional lookup on the TLB (for debugging)
301     * and don't modify any internal state
302     * @param tc thread context to get the context id from
303     * @param vaddr virtual address to translate
304     * @param pa returned physical address
305     * @return if the translation was successful
306     */
307    bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
308
309    /**
310     * Do a functional lookup on the TLB (for checker cpu) that
311     * behaves like a normal lookup without modifying any page table state.
312     */
313    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
314            ArmTranslationType tranType = NormalTran);
315
316    /** Accessor functions for memory attributes for last accessed TLB entry
317     */
318    void
319    setAttr(uint64_t attr)
320    {
321        _attr = attr;
322    }
323
324    uint64_t
325    getAttr() const
326    {
327        return _attr;
328    }
329
330    Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
331            Translation *translation, bool &delay,
332            bool timing, ArmTranslationType tranType, bool functional = false);
333    Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
334            Translation *translation, bool &delay, bool timing);
335    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
336            ArmTranslationType tranType = NormalTran);
337    Fault translateTiming(RequestPtr req, ThreadContext *tc,
338            Translation *translation, Mode mode,
339            ArmTranslationType tranType = NormalTran);
340    Fault translateComplete(RequestPtr req, ThreadContext *tc,
341            Translation *translation, Mode mode, ArmTranslationType tranType,
342            bool callFromS2);
343    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
344
345    void drainResume() override;
346
347    // Checkpointing
348    void serialize(CheckpointOut &cp) const override;
349    void unserialize(CheckpointIn &cp) override;
350
351    void regStats() override;
352
353    void regProbePoints() override;
354
355    /**
356     * Get the table walker master port. This is used for migrating
357     * port connections during a CPU takeOverFrom() call. For
358     * architectures that do not have a table walker, NULL is
359     * returned, hence the use of a pointer rather than a
360     * reference. For ARM this method will always return a valid port
361     * pointer.
362     *
363     * @return A pointer to the walker master port
364     */
365    BaseMasterPort* getMasterPort() override;
366
367    // Caching misc register values here.
368    // Writing to misc registers needs to invalidate them.
369    // translateFunctional/translateSe/translateFs checks if they are
370    // invalid and call updateMiscReg if necessary.
371protected:
372    CPSR cpsr;
373    bool aarch64;
374    ExceptionLevel aarch64EL;
375    SCTLR sctlr;
376    SCR scr;
377    bool isPriv;
378    bool isSecure;
379    bool isHyp;
380    TTBCR ttbcr;
381    uint16_t asid;
382    uint8_t vmid;
383    PRRR prrr;
384    NMRR nmrr;
385    HCR hcr;
386    uint32_t dacr;
387    bool miscRegValid;
388    ContextID miscRegContext;
389    ArmTranslationType curTranType;
390
391    // Cached copies of system-level properties
392    bool haveLPAE;
393    bool haveVirtualization;
394    bool haveLargeAsid64;
395
396    AddrRange m5opRange;
397
398    void updateMiscReg(ThreadContext *tc,
399                       ArmTranslationType tranType = NormalTran);
400
401public:
402    const Params *
403    params() const
404    {
405        return dynamic_cast<const Params *>(_params);
406    }
407    inline void invalidateMiscReg() { miscRegValid = false; }
408
409private:
410    /** Remove any entries that match both a va and asn
411     * @param mva virtual address to flush
412     * @param asn contextid/asn to flush on match
413     * @param secure_lookup if the operation affects the secure world
414     * @param hyp if the operation affects hyp mode
415     * @param ignore_asn if the flush should ignore the asn
416     */
417    void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
418                   bool hyp, bool ignore_asn, uint8_t target_el);
419
420    bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
421
422  public: /* Testing */
423    Fault testTranslation(RequestPtr req, Mode mode,
424                          TlbEntry::DomainType domain);
425    Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
426                   TlbEntry::DomainType domain,
427                   LookupLevel lookup_level);
428};
429
430} // namespace ArmISA
431
432#endif // __ARCH_ARM_TLB_HH__
433