tlb.hh revision 11395:032bc62120eb
1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_TLB_HH__ 44#define __ARCH_ARM_TLB_HH__ 45 46 47#include "arch/arm/isa_traits.hh" 48#include "arch/arm/pagetable.hh" 49#include "arch/arm/utility.hh" 50#include "arch/arm/vtophys.hh" 51#include "arch/generic/tlb.hh" 52#include "base/statistics.hh" 53#include "mem/request.hh" 54#include "params/ArmTLB.hh" 55#include "sim/probe/pmu.hh" 56 57class ThreadContext; 58 59namespace ArmISA { 60 61class TableWalker; 62class Stage2LookUp; 63class Stage2MMU; 64class TLB; 65 66class TlbTestInterface 67{ 68 public: 69 TlbTestInterface() {} 70 virtual ~TlbTestInterface() {} 71 72 /** 73 * Check if a TLB translation should be forced to fail. 74 * 75 * @param req Request requiring a translation. 76 * @param is_priv Access from a privileged mode (i.e., not EL0) 77 * @param mode Access type 78 * @param domain Domain type 79 */ 80 virtual Fault translationCheck(RequestPtr req, bool is_priv, 81 BaseTLB::Mode mode, 82 TlbEntry::DomainType domain) = 0; 83 84 /** 85 * Check if a page table walker access should be forced to fail. 86 * 87 * @param pa Physical address the walker is accessing 88 * @param size Walker access size 89 * @param va Virtual address that initiated the walk 90 * @param is_secure Access from secure state 91 * @param is_priv Access from a privileged mode (i.e., not EL0) 92 * @param mode Access type 93 * @param domain Domain type 94 * @param lookup_level Page table walker level 95 */ 96 virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure, 97 Addr is_priv, BaseTLB::Mode mode, 98 TlbEntry::DomainType domain, 99 LookupLevel lookup_level) = 0; 100}; 101 102class TLB : public BaseTLB 103{ 104 public: 105 enum ArmFlags { 106 AlignmentMask = 0x7, 107 108 AlignByte = 0x0, 109 AlignHalfWord = 0x1, 110 AlignWord = 0x2, 111 AlignDoubleWord = 0x3, 112 AlignQuadWord = 0x4, 113 AlignOctWord = 0x5, 114 115 AllowUnaligned = 0x8, 116 // Priv code operating as if it wasn't 117 UserMode = 0x10, 118 // Because zero otherwise looks like a valid setting and may be used 119 // accidentally, this bit must be non-zero to show it was used on 120 // purpose. 121 MustBeOne = 0x40 122 }; 123 124 enum ArmTranslationType { 125 NormalTran = 0, 126 S1CTran = 0x1, 127 HypMode = 0x2, 128 // Secure code operating as if it wasn't (required by some Address 129 // Translate operations) 130 S1S2NsTran = 0x4 131 }; 132 protected: 133 TlbEntry* table; // the Page Table 134 int size; // TLB Size 135 bool isStage2; // Indicates this TLB is part of the second stage MMU 136 bool stage2Req; // Indicates whether a stage 2 lookup is also required 137 uint64_t _attr; // Memory attributes for last accessed TLB entry 138 bool directToStage2; // Indicates whether all translation requests should 139 // be routed directly to the stage 2 TLB 140 141 TableWalker *tableWalker; 142 TLB *stage2Tlb; 143 Stage2MMU *stage2Mmu; 144 145 TlbTestInterface *test; 146 147 // Access Stats 148 mutable Stats::Scalar instHits; 149 mutable Stats::Scalar instMisses; 150 mutable Stats::Scalar readHits; 151 mutable Stats::Scalar readMisses; 152 mutable Stats::Scalar writeHits; 153 mutable Stats::Scalar writeMisses; 154 mutable Stats::Scalar inserts; 155 mutable Stats::Scalar flushTlb; 156 mutable Stats::Scalar flushTlbMva; 157 mutable Stats::Scalar flushTlbMvaAsid; 158 mutable Stats::Scalar flushTlbAsid; 159 mutable Stats::Scalar flushedEntries; 160 mutable Stats::Scalar alignFaults; 161 mutable Stats::Scalar prefetchFaults; 162 mutable Stats::Scalar domainFaults; 163 mutable Stats::Scalar permsFaults; 164 165 Stats::Formula readAccesses; 166 Stats::Formula writeAccesses; 167 Stats::Formula instAccesses; 168 Stats::Formula hits; 169 Stats::Formula misses; 170 Stats::Formula accesses; 171 172 /** PMU probe for TLB refills */ 173 ProbePoints::PMUUPtr ppRefills; 174 175 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 176 177 public: 178 TLB(const ArmTLBParams *p); 179 TLB(const Params *p, int _size, TableWalker *_walker); 180 181 /** Lookup an entry in the TLB 182 * @param vpn virtual address 183 * @param asn context id/address space id to use 184 * @param vmid The virtual machine ID used for stage 2 translation 185 * @param secure if the lookup is secure 186 * @param hyp if the lookup is done from hyp mode 187 * @param functional if the lookup should modify state 188 * @param ignore_asn if on lookup asn should be ignored 189 * @return pointer to TLB entry if it exists 190 */ 191 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 192 bool secure, bool functional, 193 bool ignore_asn, uint8_t target_el); 194 195 virtual ~TLB(); 196 197 void takeOverFrom(BaseTLB *otlb) override; 198 199 /// setup all the back pointers 200 void init() override; 201 202 void setTestInterface(SimObject *ti); 203 204 TableWalker *getTableWalker() { return tableWalker; } 205 206 void setMMU(Stage2MMU *m, MasterID master_id); 207 208 int getsize() const { return size; } 209 210 void insert(Addr vaddr, TlbEntry &pte); 211 212 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 213 Translation *translation, bool timing, bool functional, 214 bool is_secure, ArmTranslationType tranType); 215 216 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, 217 Mode mode, Translation *translation, bool timing, 218 bool functional, TlbEntry *mergeTe); 219 220 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode); 221 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 222 ThreadContext *tc); 223 224 225 /** Reset the entire TLB 226 * @param secure_lookup if the operation affects the secure world 227 */ 228 void flushAllSecurity(bool secure_lookup, uint8_t target_el, 229 bool ignore_el = false); 230 231 /** Remove all entries in the non secure world, depending on whether they 232 * were allocated in hyp mode or not 233 * @param hyp if the opperation affects hyp mode 234 */ 235 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false); 236 237 238 /** Reset the entire TLB. Used for CPU switching to prevent stale 239 * translations after multiple switches 240 */ 241 void flushAll() override 242 { 243 flushAllSecurity(false, 0, true); 244 flushAllSecurity(true, 0, true); 245 } 246 247 /** Remove any entries that match both a va and asn 248 * @param mva virtual address to flush 249 * @param asn contextid/asn to flush on match 250 * @param secure_lookup if the operation affects the secure world 251 */ 252 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 253 uint8_t target_el); 254 255 /** Remove any entries that match the asn 256 * @param asn contextid/asn to flush on match 257 * @param secure_lookup if the operation affects the secure world 258 */ 259 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el); 260 261 /** Remove all entries that match the va regardless of asn 262 * @param mva address to flush from cache 263 * @param secure_lookup if the operation affects the secure world 264 * @param hyp if the operation affects hyp mode 265 */ 266 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); 267 268 void printTlb() const; 269 270 void demapPage(Addr vaddr, uint64_t asn) override 271 { 272 // needed for x86 only 273 panic("demapPage() is not implemented.\n"); 274 } 275 276 /** 277 * Do a functional lookup on the TLB (for debugging) 278 * and don't modify any internal state 279 * @param tc thread context to get the context id from 280 * @param vaddr virtual address to translate 281 * @param pa returned physical address 282 * @return if the translation was successful 283 */ 284 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 285 286 /** 287 * Do a functional lookup on the TLB (for checker cpu) that 288 * behaves like a normal lookup without modifying any page table state. 289 */ 290 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 291 ArmTranslationType tranType = NormalTran); 292 293 /** Accessor functions for memory attributes for last accessed TLB entry 294 */ 295 void 296 setAttr(uint64_t attr) 297 { 298 _attr = attr; 299 } 300 301 uint64_t 302 getAttr() const 303 { 304 return _attr; 305 } 306 307 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 308 Translation *translation, bool &delay, 309 bool timing, ArmTranslationType tranType, bool functional = false); 310 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 311 Translation *translation, bool &delay, bool timing); 312 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 313 ArmTranslationType tranType = NormalTran); 314 Fault translateTiming(RequestPtr req, ThreadContext *tc, 315 Translation *translation, Mode mode, 316 ArmTranslationType tranType = NormalTran); 317 Fault translateComplete(RequestPtr req, ThreadContext *tc, 318 Translation *translation, Mode mode, ArmTranslationType tranType, 319 bool callFromS2); 320 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 321 322 void drainResume() override; 323 324 // Checkpointing 325 void serialize(CheckpointOut &cp) const override; 326 void unserialize(CheckpointIn &cp) override; 327 328 void regStats() override; 329 330 void regProbePoints() override; 331 332 /** 333 * Get the table walker master port. This is used for migrating 334 * port connections during a CPU takeOverFrom() call. For 335 * architectures that do not have a table walker, NULL is 336 * returned, hence the use of a pointer rather than a 337 * reference. For ARM this method will always return a valid port 338 * pointer. 339 * 340 * @return A pointer to the walker master port 341 */ 342 BaseMasterPort* getMasterPort() override; 343 344 // Caching misc register values here. 345 // Writing to misc registers needs to invalidate them. 346 // translateFunctional/translateSe/translateFs checks if they are 347 // invalid and call updateMiscReg if necessary. 348protected: 349 CPSR cpsr; 350 bool aarch64; 351 ExceptionLevel aarch64EL; 352 SCTLR sctlr; 353 SCR scr; 354 bool isPriv; 355 bool isSecure; 356 bool isHyp; 357 TTBCR ttbcr; 358 uint16_t asid; 359 uint8_t vmid; 360 PRRR prrr; 361 NMRR nmrr; 362 HCR hcr; 363 uint32_t dacr; 364 bool miscRegValid; 365 ContextID miscRegContext; 366 ArmTranslationType curTranType; 367 368 // Cached copies of system-level properties 369 bool haveLPAE; 370 bool haveVirtualization; 371 bool haveLargeAsid64; 372 373 void updateMiscReg(ThreadContext *tc, 374 ArmTranslationType tranType = NormalTran); 375 376public: 377 const Params * 378 params() const 379 { 380 return dynamic_cast<const Params *>(_params); 381 } 382 inline void invalidateMiscReg() { miscRegValid = false; } 383 384private: 385 /** Remove any entries that match both a va and asn 386 * @param mva virtual address to flush 387 * @param asn contextid/asn to flush on match 388 * @param secure_lookup if the operation affects the secure world 389 * @param hyp if the operation affects hyp mode 390 * @param ignore_asn if the flush should ignore the asn 391 */ 392 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 393 bool hyp, bool ignore_asn, uint8_t target_el); 394 395 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); 396 397 public: /* Testing */ 398 Fault testTranslation(RequestPtr req, Mode mode, 399 TlbEntry::DomainType domain); 400 Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, 401 TlbEntry::DomainType domain, 402 LookupLevel lookup_level); 403}; 404 405} // namespace ArmISA 406 407#endif // __ARCH_ARM_TLB_HH__ 408