tlb.hh revision 11347 
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/pagetable.hh"
49#include "arch/arm/utility.hh"
50#include "arch/arm/vtophys.hh"
51#include "arch/generic/tlb.hh"
52#include "base/statistics.hh"
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/probe/pmu.hh"
56
57class ThreadContext;
58
59namespace ArmISA {
60
61class TableWalker;
62class Stage2LookUp;
63class Stage2MMU;
64
65class TLB : public BaseTLB
66{
67  public:
68    enum ArmFlags {
69        AlignmentMask = 0x7,
70
71        AlignByte = 0x0,
72        AlignHalfWord = 0x1,
73        AlignWord = 0x2,
74        AlignDoubleWord = 0x3,
75        AlignQuadWord = 0x4,
76        AlignOctWord = 0x5,
77
78        AllowUnaligned = 0x8,
79        // Priv code operating as if it wasn't
80        UserMode = 0x10,
81        // Because zero otherwise looks like a valid setting and may be used
82        // accidentally, this bit must be non-zero to show it was used on
83        // purpose.
84        MustBeOne = 0x40
85    };
86
87    enum ArmTranslationType {
88        NormalTran = 0,
89        S1CTran = 0x1,
90        HypMode = 0x2,
91        // Secure code operating as if it wasn't (required by some Address
92        // Translate operations)
93        S1S2NsTran = 0x4
94    };
95  protected:
96    TlbEntry* table;     // the Page Table
97    int size;            // TLB Size
98    bool isStage2;       // Indicates this TLB is part of the second stage MMU
99    bool stage2Req;      // Indicates whether a stage 2 lookup is also required
100    uint64_t _attr;      // Memory attributes for last accessed TLB entry
101    bool directToStage2; // Indicates whether all translation requests should
102                         // be routed directly to the stage 2 TLB
103
104    TableWalker *tableWalker;
105    TLB *stage2Tlb;
106    Stage2MMU *stage2Mmu;
107
108    // Access Stats
109    mutable Stats::Scalar instHits;
110    mutable Stats::Scalar instMisses;
111    mutable Stats::Scalar readHits;
112    mutable Stats::Scalar readMisses;
113    mutable Stats::Scalar writeHits;
114    mutable Stats::Scalar writeMisses;
115    mutable Stats::Scalar inserts;
116    mutable Stats::Scalar flushTlb;
117    mutable Stats::Scalar flushTlbMva;
118    mutable Stats::Scalar flushTlbMvaAsid;
119    mutable Stats::Scalar flushTlbAsid;
120    mutable Stats::Scalar flushedEntries;
121    mutable Stats::Scalar alignFaults;
122    mutable Stats::Scalar prefetchFaults;
123    mutable Stats::Scalar domainFaults;
124    mutable Stats::Scalar permsFaults;
125
126    Stats::Formula readAccesses;
127    Stats::Formula writeAccesses;
128    Stats::Formula instAccesses;
129    Stats::Formula hits;
130    Stats::Formula misses;
131    Stats::Formula accesses;
132
133    /** PMU probe for TLB refills */
134    ProbePoints::PMUUPtr ppRefills;
135
136    int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
137
138  public:
139    TLB(const ArmTLBParams *p);
140    TLB(const Params *p, int _size, TableWalker *_walker);
141
142    /** Lookup an entry in the TLB
143     * @param vpn virtual address
144     * @param asn context id/address space id to use
145     * @param vmid The virtual machine ID used for stage 2 translation
146     * @param secure if the lookup is secure
147     * @param hyp if the lookup is done from hyp mode
148     * @param functional if the lookup should modify state
149     * @param ignore_asn if on lookup asn should be ignored
150     * @return pointer to TLB entry if it exists
151     */
152    TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
153                     bool secure, bool functional,
154                     bool ignore_asn, uint8_t target_el);
155
156    virtual ~TLB();
157
158    void takeOverFrom(BaseTLB *otlb) override;
159
160    /// setup all the back pointers
161    void init() override;
162
163    TableWalker *getTableWalker() { return tableWalker; }
164
165    void setMMU(Stage2MMU *m, MasterID master_id);
166
167    int getsize() const { return size; }
168
169    void insert(Addr vaddr, TlbEntry &pte);
170
171    Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
172                Translation *translation, bool timing, bool functional,
173                bool is_secure, ArmTranslationType tranType);
174
175    Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
176                      Mode mode, Translation *translation, bool timing,
177                      bool functional, TlbEntry *mergeTe);
178
179    Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
180    Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
181                             ThreadContext *tc);
182
183
184    /** Reset the entire TLB
185     * @param secure_lookup if the operation affects the secure world
186     */
187    void flushAllSecurity(bool secure_lookup, uint8_t target_el,
188                          bool ignore_el = false);
189
190    /** Remove all entries in the non secure world, depending on whether they
191     *  were allocated in hyp mode or not
192     * @param hyp if the opperation affects hyp mode
193     */
194    void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
195
196
197    /** Reset the entire TLB. Used for CPU switching to prevent stale
198     * translations after multiple switches
199     */
200    void flushAll() override
201    {
202        flushAllSecurity(false, 0, true);
203        flushAllSecurity(true, 0, true);
204    }
205
206    /** Remove any entries that match both a va and asn
207     * @param mva virtual address to flush
208     * @param asn contextid/asn to flush on match
209     * @param secure_lookup if the operation affects the secure world
210     */
211    void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
212                      uint8_t target_el);
213
214    /** Remove any entries that match the asn
215     * @param asn contextid/asn to flush on match
216     * @param secure_lookup if the operation affects the secure world
217     */
218    void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
219
220    /** Remove all entries that match the va regardless of asn
221     * @param mva address to flush from cache
222     * @param secure_lookup if the operation affects the secure world
223     * @param hyp if the operation affects hyp mode
224     */
225    void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
226
227    Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
228    Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
229            bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
230
231    void printTlb() const;
232
233    void demapPage(Addr vaddr, uint64_t asn) override
234    {
235        // needed for x86 only
236        panic("demapPage() is not implemented.\n");
237    }
238
239    /**
240     * Do a functional lookup on the TLB (for debugging)
241     * and don't modify any internal state
242     * @param tc thread context to get the context id from
243     * @param vaddr virtual address to translate
244     * @param pa returned physical address
245     * @return if the translation was successful
246     */
247    bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
248
249    /**
250     * Do a functional lookup on the TLB (for checker cpu) that
251     * behaves like a normal lookup without modifying any page table state.
252     */
253    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
254            ArmTranslationType tranType = NormalTran);
255
256    /** Accessor functions for memory attributes for last accessed TLB entry
257     */
258    void
259    setAttr(uint64_t attr)
260    {
261        _attr = attr;
262    }
263
264    uint64_t
265    getAttr() const
266    {
267        return _attr;
268    }
269
270    Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
271            Translation *translation, bool &delay,
272            bool timing, ArmTranslationType tranType, bool functional = false);
273    Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
274            Translation *translation, bool &delay, bool timing);
275    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
276            ArmTranslationType tranType = NormalTran);
277    Fault translateTiming(RequestPtr req, ThreadContext *tc,
278            Translation *translation, Mode mode,
279            ArmTranslationType tranType = NormalTran);
280    Fault translateComplete(RequestPtr req, ThreadContext *tc,
281            Translation *translation, Mode mode, ArmTranslationType tranType,
282            bool callFromS2);
283    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
284
285    void drainResume() override;
286
287    // Checkpointing
288    void serialize(CheckpointOut &cp) const override;
289    void unserialize(CheckpointIn &cp) override;
290
291    void regStats() override;
292
293    void regProbePoints() override;
294
295    /**
296     * Get the table walker master port. This is used for migrating
297     * port connections during a CPU takeOverFrom() call. For
298     * architectures that do not have a table walker, NULL is
299     * returned, hence the use of a pointer rather than a
300     * reference. For ARM this method will always return a valid port
301     * pointer.
302     *
303     * @return A pointer to the walker master port
304     */
305    BaseMasterPort* getMasterPort() override;
306
307    // Caching misc register values here.
308    // Writing to misc registers needs to invalidate them.
309    // translateFunctional/translateSe/translateFs checks if they are
310    // invalid and call updateMiscReg if necessary.
311protected:
312    CPSR cpsr;
313    bool aarch64;
314    ExceptionLevel aarch64EL;
315    SCTLR sctlr;
316    SCR scr;
317    bool isPriv;
318    bool isSecure;
319    bool isHyp;
320    TTBCR ttbcr;
321    uint16_t asid;
322    uint8_t vmid;
323    PRRR prrr;
324    NMRR nmrr;
325    HCR hcr;
326    uint32_t dacr;
327    bool miscRegValid;
328    ContextID miscRegContext;
329    ArmTranslationType curTranType;
330
331    // Cached copies of system-level properties
332    bool haveLPAE;
333    bool haveVirtualization;
334    bool haveLargeAsid64;
335
336    void updateMiscReg(ThreadContext *tc,
337                       ArmTranslationType tranType = NormalTran);
338
339public:
340    const Params *
341    params() const
342    {
343        return dynamic_cast<const Params *>(_params);
344    }
345    inline void invalidateMiscReg() { miscRegValid = false; }
346
347private:
348    /** Remove any entries that match both a va and asn
349     * @param mva virtual address to flush
350     * @param asn contextid/asn to flush on match
351     * @param secure_lookup if the operation affects the secure world
352     * @param hyp if the operation affects hyp mode
353     * @param ignore_asn if the flush should ignore the asn
354     */
355    void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
356                   bool hyp, bool ignore_asn, uint8_t target_el);
357
358    bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
359};
360
361} // namespace ArmISA
362
363#endif // __ARCH_ARM_TLB_HH__
364