tlb.hh revision 10687
113312Sgabeblack@google.com/* 213312Sgabeblack@google.com * Copyright (c) 2010-2013 ARM Limited 313312Sgabeblack@google.com * All rights reserved 413312Sgabeblack@google.com * 513312Sgabeblack@google.com * The license below extends only to copyright in the software and shall 613312Sgabeblack@google.com * not be construed as granting a license to any other intellectual 713312Sgabeblack@google.com * property including but not limited to intellectual property relating 813312Sgabeblack@google.com * to a hardware implementation of the functionality of the software 913312Sgabeblack@google.com * licensed hereunder. You may use the software subject to the license 1013312Sgabeblack@google.com * terms below provided that you ensure that this notice is replicated 1113312Sgabeblack@google.com * unmodified and in its entirety in all distributions of the software, 1213312Sgabeblack@google.com * modified or unmodified, in source code or in binary form. 1313312Sgabeblack@google.com * 1413312Sgabeblack@google.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 1513312Sgabeblack@google.com * All rights reserved. 1613312Sgabeblack@google.com * 1713312Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 1813312Sgabeblack@google.com * modification, are permitted provided that the following conditions are 1913312Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 2013312Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 2113312Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 2213312Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 2313312Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 2413312Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 2513312Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 2613312Sgabeblack@google.com * this software without specific prior written permission. 2713312Sgabeblack@google.com * 2813312Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2913312Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3013312Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3113312Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3213312Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3313316Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3413312Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3513312Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3613312Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3713316Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3813312Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3913312Sgabeblack@google.com * 4013312Sgabeblack@google.com * Authors: Ali Saidi 4113312Sgabeblack@google.com */ 4213312Sgabeblack@google.com 4313312Sgabeblack@google.com#ifndef __ARCH_ARM_TLB_HH__ 4413312Sgabeblack@google.com#define __ARCH_ARM_TLB_HH__ 4513312Sgabeblack@google.com 4613312Sgabeblack@google.com 4713312Sgabeblack@google.com#include "arch/arm/isa_traits.hh" 4813312Sgabeblack@google.com#include "arch/arm/pagetable.hh" 4913312Sgabeblack@google.com#include "arch/arm/utility.hh" 5013312Sgabeblack@google.com#include "arch/arm/vtophys.hh" 5113312Sgabeblack@google.com#include "arch/generic/tlb.hh" 5213312Sgabeblack@google.com#include "base/statistics.hh" 5313312Sgabeblack@google.com#include "dev/dma_device.hh" 5413312Sgabeblack@google.com#include "mem/request.hh" 5513312Sgabeblack@google.com#include "params/ArmTLB.hh" 5613312Sgabeblack@google.com#include "sim/probe/pmu.hh" 5713312Sgabeblack@google.com 5813312Sgabeblack@google.comclass ThreadContext; 5913312Sgabeblack@google.com 6013312Sgabeblack@google.comnamespace ArmISA { 6113312Sgabeblack@google.com 6213312Sgabeblack@google.comclass TableWalker; 6313312Sgabeblack@google.comclass Stage2LookUp; 6413312Sgabeblack@google.comclass Stage2MMU; 6513312Sgabeblack@google.com 6613312Sgabeblack@google.comclass TLB : public BaseTLB 6713312Sgabeblack@google.com{ 6813312Sgabeblack@google.com public: 6913312Sgabeblack@google.com enum ArmFlags { 7013312Sgabeblack@google.com AlignmentMask = 0x7, 7113312Sgabeblack@google.com 7213312Sgabeblack@google.com AlignByte = 0x0, 7313312Sgabeblack@google.com AlignHalfWord = 0x1, 7413312Sgabeblack@google.com AlignWord = 0x2, 7513312Sgabeblack@google.com AlignDoubleWord = 0x3, 7613312Sgabeblack@google.com AlignQuadWord = 0x4, 7713312Sgabeblack@google.com AlignOctWord = 0x5, 7813312Sgabeblack@google.com 7913312Sgabeblack@google.com AllowUnaligned = 0x8, 8013312Sgabeblack@google.com // Priv code operating as if it wasn't 8113312Sgabeblack@google.com UserMode = 0x10, 8213312Sgabeblack@google.com // Because zero otherwise looks like a valid setting and may be used 8313312Sgabeblack@google.com // accidentally, this bit must be non-zero to show it was used on 8413312Sgabeblack@google.com // purpose. 8513312Sgabeblack@google.com MustBeOne = 0x40 8613312Sgabeblack@google.com }; 8713312Sgabeblack@google.com 8813312Sgabeblack@google.com enum ArmTranslationType { 8913312Sgabeblack@google.com NormalTran = 0, 9013312Sgabeblack@google.com S1CTran = 0x1, 9113312Sgabeblack@google.com HypMode = 0x2, 9213312Sgabeblack@google.com // Secure code operating as if it wasn't (required by some Address 9313312Sgabeblack@google.com // Translate operations) 9413312Sgabeblack@google.com S1S2NsTran = 0x4 9513312Sgabeblack@google.com }; 9613401Sgabeblack@google.com protected: 9713401Sgabeblack@google.com TlbEntry* table; // the Page Table 9813401Sgabeblack@google.com int size; // TLB Size 9913312Sgabeblack@google.com bool isStage2; // Indicates this TLB is part of the second stage MMU 10013312Sgabeblack@google.com bool stage2Req; // Indicates whether a stage 2 lookup is also required 10113312Sgabeblack@google.com uint64_t _attr; // Memory attributes for last accessed TLB entry 10213312Sgabeblack@google.com bool directToStage2; // Indicates whether all translation requests should 10313312Sgabeblack@google.com // be routed directly to the stage 2 TLB 10413312Sgabeblack@google.com 10513312Sgabeblack@google.com TableWalker *tableWalker; 10613312Sgabeblack@google.com TLB *stage2Tlb; 10713312Sgabeblack@google.com Stage2MMU *stage2Mmu; 10813312Sgabeblack@google.com 10913312Sgabeblack@google.com // Access Stats 11013313Sgabeblack@google.com mutable Stats::Scalar instHits; 11113313Sgabeblack@google.com mutable Stats::Scalar instMisses; 11213316Sgabeblack@google.com mutable Stats::Scalar readHits; 11313316Sgabeblack@google.com mutable Stats::Scalar readMisses; 11413323Sgabeblack@google.com mutable Stats::Scalar writeHits; 11513323Sgabeblack@google.com mutable Stats::Scalar writeMisses; 11613323Sgabeblack@google.com mutable Stats::Scalar inserts; 11713323Sgabeblack@google.com mutable Stats::Scalar flushTlb; 11813323Sgabeblack@google.com mutable Stats::Scalar flushTlbMva; 11913323Sgabeblack@google.com mutable Stats::Scalar flushTlbMvaAsid; 12013323Sgabeblack@google.com mutable Stats::Scalar flushTlbAsid; 12113316Sgabeblack@google.com mutable Stats::Scalar flushedEntries; 12213316Sgabeblack@google.com mutable Stats::Scalar alignFaults; 12313323Sgabeblack@google.com mutable Stats::Scalar prefetchFaults; 12413323Sgabeblack@google.com mutable Stats::Scalar domainFaults; 12513316Sgabeblack@google.com mutable Stats::Scalar permsFaults; 12613316Sgabeblack@google.com 12713312Sgabeblack@google.com Stats::Formula readAccesses; 12813312Sgabeblack@google.com Stats::Formula writeAccesses; 12913312Sgabeblack@google.com Stats::Formula instAccesses; 130 Stats::Formula hits; 131 Stats::Formula misses; 132 Stats::Formula accesses; 133 134 /** PMU probe for TLB refills */ 135 ProbePoints::PMUUPtr ppRefills; 136 137 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 138 139 bool bootUncacheability; 140 141 public: 142 TLB(const ArmTLBParams *p); 143 TLB(const Params *p, int _size, TableWalker *_walker); 144 145 /** Lookup an entry in the TLB 146 * @param vpn virtual address 147 * @param asn context id/address space id to use 148 * @param vmid The virtual machine ID used for stage 2 translation 149 * @param secure if the lookup is secure 150 * @param hyp if the lookup is done from hyp mode 151 * @param functional if the lookup should modify state 152 * @param ignore_asn if on lookup asn should be ignored 153 * @return pointer to TLB entry if it exists 154 */ 155 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 156 bool secure, bool functional, 157 bool ignore_asn, uint8_t target_el); 158 159 virtual ~TLB(); 160 161 void takeOverFrom(BaseTLB *otlb); 162 163 /// setup all the back pointers 164 virtual void init(); 165 166 void setMMU(Stage2MMU *m); 167 168 int getsize() const { return size; } 169 170 void insert(Addr vaddr, TlbEntry &pte); 171 172 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 173 Translation *translation, bool timing, bool functional, 174 bool is_secure, ArmTranslationType tranType); 175 176 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, 177 Mode mode, Translation *translation, bool timing, 178 bool functional, TlbEntry *mergeTe); 179 180 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode); 181 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 182 ThreadContext *tc); 183 184 185 /** Reset the entire TLB 186 * @param secure_lookup if the operation affects the secure world 187 */ 188 void flushAllSecurity(bool secure_lookup, uint8_t target_el, 189 bool ignore_el = false); 190 191 /** Remove all entries in the non secure world, depending on whether they 192 * were allocated in hyp mode or not 193 * @param hyp if the opperation affects hyp mode 194 */ 195 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false); 196 197 198 /** Reset the entire TLB. Used for CPU switching to prevent stale 199 * translations after multiple switches 200 */ 201 void flushAll() 202 { 203 flushAllSecurity(false, 0, true); 204 flushAllSecurity(true, 0, true); 205 } 206 207 /** Remove any entries that match both a va and asn 208 * @param mva virtual address to flush 209 * @param asn contextid/asn to flush on match 210 * @param secure_lookup if the operation affects the secure world 211 */ 212 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 213 uint8_t target_el); 214 215 /** Remove any entries that match the asn 216 * @param asn contextid/asn to flush on match 217 * @param secure_lookup if the operation affects the secure world 218 */ 219 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el); 220 221 /** Remove all entries that match the va regardless of asn 222 * @param mva address to flush from cache 223 * @param secure_lookup if the operation affects the secure world 224 * @param hyp if the operation affects hyp mode 225 */ 226 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); 227 228 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain); 229 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 230 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level); 231 232 void printTlb() const; 233 234 void allCpusCaching() { bootUncacheability = true; } 235 void demapPage(Addr vaddr, uint64_t asn) 236 { 237 // needed for x86 only 238 panic("demapPage() is not implemented.\n"); 239 } 240 241 static bool validVirtualAddress(Addr vaddr); 242 243 /** 244 * Do a functional lookup on the TLB (for debugging) 245 * and don't modify any internal state 246 * @param tc thread context to get the context id from 247 * @param vaddr virtual address to translate 248 * @param pa returned physical address 249 * @return if the translation was successful 250 */ 251 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 252 253 /** 254 * Do a functional lookup on the TLB (for checker cpu) that 255 * behaves like a normal lookup without modifying any page table state. 256 */ 257 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 258 ArmTranslationType tranType = NormalTran); 259 260 /** Accessor functions for memory attributes for last accessed TLB entry 261 */ 262 void 263 setAttr(uint64_t attr) 264 { 265 _attr = attr; 266 } 267 268 uint64_t 269 getAttr() const 270 { 271 return _attr; 272 } 273 274 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 275 Translation *translation, bool &delay, 276 bool timing, ArmTranslationType tranType, bool functional = false); 277 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 278 Translation *translation, bool &delay, bool timing); 279 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 280 ArmTranslationType tranType = NormalTran); 281 Fault translateTiming(RequestPtr req, ThreadContext *tc, 282 Translation *translation, Mode mode, 283 ArmTranslationType tranType = NormalTran); 284 Fault translateComplete(RequestPtr req, ThreadContext *tc, 285 Translation *translation, Mode mode, ArmTranslationType tranType, 286 bool callFromS2); 287 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 288 289 void drainResume(); 290 291 // Checkpointing 292 void serialize(std::ostream &os); 293 void unserialize(Checkpoint *cp, const std::string §ion); 294 295 void regStats(); 296 297 void regProbePoints() M5_ATTR_OVERRIDE; 298 299 /** 300 * Get the table walker master port. This is used for migrating 301 * port connections during a CPU takeOverFrom() call. For 302 * architectures that do not have a table walker, NULL is 303 * returned, hence the use of a pointer rather than a 304 * reference. For ARM this method will always return a valid port 305 * pointer. 306 * 307 * @return A pointer to the walker master port 308 */ 309 virtual BaseMasterPort* getMasterPort(); 310 311 /** 312 * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to 313 * access the table walker port of this TLB so that it can 314 * orchestrate staged translations. 315 * 316 * @return The table walker DMA port 317 */ 318 DmaPort& getWalkerPort(); 319 320 // Caching misc register values here. 321 // Writing to misc registers needs to invalidate them. 322 // translateFunctional/translateSe/translateFs checks if they are 323 // invalid and call updateMiscReg if necessary. 324protected: 325 bool aarch64; 326 ExceptionLevel aarch64EL; 327 SCTLR sctlr; 328 SCR scr; 329 bool isPriv; 330 bool isSecure; 331 bool isHyp; 332 TTBCR ttbcr; 333 uint16_t asid; 334 uint8_t vmid; 335 PRRR prrr; 336 NMRR nmrr; 337 HCR hcr; 338 uint32_t dacr; 339 bool miscRegValid; 340 ArmTranslationType curTranType; 341 342 // Cached copies of system-level properties 343 bool haveLPAE; 344 bool haveVirtualization; 345 bool haveLargeAsid64; 346 347 void updateMiscReg(ThreadContext *tc, 348 ArmTranslationType tranType = NormalTran); 349 350public: 351 const Params * 352 params() const 353 { 354 return dynamic_cast<const Params *>(_params); 355 } 356 inline void invalidateMiscReg() { miscRegValid = false; } 357 358private: 359 /** Remove any entries that match both a va and asn 360 * @param mva virtual address to flush 361 * @param asn contextid/asn to flush on match 362 * @param secure_lookup if the operation affects the secure world 363 * @param hyp if the operation affects hyp mode 364 * @param ignore_asn if the flush should ignore the asn 365 */ 366 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 367 bool hyp, bool ignore_asn, uint8_t target_el); 368 369 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); 370}; 371 372} // namespace ArmISA 373 374#endif // __ARCH_ARM_TLB_HH__ 375