tlb.hh revision 10463
1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 */ 42 43#ifndef __ARCH_ARM_TLB_HH__ 44#define __ARCH_ARM_TLB_HH__ 45 46 47#include "arch/arm/isa_traits.hh" 48#include "arch/arm/pagetable.hh" 49#include "arch/arm/utility.hh" 50#include "arch/arm/vtophys.hh" 51#include "base/statistics.hh" 52#include "dev/dma_device.hh" 53#include "mem/request.hh" 54#include "params/ArmTLB.hh" 55#include "sim/fault_fwd.hh" 56#include "sim/probe/pmu.hh" 57#include "sim/tlb.hh" 58 59class ThreadContext; 60 61namespace ArmISA { 62 63class TableWalker; 64class Stage2LookUp; 65class Stage2MMU; 66 67class TLB : public BaseTLB 68{ 69 public: 70 enum ArmFlags { 71 AlignmentMask = 0x7, 72 73 AlignByte = 0x0, 74 AlignHalfWord = 0x1, 75 AlignWord = 0x2, 76 AlignDoubleWord = 0x3, 77 AlignQuadWord = 0x4, 78 AlignOctWord = 0x5, 79 80 AllowUnaligned = 0x8, 81 // Priv code operating as if it wasn't 82 UserMode = 0x10, 83 // Because zero otherwise looks like a valid setting and may be used 84 // accidentally, this bit must be non-zero to show it was used on 85 // purpose. 86 MustBeOne = 0x40 87 }; 88 89 enum ArmTranslationType { 90 NormalTran = 0, 91 S1CTran = 0x1, 92 HypMode = 0x2, 93 // Secure code operating as if it wasn't (required by some Address 94 // Translate operations) 95 S1S2NsTran = 0x4 96 }; 97 protected: 98 TlbEntry* table; // the Page Table 99 int size; // TLB Size 100 bool isStage2; // Indicates this TLB is part of the second stage MMU 101 bool stage2Req; // Indicates whether a stage 2 lookup is also required 102 uint64_t _attr; // Memory attributes for last accessed TLB entry 103 bool directToStage2; // Indicates whether all translation requests should 104 // be routed directly to the stage 2 TLB 105 106 TableWalker *tableWalker; 107 TLB *stage2Tlb; 108 Stage2MMU *stage2Mmu; 109 110 // Access Stats 111 mutable Stats::Scalar instHits; 112 mutable Stats::Scalar instMisses; 113 mutable Stats::Scalar readHits; 114 mutable Stats::Scalar readMisses; 115 mutable Stats::Scalar writeHits; 116 mutable Stats::Scalar writeMisses; 117 mutable Stats::Scalar inserts; 118 mutable Stats::Scalar flushTlb; 119 mutable Stats::Scalar flushTlbMva; 120 mutable Stats::Scalar flushTlbMvaAsid; 121 mutable Stats::Scalar flushTlbAsid; 122 mutable Stats::Scalar flushedEntries; 123 mutable Stats::Scalar alignFaults; 124 mutable Stats::Scalar prefetchFaults; 125 mutable Stats::Scalar domainFaults; 126 mutable Stats::Scalar permsFaults; 127 128 Stats::Formula readAccesses; 129 Stats::Formula writeAccesses; 130 Stats::Formula instAccesses; 131 Stats::Formula hits; 132 Stats::Formula misses; 133 Stats::Formula accesses; 134 135 /** PMU probe for TLB refills */ 136 ProbePoints::PMUUPtr ppRefills; 137 138 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 139 140 bool bootUncacheability; 141 142 public: 143 TLB(const ArmTLBParams *p); 144 TLB(const Params *p, int _size, TableWalker *_walker); 145 146 /** Lookup an entry in the TLB 147 * @param vpn virtual address 148 * @param asn context id/address space id to use 149 * @param vmid The virtual machine ID used for stage 2 translation 150 * @param secure if the lookup is secure 151 * @param hyp if the lookup is done from hyp mode 152 * @param functional if the lookup should modify state 153 * @param ignore_asn if on lookup asn should be ignored 154 * @return pointer to TLB entry if it exists 155 */ 156 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 157 bool secure, bool functional, 158 bool ignore_asn, uint8_t target_el); 159 160 virtual ~TLB(); 161 162 void takeOverFrom(BaseTLB *otlb); 163 164 /// setup all the back pointers 165 virtual void init(); 166 167 void setMMU(Stage2MMU *m); 168 169 int getsize() const { return size; } 170 171 void insert(Addr vaddr, TlbEntry &pte); 172 173 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 174 Translation *translation, bool timing, bool functional, 175 bool is_secure, ArmTranslationType tranType); 176 177 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, 178 Mode mode, Translation *translation, bool timing, 179 bool functional, TlbEntry *mergeTe); 180 181 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode); 182 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 183 ThreadContext *tc); 184 185 186 /** Reset the entire TLB 187 * @param secure_lookup if the operation affects the secure world 188 */ 189 void flushAllSecurity(bool secure_lookup, uint8_t target_el, 190 bool ignore_el = false); 191 192 /** Remove all entries in the non secure world, depending on whether they 193 * were allocated in hyp mode or not 194 * @param hyp if the opperation affects hyp mode 195 */ 196 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false); 197 198 199 /** Reset the entire TLB. Used for CPU switching to prevent stale 200 * translations after multiple switches 201 */ 202 void flushAll() 203 { 204 flushAllSecurity(false, 0, true); 205 flushAllSecurity(true, 0, true); 206 } 207 208 /** Remove any entries that match both a va and asn 209 * @param mva virtual address to flush 210 * @param asn contextid/asn to flush on match 211 * @param secure_lookup if the operation affects the secure world 212 */ 213 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 214 uint8_t target_el); 215 216 /** Remove any entries that match the asn 217 * @param asn contextid/asn to flush on match 218 * @param secure_lookup if the operation affects the secure world 219 */ 220 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el); 221 222 /** Remove all entries that match the va regardless of asn 223 * @param mva address to flush from cache 224 * @param secure_lookup if the operation affects the secure world 225 * @param hyp if the operation affects hyp mode 226 */ 227 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); 228 229 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain); 230 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 231 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level); 232 233 void printTlb() const; 234 235 void allCpusCaching() { bootUncacheability = true; } 236 void demapPage(Addr vaddr, uint64_t asn) 237 { 238 // needed for x86 only 239 panic("demapPage() is not implemented.\n"); 240 } 241 242 static bool validVirtualAddress(Addr vaddr); 243 244 /** 245 * Do a functional lookup on the TLB (for debugging) 246 * and don't modify any internal state 247 * @param tc thread context to get the context id from 248 * @param vaddr virtual address to translate 249 * @param pa returned physical address 250 * @return if the translation was successful 251 */ 252 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 253 254 /** 255 * Do a functional lookup on the TLB (for checker cpu) that 256 * behaves like a normal lookup without modifying any page table state. 257 */ 258 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 259 ArmTranslationType tranType = NormalTran); 260 261 /** Accessor functions for memory attributes for last accessed TLB entry 262 */ 263 void 264 setAttr(uint64_t attr) 265 { 266 _attr = attr; 267 } 268 269 uint64_t 270 getAttr() const 271 { 272 return _attr; 273 } 274 275 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 276 Translation *translation, bool &delay, 277 bool timing, ArmTranslationType tranType, bool functional = false); 278 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 279 Translation *translation, bool &delay, bool timing); 280 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 281 ArmTranslationType tranType = NormalTran); 282 Fault translateTiming(RequestPtr req, ThreadContext *tc, 283 Translation *translation, Mode mode, 284 ArmTranslationType tranType = NormalTran); 285 Fault translateComplete(RequestPtr req, ThreadContext *tc, 286 Translation *translation, Mode mode, ArmTranslationType tranType, 287 bool callFromS2); 288 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 289 290 void drainResume(); 291 292 // Checkpointing 293 void serialize(std::ostream &os); 294 void unserialize(Checkpoint *cp, const std::string §ion); 295 296 void regStats(); 297 298 void regProbePoints() M5_ATTR_OVERRIDE; 299 300 /** 301 * Get the table walker master port. This is used for migrating 302 * port connections during a CPU takeOverFrom() call. For 303 * architectures that do not have a table walker, NULL is 304 * returned, hence the use of a pointer rather than a 305 * reference. For ARM this method will always return a valid port 306 * pointer. 307 * 308 * @return A pointer to the walker master port 309 */ 310 virtual BaseMasterPort* getMasterPort(); 311 312 /** 313 * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to 314 * access the table walker port of this TLB so that it can 315 * orchestrate staged translations. 316 * 317 * @return The table walker DMA port 318 */ 319 DmaPort& getWalkerPort(); 320 321 // Caching misc register values here. 322 // Writing to misc registers needs to invalidate them. 323 // translateFunctional/translateSe/translateFs checks if they are 324 // invalid and call updateMiscReg if necessary. 325protected: 326 bool aarch64; 327 ExceptionLevel aarch64EL; 328 SCTLR sctlr; 329 SCR scr; 330 bool isPriv; 331 bool isSecure; 332 bool isHyp; 333 TTBCR ttbcr; 334 uint16_t asid; 335 uint8_t vmid; 336 PRRR prrr; 337 NMRR nmrr; 338 HCR hcr; 339 uint32_t dacr; 340 bool miscRegValid; 341 ArmTranslationType curTranType; 342 343 // Cached copies of system-level properties 344 bool haveLPAE; 345 bool haveVirtualization; 346 bool haveLargeAsid64; 347 348 void updateMiscReg(ThreadContext *tc, 349 ArmTranslationType tranType = NormalTran); 350 351public: 352 const Params * 353 params() const 354 { 355 return dynamic_cast<const Params *>(_params); 356 } 357 inline void invalidateMiscReg() { miscRegValid = false; } 358 359private: 360 /** Remove any entries that match both a va and asn 361 * @param mva virtual address to flush 362 * @param asn contextid/asn to flush on match 363 * @param secure_lookup if the operation affects the secure world 364 * @param hyp if the operation affects hyp mode 365 * @param ignore_asn if the flush should ignore the asn 366 */ 367 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 368 bool hyp, bool ignore_asn, uint8_t target_el); 369 370 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); 371}; 372 373} // namespace ArmISA 374 375#endif // __ARCH_ARM_TLB_HH__ 376