tlb.hh revision 10037:5cac77888310
17405SAli.Saidi@ARM.com/* 212667Schuan.zhu@arm.com * Copyright (c) 2010-2013 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 157405SAli.Saidi@ARM.com * All rights reserved. 167405SAli.Saidi@ARM.com * 177405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 187405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 197405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 207405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 217405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 227405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 237405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 247405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 257405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 267405SAli.Saidi@ARM.com * this software without specific prior written permission. 277405SAli.Saidi@ARM.com * 287405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397405SAli.Saidi@ARM.com * 407405SAli.Saidi@ARM.com * Authors: Ali Saidi 417405SAli.Saidi@ARM.com */ 4210461SAndreas.Sandberg@ARM.com 439050Schander.sudanthi@arm.com#ifndef __ARCH_ARM_TLB_HH__ 4412406Sgabeblack@google.com#define __ARCH_ARM_TLB_HH__ 4512605Sgiacomo.travaglini@arm.com 4611793Sbrandon.potter@amd.com 478887Sgeoffrey.blake@arm.com#include "arch/arm/isa_traits.hh" 488232Snate@binkert.org#include "arch/arm/pagetable.hh" 498232Snate@binkert.org#include "arch/arm/utility.hh" 5010844Sandreas.sandberg@arm.com#include "arch/arm/vtophys.hh" 519384SAndreas.Sandberg@arm.com#include "base/statistics.hh" 527678Sgblack@eecs.umich.edu#include "dev/dma_device.hh" 538059SAli.Saidi@ARM.com#include "mem/request.hh" 548284SAli.Saidi@ARM.com#include "params/ArmTLB.hh" 557405SAli.Saidi@ARM.com#include "sim/fault_fwd.hh" 567405SAli.Saidi@ARM.com#include "sim/tlb.hh" 577405SAli.Saidi@ARM.com 587405SAli.Saidi@ARM.comclass ThreadContext; 599384SAndreas.Sandberg@arm.com 6010461SAndreas.Sandberg@ARM.comnamespace ArmISA { 6110461SAndreas.Sandberg@ARM.com 6211165SRekai.GonzalezAlberquilla@arm.comclass TableWalker; 6312109SRekai.GonzalezAlberquilla@arm.comclass Stage2LookUp; 6412479SCurtis.Dunham@arm.comclass Stage2MMU; 659384SAndreas.Sandberg@arm.com 6611770SCurtis.Dunham@arm.comclass TLB : public BaseTLB 6710037SARM gem5 Developers{ 6810461SAndreas.Sandberg@ARM.com public: 6910461SAndreas.Sandberg@ARM.com enum ArmFlags { 7010461SAndreas.Sandberg@ARM.com AlignmentMask = 0x7, 7110461SAndreas.Sandberg@ARM.com 7210461SAndreas.Sandberg@ARM.com AlignByte = 0x0, 7310461SAndreas.Sandberg@ARM.com AlignHalfWord = 0x1, 7410609Sandreas.sandberg@arm.com AlignWord = 0x2, 7510609Sandreas.sandberg@arm.com AlignDoubleWord = 0x3, 7610609Sandreas.sandberg@arm.com AlignQuadWord = 0x4, 7710037SARM gem5 Developers AlignOctWord = 0x5, 7810037SARM gem5 Developers 7910037SARM gem5 Developers AllowUnaligned = 0x8, 8010037SARM gem5 Developers // Priv code operating as if it wasn't 8111771SCurtis.Dunham@arm.com UserMode = 0x10, 8210037SARM gem5 Developers // Because zero otherwise looks like a valid setting and may be used 8310037SARM gem5 Developers // accidentally, this bit must be non-zero to show it was used on 8410037SARM gem5 Developers // purpose. 8510037SARM gem5 Developers MustBeOne = 0x40 8610037SARM gem5 Developers }; 8710037SARM gem5 Developers 8811771SCurtis.Dunham@arm.com enum ArmTranslationType { 8910037SARM gem5 Developers NormalTran = 0, 9010037SARM gem5 Developers S1CTran = 0x1, 9110037SARM gem5 Developers HypMode = 0x2, 9210037SARM gem5 Developers // Secure code operating as if it wasn't (required by some Address 9310037SARM gem5 Developers // Translate operations) 9412477SCurtis.Dunham@arm.com S1S2NsTran = 0x4 9510037SARM gem5 Developers }; 9610037SARM gem5 Developers protected: 979384SAndreas.Sandberg@arm.com TlbEntry* table; // the Page Table 989384SAndreas.Sandberg@arm.com int size; // TLB Size 999384SAndreas.Sandberg@arm.com bool isStage2; // Indicates this TLB is part of the second stage MMU 10012479SCurtis.Dunham@arm.com bool stage2Req; // Indicates whether a stage 2 lookup is also required 10112479SCurtis.Dunham@arm.com uint64_t _attr; // Memory attributes for last accessed TLB entry 1029384SAndreas.Sandberg@arm.com bool directToStage2; // Indicates whether all translation requests should 1039384SAndreas.Sandberg@arm.com // be routed directly to the stage 2 TLB 1049384SAndreas.Sandberg@arm.com 1059384SAndreas.Sandberg@arm.com TableWalker *tableWalker; 1069384SAndreas.Sandberg@arm.com TLB *stage2Tlb; 1079384SAndreas.Sandberg@arm.com Stage2MMU *stage2Mmu; 1087427Sgblack@eecs.umich.edu 1097427Sgblack@eecs.umich.edu // Access Stats 1107427Sgblack@eecs.umich.edu mutable Stats::Scalar instHits; 1119385SAndreas.Sandberg@arm.com mutable Stats::Scalar instMisses; 1129385SAndreas.Sandberg@arm.com mutable Stats::Scalar readHits; 1137427Sgblack@eecs.umich.edu mutable Stats::Scalar readMisses; 1147427Sgblack@eecs.umich.edu mutable Stats::Scalar writeHits; 11510037SARM gem5 Developers mutable Stats::Scalar writeMisses; 11610037SARM gem5 Developers mutable Stats::Scalar inserts; 11710037SARM gem5 Developers mutable Stats::Scalar flushTlb; 11810037SARM gem5 Developers mutable Stats::Scalar flushTlbMva; 11910037SARM gem5 Developers mutable Stats::Scalar flushTlbMvaAsid; 12010037SARM gem5 Developers mutable Stats::Scalar flushTlbAsid; 12110037SARM gem5 Developers mutable Stats::Scalar flushedEntries; 12210037SARM gem5 Developers mutable Stats::Scalar alignFaults; 12310037SARM gem5 Developers mutable Stats::Scalar prefetchFaults; 12410037SARM gem5 Developers mutable Stats::Scalar domainFaults; 12510037SARM gem5 Developers mutable Stats::Scalar permsFaults; 12610037SARM gem5 Developers 12710037SARM gem5 Developers Stats::Formula readAccesses; 12810037SARM gem5 Developers Stats::Formula writeAccesses; 1297427Sgblack@eecs.umich.edu Stats::Formula instAccesses; 1307427Sgblack@eecs.umich.edu Stats::Formula hits; 1317427Sgblack@eecs.umich.edu Stats::Formula misses; 1327427Sgblack@eecs.umich.edu Stats::Formula accesses; 1337427Sgblack@eecs.umich.edu 1347427Sgblack@eecs.umich.edu int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 13510037SARM gem5 Developers 13610037SARM gem5 Developers bool bootUncacheability; 13710037SARM gem5 Developers 13810037SARM gem5 Developers public: 1397427Sgblack@eecs.umich.edu TLB(const ArmTLBParams *p); 1407427Sgblack@eecs.umich.edu TLB(const Params *p, int _size, TableWalker *_walker); 1417427Sgblack@eecs.umich.edu 14210037SARM gem5 Developers /** Lookup an entry in the TLB 14310204SAli.Saidi@ARM.com * @param vpn virtual address 14410204SAli.Saidi@ARM.com * @param asn context id/address space id to use 14510037SARM gem5 Developers * @param vmid The virtual machine ID used for stage 2 translation 1467427Sgblack@eecs.umich.edu * @param secure if the lookup is secure 14710037SARM gem5 Developers * @param hyp if the lookup is done from hyp mode 1487427Sgblack@eecs.umich.edu * @param functional if the lookup should modify state 14910037SARM gem5 Developers * @param ignore_asn if on lookup asn should be ignored 1507427Sgblack@eecs.umich.edu * @return pointer to TLB entry if it exists 1517427Sgblack@eecs.umich.edu */ 15210037SARM gem5 Developers TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 1537427Sgblack@eecs.umich.edu bool secure, bool functional, 1547427Sgblack@eecs.umich.edu bool ignore_asn, uint8_t target_el); 1557427Sgblack@eecs.umich.edu 1567427Sgblack@eecs.umich.edu virtual ~TLB(); 1577427Sgblack@eecs.umich.edu 1587427Sgblack@eecs.umich.edu /// setup all the back pointers 1597427Sgblack@eecs.umich.edu virtual void init(); 1607427Sgblack@eecs.umich.edu 1617427Sgblack@eecs.umich.edu void setMMU(Stage2MMU *m); 1627427Sgblack@eecs.umich.edu 1637427Sgblack@eecs.umich.edu int getsize() const { return size; } 1647427Sgblack@eecs.umich.edu 1657427Sgblack@eecs.umich.edu void insert(Addr vaddr, TlbEntry &pte); 1667427Sgblack@eecs.umich.edu 1677427Sgblack@eecs.umich.edu Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 1687427Sgblack@eecs.umich.edu Translation *translation, bool timing, bool functional, 1697427Sgblack@eecs.umich.edu bool is_secure, ArmTranslationType tranType); 1707427Sgblack@eecs.umich.edu 1717427Sgblack@eecs.umich.edu Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, 1727427Sgblack@eecs.umich.edu Mode mode, Translation *translation, bool timing, 1737427Sgblack@eecs.umich.edu bool functional, TlbEntry *mergeTe); 1747427Sgblack@eecs.umich.edu 1757427Sgblack@eecs.umich.edu Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode); 1767436Sdam.sunwoo@arm.com Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 1777436Sdam.sunwoo@arm.com ThreadContext *tc); 17810037SARM gem5 Developers 17910037SARM gem5 Developers 1807436Sdam.sunwoo@arm.com /** Reset the entire TLB 1817436Sdam.sunwoo@arm.com * @param secure_lookup if the operation affects the secure world 1827436Sdam.sunwoo@arm.com */ 1837436Sdam.sunwoo@arm.com void flushAllSecurity(bool secure_lookup, uint8_t target_el, 1847436Sdam.sunwoo@arm.com bool ignore_el = false); 1857436Sdam.sunwoo@arm.com 1867436Sdam.sunwoo@arm.com /** Remove all entries in the non secure world, depending on whether they 1877436Sdam.sunwoo@arm.com * were allocated in hyp mode or not 1887436Sdam.sunwoo@arm.com * @param hyp if the opperation affects hyp mode 1897436Sdam.sunwoo@arm.com */ 1907436Sdam.sunwoo@arm.com void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false); 1917436Sdam.sunwoo@arm.com 19210037SARM gem5 Developers 1937436Sdam.sunwoo@arm.com /** Reset the entire TLB. Used for CPU switching to prevent stale 1947436Sdam.sunwoo@arm.com * translations after multiple switches 1957436Sdam.sunwoo@arm.com */ 1967436Sdam.sunwoo@arm.com void flushAll() 1977436Sdam.sunwoo@arm.com { 1987436Sdam.sunwoo@arm.com flushAllSecurity(false, 0, true); 1997436Sdam.sunwoo@arm.com flushAllSecurity(true, 0, true); 2007436Sdam.sunwoo@arm.com } 2017436Sdam.sunwoo@arm.com 2027436Sdam.sunwoo@arm.com /** Remove any entries that match both a va and asn 2037436Sdam.sunwoo@arm.com * @param mva virtual address to flush 2047436Sdam.sunwoo@arm.com * @param asn contextid/asn to flush on match 2057436Sdam.sunwoo@arm.com * @param secure_lookup if the operation affects the secure world 2067436Sdam.sunwoo@arm.com */ 2077436Sdam.sunwoo@arm.com void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 2087436Sdam.sunwoo@arm.com uint8_t target_el); 2097644Sali.saidi@arm.com 2108147SAli.Saidi@ARM.com /** Remove any entries that match the asn 2119385SAndreas.Sandberg@arm.com * @param asn contextid/asn to flush on match 2129385SAndreas.Sandberg@arm.com * @param secure_lookup if the operation affects the secure world 2139385SAndreas.Sandberg@arm.com */ 2149385SAndreas.Sandberg@arm.com void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el); 2159385SAndreas.Sandberg@arm.com 2169385SAndreas.Sandberg@arm.com /** Remove all entries that match the va regardless of asn 2179385SAndreas.Sandberg@arm.com * @param mva address to flush from cache 2189385SAndreas.Sandberg@arm.com * @param secure_lookup if the operation affects the secure world 2199385SAndreas.Sandberg@arm.com * @param hyp if the operation affects hyp mode 2209385SAndreas.Sandberg@arm.com */ 2219385SAndreas.Sandberg@arm.com void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); 2229385SAndreas.Sandberg@arm.com 2239385SAndreas.Sandberg@arm.com Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain); 2249385SAndreas.Sandberg@arm.com Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 22510037SARM gem5 Developers bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level); 22610037SARM gem5 Developers 22710037SARM gem5 Developers void printTlb() const; 22810037SARM gem5 Developers 22910037SARM gem5 Developers void allCpusCaching() { bootUncacheability = true; } 23010037SARM gem5 Developers void demapPage(Addr vaddr, uint64_t asn) 23110037SARM gem5 Developers { 23210037SARM gem5 Developers // needed for x86 only 23310037SARM gem5 Developers panic("demapPage() is not implemented.\n"); 23410037SARM gem5 Developers } 23510037SARM gem5 Developers 23610037SARM gem5 Developers static bool validVirtualAddress(Addr vaddr); 23710037SARM gem5 Developers 23810037SARM gem5 Developers /** 23910037SARM gem5 Developers * Do a functional lookup on the TLB (for debugging) 24010037SARM gem5 Developers * and don't modify any internal state 2418147SAli.Saidi@ARM.com * @param tc thread context to get the context id from 2427427Sgblack@eecs.umich.edu * @param vaddr virtual address to translate 2437427Sgblack@eecs.umich.edu * @param pa returned physical address 2447427Sgblack@eecs.umich.edu * @return if the translation was successful 24510037SARM gem5 Developers */ 24610037SARM gem5 Developers bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 24710037SARM gem5 Developers 24810037SARM gem5 Developers /** 24910037SARM gem5 Developers * Do a functional lookup on the TLB (for checker cpu) that 25010037SARM gem5 Developers * behaves like a normal lookup without modifying any page table state. 25110037SARM gem5 Developers */ 25210037SARM gem5 Developers Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 25310037SARM gem5 Developers ArmTranslationType tranType = NormalTran); 25410037SARM gem5 Developers 25510037SARM gem5 Developers /** Accessor functions for memory attributes for last accessed TLB entry 25610037SARM gem5 Developers */ 25710037SARM gem5 Developers void 25810037SARM gem5 Developers setAttr(uint64_t attr) 25910037SARM gem5 Developers { 26010037SARM gem5 Developers _attr = attr; 26110037SARM gem5 Developers } 26210037SARM gem5 Developers 26310037SARM gem5 Developers uint64_t 26410037SARM gem5 Developers getAttr() const 26510037SARM gem5 Developers { 26610037SARM gem5 Developers return _attr; 26710037SARM gem5 Developers } 26810037SARM gem5 Developers 26910037SARM gem5 Developers Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 27010037SARM gem5 Developers Translation *translation, bool &delay, 27110037SARM gem5 Developers bool timing, ArmTranslationType tranType, bool functional = false); 27210037SARM gem5 Developers Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 27310037SARM gem5 Developers Translation *translation, bool &delay, bool timing); 27410037SARM gem5 Developers Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 27510037SARM gem5 Developers ArmTranslationType tranType = NormalTran); 27610037SARM gem5 Developers Fault translateTiming(RequestPtr req, ThreadContext *tc, 27710037SARM gem5 Developers Translation *translation, Mode mode, 27810037SARM gem5 Developers ArmTranslationType tranType = NormalTran); 27910037SARM gem5 Developers Fault translateComplete(RequestPtr req, ThreadContext *tc, 28010037SARM gem5 Developers Translation *translation, Mode mode, ArmTranslationType tranType, 28111770SCurtis.Dunham@arm.com bool callFromS2); 28210037SARM gem5 Developers Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 28311574SCurtis.Dunham@arm.com 28411770SCurtis.Dunham@arm.com void drainResume(); 28511770SCurtis.Dunham@arm.com 28610037SARM gem5 Developers // Checkpointing 28711770SCurtis.Dunham@arm.com void serialize(std::ostream &os); 28811770SCurtis.Dunham@arm.com void unserialize(Checkpoint *cp, const std::string §ion); 28910037SARM gem5 Developers 29010037SARM gem5 Developers void regStats(); 29110037SARM gem5 Developers 29210037SARM gem5 Developers /** 29310037SARM gem5 Developers * Get the table walker master port. This is used for migrating 29410037SARM gem5 Developers * port connections during a CPU takeOverFrom() call. For 29510037SARM gem5 Developers * architectures that do not have a table walker, NULL is 29610461SAndreas.Sandberg@ARM.com * returned, hence the use of a pointer rather than a 29710461SAndreas.Sandberg@ARM.com * reference. For ARM this method will always return a valid port 29810461SAndreas.Sandberg@ARM.com * pointer. 29910461SAndreas.Sandberg@ARM.com * 30010037SARM gem5 Developers * @return A pointer to the walker master port 30110037SARM gem5 Developers */ 30210037SARM gem5 Developers virtual BaseMasterPort* getMasterPort(); 30310037SARM gem5 Developers 30410037SARM gem5 Developers /** 30510037SARM gem5 Developers * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to 30610461SAndreas.Sandberg@ARM.com * access the table walker port of this TLB so that it can 30710461SAndreas.Sandberg@ARM.com * orchestrate staged translations. 30810461SAndreas.Sandberg@ARM.com * 30910461SAndreas.Sandberg@ARM.com * @return The table walker DMA port 31010461SAndreas.Sandberg@ARM.com */ 31110037SARM gem5 Developers DmaPort& getWalkerPort(); 31210037SARM gem5 Developers 31310037SARM gem5 Developers // Caching misc register values here. 31410037SARM gem5 Developers // Writing to misc registers needs to invalidate them. 31510037SARM gem5 Developers // translateFunctional/translateSe/translateFs checks if they are 31611574SCurtis.Dunham@arm.com // invalid and call updateMiscReg if necessary. 31710037SARM gem5 Developersprotected: 31810037SARM gem5 Developers bool aarch64; 31910037SARM gem5 Developers ExceptionLevel aarch64EL; 32011574SCurtis.Dunham@arm.com SCTLR sctlr; 32110037SARM gem5 Developers SCR scr; 32210037SARM gem5 Developers bool isPriv; 32310037SARM gem5 Developers bool isSecure; 32410037SARM gem5 Developers bool isHyp; 32510037SARM gem5 Developers TTBCR ttbcr; 32610037SARM gem5 Developers uint16_t asid; 32710037SARM gem5 Developers uint8_t vmid; 32810037SARM gem5 Developers PRRR prrr; 32910037SARM gem5 Developers NMRR nmrr; 33010037SARM gem5 Developers HCR hcr; 3317405SAli.Saidi@ARM.com uint32_t dacr; 33210035Sandreas.hansson@arm.com bool miscRegValid; 3337405SAli.Saidi@ARM.com ArmTranslationType curTranType; 3347405SAli.Saidi@ARM.com 3357614Sminkyu.jeong@arm.com // Cached copies of system-level properties 33612478SCurtis.Dunham@arm.com bool haveLPAE; 33712478SCurtis.Dunham@arm.com bool haveVirtualization; 33812478SCurtis.Dunham@arm.com bool haveLargeAsid64; 33912478SCurtis.Dunham@arm.com 34012478SCurtis.Dunham@arm.com void updateMiscReg(ThreadContext *tc, 34112478SCurtis.Dunham@arm.com ArmTranslationType tranType = NormalTran); 34212478SCurtis.Dunham@arm.com 34312478SCurtis.Dunham@arm.compublic: 34412478SCurtis.Dunham@arm.com const Params * 34512478SCurtis.Dunham@arm.com params() const 34612478SCurtis.Dunham@arm.com { 34712478SCurtis.Dunham@arm.com return dynamic_cast<const Params *>(_params); 34812478SCurtis.Dunham@arm.com } 34912478SCurtis.Dunham@arm.com inline void invalidateMiscReg() { miscRegValid = false; } 35012478SCurtis.Dunham@arm.com 35112478SCurtis.Dunham@arm.comprivate: 3527405SAli.Saidi@ARM.com /** Remove any entries that match both a va and asn 3537405SAli.Saidi@ARM.com * @param mva virtual address to flush 3547405SAli.Saidi@ARM.com * @param asn contextid/asn to flush on match 3557405SAli.Saidi@ARM.com * @param secure_lookup if the operation affects the secure world 3567405SAli.Saidi@ARM.com * @param hyp if the operation affects hyp mode 3577405SAli.Saidi@ARM.com * @param ignore_asn if the flush should ignore the asn 35810037SARM gem5 Developers */ 35910037SARM gem5 Developers void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 36010037SARM gem5 Developers bool hyp, bool ignore_asn, uint8_t target_el); 3619050Schander.sudanthi@arm.com 3627405SAli.Saidi@ARM.com bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); 36310037SARM gem5 Developers}; 36410037SARM gem5 Developers 3657720Sgblack@eecs.umich.edu} // namespace ArmISA 3667720Sgblack@eecs.umich.edu 3677405SAli.Saidi@ARM.com#endif // __ARCH_ARM_TLB_HH__ 3687405SAli.Saidi@ARM.com