tlb.hh revision 10037:5cac77888310 
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/pagetable.hh"
49#include "arch/arm/utility.hh"
50#include "arch/arm/vtophys.hh"
51#include "base/statistics.hh"
52#include "dev/dma_device.hh"
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/fault_fwd.hh"
56#include "sim/tlb.hh"
57
58class ThreadContext;
59
60namespace ArmISA {
61
62class TableWalker;
63class Stage2LookUp;
64class Stage2MMU;
65
66class TLB : public BaseTLB
67{
68  public:
69    enum ArmFlags {
70        AlignmentMask = 0x7,
71
72        AlignByte = 0x0,
73        AlignHalfWord = 0x1,
74        AlignWord = 0x2,
75        AlignDoubleWord = 0x3,
76        AlignQuadWord = 0x4,
77        AlignOctWord = 0x5,
78
79        AllowUnaligned = 0x8,
80        // Priv code operating as if it wasn't
81        UserMode = 0x10,
82        // Because zero otherwise looks like a valid setting and may be used
83        // accidentally, this bit must be non-zero to show it was used on
84        // purpose.
85        MustBeOne = 0x40
86    };
87
88    enum ArmTranslationType {
89        NormalTran = 0,
90        S1CTran = 0x1,
91        HypMode = 0x2,
92        // Secure code operating as if it wasn't (required by some Address
93        // Translate operations)
94        S1S2NsTran = 0x4
95    };
96  protected:
97    TlbEntry* table;     // the Page Table
98    int size;            // TLB Size
99    bool isStage2;       // Indicates this TLB is part of the second stage MMU
100    bool stage2Req;      // Indicates whether a stage 2 lookup is also required
101    uint64_t _attr;      // Memory attributes for last accessed TLB entry
102    bool directToStage2; // Indicates whether all translation requests should
103                         // be routed directly to the stage 2 TLB
104
105    TableWalker *tableWalker;
106    TLB *stage2Tlb;
107    Stage2MMU *stage2Mmu;
108
109    // Access Stats
110    mutable Stats::Scalar instHits;
111    mutable Stats::Scalar instMisses;
112    mutable Stats::Scalar readHits;
113    mutable Stats::Scalar readMisses;
114    mutable Stats::Scalar writeHits;
115    mutable Stats::Scalar writeMisses;
116    mutable Stats::Scalar inserts;
117    mutable Stats::Scalar flushTlb;
118    mutable Stats::Scalar flushTlbMva;
119    mutable Stats::Scalar flushTlbMvaAsid;
120    mutable Stats::Scalar flushTlbAsid;
121    mutable Stats::Scalar flushedEntries;
122    mutable Stats::Scalar alignFaults;
123    mutable Stats::Scalar prefetchFaults;
124    mutable Stats::Scalar domainFaults;
125    mutable Stats::Scalar permsFaults;
126
127    Stats::Formula readAccesses;
128    Stats::Formula writeAccesses;
129    Stats::Formula instAccesses;
130    Stats::Formula hits;
131    Stats::Formula misses;
132    Stats::Formula accesses;
133
134    int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
135
136    bool bootUncacheability;
137
138  public:
139    TLB(const ArmTLBParams *p);
140    TLB(const Params *p, int _size, TableWalker *_walker);
141
142    /** Lookup an entry in the TLB
143     * @param vpn virtual address
144     * @param asn context id/address space id to use
145     * @param vmid The virtual machine ID used for stage 2 translation
146     * @param secure if the lookup is secure
147     * @param hyp if the lookup is done from hyp mode
148     * @param functional if the lookup should modify state
149     * @param ignore_asn if on lookup asn should be ignored
150     * @return pointer to TLB entry if it exists
151     */
152    TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
153                     bool secure, bool functional,
154                     bool ignore_asn, uint8_t target_el);
155
156    virtual ~TLB();
157
158    /// setup all the back pointers
159    virtual void init();
160
161    void setMMU(Stage2MMU *m);
162
163    int getsize() const { return size; }
164
165    void insert(Addr vaddr, TlbEntry &pte);
166
167    Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
168                Translation *translation, bool timing, bool functional,
169                bool is_secure, ArmTranslationType tranType);
170
171    Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
172                      Mode mode, Translation *translation, bool timing,
173                      bool functional, TlbEntry *mergeTe);
174
175    Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
176    Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
177                             ThreadContext *tc);
178
179
180    /** Reset the entire TLB
181     * @param secure_lookup if the operation affects the secure world
182     */
183    void flushAllSecurity(bool secure_lookup, uint8_t target_el,
184                          bool ignore_el = false);
185
186    /** Remove all entries in the non secure world, depending on whether they
187     *  were allocated in hyp mode or not
188     * @param hyp if the opperation affects hyp mode
189     */
190    void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
191
192
193    /** Reset the entire TLB. Used for CPU switching to prevent stale
194     * translations after multiple switches
195     */
196    void flushAll()
197    {
198        flushAllSecurity(false, 0, true);
199        flushAllSecurity(true, 0, true);
200    }
201
202    /** Remove any entries that match both a va and asn
203     * @param mva virtual address to flush
204     * @param asn contextid/asn to flush on match
205     * @param secure_lookup if the operation affects the secure world
206     */
207    void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
208                      uint8_t target_el);
209
210    /** Remove any entries that match the asn
211     * @param asn contextid/asn to flush on match
212     * @param secure_lookup if the operation affects the secure world
213     */
214    void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
215
216    /** Remove all entries that match the va regardless of asn
217     * @param mva address to flush from cache
218     * @param secure_lookup if the operation affects the secure world
219     * @param hyp if the operation affects hyp mode
220     */
221    void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
222
223    Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
224    Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
225            bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
226
227    void printTlb() const;
228
229    void allCpusCaching() { bootUncacheability = true; }
230    void demapPage(Addr vaddr, uint64_t asn)
231    {
232        // needed for x86 only
233        panic("demapPage() is not implemented.\n");
234    }
235
236    static bool validVirtualAddress(Addr vaddr);
237
238    /**
239     * Do a functional lookup on the TLB (for debugging)
240     * and don't modify any internal state
241     * @param tc thread context to get the context id from
242     * @param vaddr virtual address to translate
243     * @param pa returned physical address
244     * @return if the translation was successful
245     */
246    bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
247
248    /**
249     * Do a functional lookup on the TLB (for checker cpu) that
250     * behaves like a normal lookup without modifying any page table state.
251     */
252    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
253            ArmTranslationType tranType = NormalTran);
254
255    /** Accessor functions for memory attributes for last accessed TLB entry
256     */
257    void
258    setAttr(uint64_t attr)
259    {
260        _attr = attr;
261    }
262
263    uint64_t
264    getAttr() const
265    {
266        return _attr;
267    }
268
269    Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
270            Translation *translation, bool &delay,
271            bool timing, ArmTranslationType tranType, bool functional = false);
272    Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
273            Translation *translation, bool &delay, bool timing);
274    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
275            ArmTranslationType tranType = NormalTran);
276    Fault translateTiming(RequestPtr req, ThreadContext *tc,
277            Translation *translation, Mode mode,
278            ArmTranslationType tranType = NormalTran);
279    Fault translateComplete(RequestPtr req, ThreadContext *tc,
280            Translation *translation, Mode mode, ArmTranslationType tranType,
281            bool callFromS2);
282    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
283
284    void drainResume();
285
286    // Checkpointing
287    void serialize(std::ostream &os);
288    void unserialize(Checkpoint *cp, const std::string &section);
289
290    void regStats();
291
292    /**
293     * Get the table walker master port. This is used for migrating
294     * port connections during a CPU takeOverFrom() call. For
295     * architectures that do not have a table walker, NULL is
296     * returned, hence the use of a pointer rather than a
297     * reference. For ARM this method will always return a valid port
298     * pointer.
299     *
300     * @return A pointer to the walker master port
301     */
302    virtual BaseMasterPort* getMasterPort();
303
304    /**
305     * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
306     * access the table walker port of this TLB so that it can
307     * orchestrate staged translations.
308     *
309     * @return The table walker DMA port
310     */
311    DmaPort& getWalkerPort();
312
313    // Caching misc register values here.
314    // Writing to misc registers needs to invalidate them.
315    // translateFunctional/translateSe/translateFs checks if they are
316    // invalid and call updateMiscReg if necessary.
317protected:
318    bool aarch64;
319    ExceptionLevel aarch64EL;
320    SCTLR sctlr;
321    SCR scr;
322    bool isPriv;
323    bool isSecure;
324    bool isHyp;
325    TTBCR ttbcr;
326    uint16_t asid;
327    uint8_t vmid;
328    PRRR prrr;
329    NMRR nmrr;
330    HCR hcr;
331    uint32_t dacr;
332    bool miscRegValid;
333    ArmTranslationType curTranType;
334
335    // Cached copies of system-level properties
336    bool haveLPAE;
337    bool haveVirtualization;
338    bool haveLargeAsid64;
339
340    void updateMiscReg(ThreadContext *tc,
341                       ArmTranslationType tranType = NormalTran);
342
343public:
344    const Params *
345    params() const
346    {
347        return dynamic_cast<const Params *>(_params);
348    }
349    inline void invalidateMiscReg() { miscRegValid = false; }
350
351private:
352    /** Remove any entries that match both a va and asn
353     * @param mva virtual address to flush
354     * @param asn contextid/asn to flush on match
355     * @param secure_lookup if the operation affects the secure world
356     * @param hyp if the operation affects hyp mode
357     * @param ignore_asn if the flush should ignore the asn
358     */
359    void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
360                   bool hyp, bool ignore_asn, uint8_t target_el);
361
362    bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
363};
364
365} // namespace ArmISA
366
367#endif // __ARCH_ARM_TLB_HH__
368