tlb.hh revision 13374
113531Sjairo.balart@metempsy.com/* 214167Sgiacomo.travaglini@arm.com * Copyright (c) 2010-2013, 2016, 2018 ARM Limited 314167Sgiacomo.travaglini@arm.com * All rights reserved 414167Sgiacomo.travaglini@arm.com * 514167Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 614167Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 714167Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 814167Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 914167Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1014167Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1114167Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1214167Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1314167Sgiacomo.travaglini@arm.com * 1413531Sjairo.balart@metempsy.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 1513531Sjairo.balart@metempsy.com * All rights reserved. 1613531Sjairo.balart@metempsy.com * 1713531Sjairo.balart@metempsy.com * Redistribution and use in source and binary forms, with or without 1813531Sjairo.balart@metempsy.com * modification, are permitted provided that the following conditions are 1913531Sjairo.balart@metempsy.com * met: redistributions of source code must retain the above copyright 2013531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer; 2113531Sjairo.balart@metempsy.com * redistributions in binary form must reproduce the above copyright 2213531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer in the 2313531Sjairo.balart@metempsy.com * documentation and/or other materials provided with the distribution; 2413531Sjairo.balart@metempsy.com * neither the name of the copyright holders nor the names of its 2513531Sjairo.balart@metempsy.com * contributors may be used to endorse or promote products derived from 2613531Sjairo.balart@metempsy.com * this software without specific prior written permission. 2713531Sjairo.balart@metempsy.com * 2813531Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2913531Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3013531Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3113531Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3213531Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3313531Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3413531Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3513531Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3613531Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3713531Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3813531Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3913531Sjairo.balart@metempsy.com * 4013531Sjairo.balart@metempsy.com * Authors: Ali Saidi 4113531Sjairo.balart@metempsy.com */ 4213756Sjairo.balart@metempsy.com 4313531Sjairo.balart@metempsy.com#ifndef __ARCH_ARM_TLB_HH__ 4413531Sjairo.balart@metempsy.com#define __ARCH_ARM_TLB_HH__ 4513531Sjairo.balart@metempsy.com 4613531Sjairo.balart@metempsy.com 4714257Sgiacomo.travaglini@arm.com#include "arch/arm/isa_traits.hh" 4813531Sjairo.balart@metempsy.com#include "arch/arm/pagetable.hh" 4913531Sjairo.balart@metempsy.com#include "arch/arm/utility.hh" 5013531Sjairo.balart@metempsy.com#include "arch/arm/vtophys.hh" 5113531Sjairo.balart@metempsy.com#include "arch/generic/tlb.hh" 5213531Sjairo.balart@metempsy.com#include "base/statistics.hh" 5313756Sjairo.balart@metempsy.com#include "mem/request.hh" 5413756Sjairo.balart@metempsy.com#include "params/ArmTLB.hh" 5513756Sjairo.balart@metempsy.com#include "sim/probe/pmu.hh" 5613756Sjairo.balart@metempsy.com 5713756Sjairo.balart@metempsy.comclass ThreadContext; 5813756Sjairo.balart@metempsy.com 5913756Sjairo.balart@metempsy.comnamespace ArmISA { 6013531Sjairo.balart@metempsy.com 6113756Sjairo.balart@metempsy.comclass TableWalker; 6213756Sjairo.balart@metempsy.comclass Stage2LookUp; 6313756Sjairo.balart@metempsy.comclass Stage2MMU; 6413756Sjairo.balart@metempsy.comclass TLB; 6513756Sjairo.balart@metempsy.com 6613756Sjairo.balart@metempsy.comclass TlbTestInterface 6713756Sjairo.balart@metempsy.com{ 6813531Sjairo.balart@metempsy.com public: 6913531Sjairo.balart@metempsy.com TlbTestInterface() {} 7013531Sjairo.balart@metempsy.com virtual ~TlbTestInterface() {} 7113531Sjairo.balart@metempsy.com 7214258Sgiacomo.travaglini@arm.com /** 7314258Sgiacomo.travaglini@arm.com * Check if a TLB translation should be forced to fail. 7414258Sgiacomo.travaglini@arm.com * 7514258Sgiacomo.travaglini@arm.com * @param req Request requiring a translation. 7614258Sgiacomo.travaglini@arm.com * @param is_priv Access from a privileged mode (i.e., not EL0) 7714258Sgiacomo.travaglini@arm.com * @param mode Access type 7814258Sgiacomo.travaglini@arm.com * @param domain Domain type 7914258Sgiacomo.travaglini@arm.com */ 8014258Sgiacomo.travaglini@arm.com virtual Fault translationCheck(const RequestPtr &req, bool is_priv, 8114258Sgiacomo.travaglini@arm.com BaseTLB::Mode mode, 8214258Sgiacomo.travaglini@arm.com TlbEntry::DomainType domain) = 0; 8314258Sgiacomo.travaglini@arm.com 8414258Sgiacomo.travaglini@arm.com /** 8514257Sgiacomo.travaglini@arm.com * Check if a page table walker access should be forced to fail. 8614167Sgiacomo.travaglini@arm.com * 8714167Sgiacomo.travaglini@arm.com * @param pa Physical address the walker is accessing 8814167Sgiacomo.travaglini@arm.com * @param size Walker access size 8914167Sgiacomo.travaglini@arm.com * @param va Virtual address that initiated the walk 9014167Sgiacomo.travaglini@arm.com * @param is_secure Access from secure state 9113531Sjairo.balart@metempsy.com * @param is_priv Access from a privileged mode (i.e., not EL0) 9213531Sjairo.balart@metempsy.com * @param mode Access type 9314257Sgiacomo.travaglini@arm.com * @param domain Domain type 9414257Sgiacomo.travaglini@arm.com * @param lookup_level Page table walker level 9514257Sgiacomo.travaglini@arm.com */ 9614257Sgiacomo.travaglini@arm.com virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure, 9714257Sgiacomo.travaglini@arm.com Addr is_priv, BaseTLB::Mode mode, 9814257Sgiacomo.travaglini@arm.com TlbEntry::DomainType domain, 9914257Sgiacomo.travaglini@arm.com LookupLevel lookup_level) = 0; 10014257Sgiacomo.travaglini@arm.com}; 10114257Sgiacomo.travaglini@arm.com 10214257Sgiacomo.travaglini@arm.comclass TLB : public BaseTLB 10314257Sgiacomo.travaglini@arm.com{ 10414257Sgiacomo.travaglini@arm.com public: 10514257Sgiacomo.travaglini@arm.com enum ArmFlags { 10614257Sgiacomo.travaglini@arm.com AlignmentMask = 0x7, 10714257Sgiacomo.travaglini@arm.com 10814257Sgiacomo.travaglini@arm.com AlignByte = 0x0, 10914257Sgiacomo.travaglini@arm.com AlignHalfWord = 0x1, 11014257Sgiacomo.travaglini@arm.com AlignWord = 0x2, 11114257Sgiacomo.travaglini@arm.com AlignDoubleWord = 0x3, 11214257Sgiacomo.travaglini@arm.com AlignQuadWord = 0x4, 11314257Sgiacomo.travaglini@arm.com AlignOctWord = 0x5, 11414257Sgiacomo.travaglini@arm.com 11514257Sgiacomo.travaglini@arm.com AllowUnaligned = 0x8, 11614257Sgiacomo.travaglini@arm.com // Priv code operating as if it wasn't 11714257Sgiacomo.travaglini@arm.com UserMode = 0x10, 11814257Sgiacomo.travaglini@arm.com // Because zero otherwise looks like a valid setting and may be used 11914257Sgiacomo.travaglini@arm.com // accidentally, this bit must be non-zero to show it was used on 12014257Sgiacomo.travaglini@arm.com // purpose. 12114257Sgiacomo.travaglini@arm.com MustBeOne = 0x40 12214257Sgiacomo.travaglini@arm.com }; 12314257Sgiacomo.travaglini@arm.com 12413531Sjairo.balart@metempsy.com enum ArmTranslationType { 12513531Sjairo.balart@metempsy.com NormalTran = 0, 12613531Sjairo.balart@metempsy.com S1CTran = 0x1, 12713531Sjairo.balart@metempsy.com HypMode = 0x2, 12813531Sjairo.balart@metempsy.com // Secure code operating as if it wasn't (required by some Address 12913531Sjairo.balart@metempsy.com // Translate operations) 13014258Sgiacomo.travaglini@arm.com S1S2NsTran = 0x4, 13113531Sjairo.balart@metempsy.com // Address translation instructions (eg AT S1E0R_Xt) need to be handled 13214258Sgiacomo.travaglini@arm.com // in special ways during translation because they could need to act 13314258Sgiacomo.travaglini@arm.com // like a different EL than the current EL. The following flags are 13414258Sgiacomo.travaglini@arm.com // for these instructions 13513531Sjairo.balart@metempsy.com S1E0Tran = 0x8, 13613531Sjairo.balart@metempsy.com S1E1Tran = 0x10, 13713531Sjairo.balart@metempsy.com S1E2Tran = 0x20, 13813531Sjairo.balart@metempsy.com S1E3Tran = 0x40, 13913531Sjairo.balart@metempsy.com S12E0Tran = 0x80, 14013531Sjairo.balart@metempsy.com S12E1Tran = 0x100 14113531Sjairo.balart@metempsy.com }; 14213531Sjairo.balart@metempsy.com 14313531Sjairo.balart@metempsy.com /** 14413531Sjairo.balart@metempsy.com * Determine the EL to use for the purpose of a translation given 14513531Sjairo.balart@metempsy.com * a specific translation type. If the translation type doesn't 14613531Sjairo.balart@metempsy.com * specify an EL, we use the current EL. 14713531Sjairo.balart@metempsy.com */ 14813531Sjairo.balart@metempsy.com static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type); 14913531Sjairo.balart@metempsy.com 15013531Sjairo.balart@metempsy.com protected: 15113531Sjairo.balart@metempsy.com TlbEntry* table; // the Page Table 15213531Sjairo.balart@metempsy.com int size; // TLB Size 15313531Sjairo.balart@metempsy.com bool isStage2; // Indicates this TLB is part of the second stage MMU 15413531Sjairo.balart@metempsy.com bool stage2Req; // Indicates whether a stage 2 lookup is also required 15513756Sjairo.balart@metempsy.com // Indicates whether a stage 2 lookup of the table descriptors is required. 15613531Sjairo.balart@metempsy.com // Certain address translation instructions will intercept the IPA but the 15713531Sjairo.balart@metempsy.com // table descriptors still need to be translated by the stage2. 15813531Sjairo.balart@metempsy.com bool stage2DescReq; 15913531Sjairo.balart@metempsy.com uint64_t _attr; // Memory attributes for last accessed TLB entry 16013756Sjairo.balart@metempsy.com bool directToStage2; // Indicates whether all translation requests should 16113531Sjairo.balart@metempsy.com // be routed directly to the stage 2 TLB 16213531Sjairo.balart@metempsy.com 16313531Sjairo.balart@metempsy.com TableWalker *tableWalker; 16413531Sjairo.balart@metempsy.com TLB *stage2Tlb; 16513531Sjairo.balart@metempsy.com Stage2MMU *stage2Mmu; 16613531Sjairo.balart@metempsy.com 16713531Sjairo.balart@metempsy.com TlbTestInterface *test; 16813531Sjairo.balart@metempsy.com 16913531Sjairo.balart@metempsy.com // Access Stats 17013756Sjairo.balart@metempsy.com mutable Stats::Scalar instHits; 17113756Sjairo.balart@metempsy.com mutable Stats::Scalar instMisses; 17213531Sjairo.balart@metempsy.com mutable Stats::Scalar readHits; 17313531Sjairo.balart@metempsy.com mutable Stats::Scalar readMisses; 17413531Sjairo.balart@metempsy.com mutable Stats::Scalar writeHits; 17513531Sjairo.balart@metempsy.com mutable Stats::Scalar writeMisses; 17613531Sjairo.balart@metempsy.com mutable Stats::Scalar inserts; 17713531Sjairo.balart@metempsy.com mutable Stats::Scalar flushTlb; 17813531Sjairo.balart@metempsy.com mutable Stats::Scalar flushTlbMva; 17913531Sjairo.balart@metempsy.com mutable Stats::Scalar flushTlbMvaAsid; 18013531Sjairo.balart@metempsy.com mutable Stats::Scalar flushTlbAsid; 18113531Sjairo.balart@metempsy.com mutable Stats::Scalar flushedEntries; 18213531Sjairo.balart@metempsy.com mutable Stats::Scalar alignFaults; 18313531Sjairo.balart@metempsy.com mutable Stats::Scalar prefetchFaults; 18413531Sjairo.balart@metempsy.com mutable Stats::Scalar domainFaults; 18513531Sjairo.balart@metempsy.com mutable Stats::Scalar permsFaults; 18613531Sjairo.balart@metempsy.com 18713531Sjairo.balart@metempsy.com Stats::Formula readAccesses; 18813531Sjairo.balart@metempsy.com Stats::Formula writeAccesses; 18913531Sjairo.balart@metempsy.com Stats::Formula instAccesses; 19013531Sjairo.balart@metempsy.com Stats::Formula hits; 19113756Sjairo.balart@metempsy.com Stats::Formula misses; 19213756Sjairo.balart@metempsy.com Stats::Formula accesses; 19313531Sjairo.balart@metempsy.com 19413531Sjairo.balart@metempsy.com /** PMU probe for TLB refills */ 19513531Sjairo.balart@metempsy.com ProbePoints::PMUUPtr ppRefills; 19613531Sjairo.balart@metempsy.com 19713531Sjairo.balart@metempsy.com int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU 19813531Sjairo.balart@metempsy.com 19913531Sjairo.balart@metempsy.com public: 20013531Sjairo.balart@metempsy.com TLB(const ArmTLBParams *p); 20113531Sjairo.balart@metempsy.com TLB(const Params *p, int _size, TableWalker *_walker); 20213531Sjairo.balart@metempsy.com 20313756Sjairo.balart@metempsy.com /** Lookup an entry in the TLB 20413531Sjairo.balart@metempsy.com * @param vpn virtual address 20513531Sjairo.balart@metempsy.com * @param asn context id/address space id to use 20613531Sjairo.balart@metempsy.com * @param vmid The virtual machine ID used for stage 2 translation 20713531Sjairo.balart@metempsy.com * @param secure if the lookup is secure 20813531Sjairo.balart@metempsy.com * @param hyp if the lookup is done from hyp mode 20913531Sjairo.balart@metempsy.com * @param functional if the lookup should modify state 21013531Sjairo.balart@metempsy.com * @param ignore_asn if on lookup asn should be ignored 21113531Sjairo.balart@metempsy.com * @return pointer to TLB entry if it exists 21213756Sjairo.balart@metempsy.com */ 21313756Sjairo.balart@metempsy.com TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, 21413531Sjairo.balart@metempsy.com bool secure, bool functional, 21513531Sjairo.balart@metempsy.com bool ignore_asn, uint8_t target_el); 21613531Sjairo.balart@metempsy.com 21713531Sjairo.balart@metempsy.com virtual ~TLB(); 21813531Sjairo.balart@metempsy.com 21913531Sjairo.balart@metempsy.com void takeOverFrom(BaseTLB *otlb) override; 22013531Sjairo.balart@metempsy.com 22113531Sjairo.balart@metempsy.com /// setup all the back pointers 22213531Sjairo.balart@metempsy.com void init() override; 22313531Sjairo.balart@metempsy.com 22413531Sjairo.balart@metempsy.com void setTestInterface(SimObject *ti); 22513531Sjairo.balart@metempsy.com 22613531Sjairo.balart@metempsy.com TableWalker *getTableWalker() { return tableWalker; } 22713756Sjairo.balart@metempsy.com 22813531Sjairo.balart@metempsy.com void setMMU(Stage2MMU *m, MasterID master_id); 22913531Sjairo.balart@metempsy.com 23013531Sjairo.balart@metempsy.com int getsize() const { return size; } 23113531Sjairo.balart@metempsy.com 23213531Sjairo.balart@metempsy.com void insert(Addr vaddr, TlbEntry &pte); 23313531Sjairo.balart@metempsy.com 23413531Sjairo.balart@metempsy.com Fault getTE(TlbEntry **te, const RequestPtr &req, 23513531Sjairo.balart@metempsy.com ThreadContext *tc, Mode mode, 23613756Sjairo.balart@metempsy.com Translation *translation, bool timing, bool functional, 23713756Sjairo.balart@metempsy.com bool is_secure, ArmTranslationType tranType); 23813531Sjairo.balart@metempsy.com 23913531Sjairo.balart@metempsy.com Fault getResultTe(TlbEntry **te, const RequestPtr &req, 24013531Sjairo.balart@metempsy.com ThreadContext *tc, Mode mode, 24113531Sjairo.balart@metempsy.com Translation *translation, bool timing, 24213531Sjairo.balart@metempsy.com bool functional, TlbEntry *mergeTe); 24313531Sjairo.balart@metempsy.com 24413531Sjairo.balart@metempsy.com Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode); 24513531Sjairo.balart@metempsy.com Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, 24613531Sjairo.balart@metempsy.com ThreadContext *tc); 24713531Sjairo.balart@metempsy.com 24813531Sjairo.balart@metempsy.com 24913531Sjairo.balart@metempsy.com /** Reset the entire TLB 25013756Sjairo.balart@metempsy.com * @param secure_lookup if the operation affects the secure world 25113531Sjairo.balart@metempsy.com */ 25213531Sjairo.balart@metempsy.com void flushAllSecurity(bool secure_lookup, uint8_t target_el, 25313531Sjairo.balart@metempsy.com bool ignore_el = false); 25413531Sjairo.balart@metempsy.com 25513531Sjairo.balart@metempsy.com /** Remove all entries in the non secure world, depending on whether they 25613531Sjairo.balart@metempsy.com * were allocated in hyp mode or not 25713531Sjairo.balart@metempsy.com * @param hyp if the opperation affects hyp mode 25813531Sjairo.balart@metempsy.com */ 25913531Sjairo.balart@metempsy.com void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false); 26013531Sjairo.balart@metempsy.com 26113756Sjairo.balart@metempsy.com 26213756Sjairo.balart@metempsy.com /** Reset the entire TLB. Used for CPU switching to prevent stale 26313531Sjairo.balart@metempsy.com * translations after multiple switches 26413531Sjairo.balart@metempsy.com */ 26513531Sjairo.balart@metempsy.com void flushAll() override 26613531Sjairo.balart@metempsy.com { 26713531Sjairo.balart@metempsy.com flushAllSecurity(false, 0, true); 26813531Sjairo.balart@metempsy.com flushAllSecurity(true, 0, true); 26913531Sjairo.balart@metempsy.com } 27013531Sjairo.balart@metempsy.com 27113531Sjairo.balart@metempsy.com /** Remove any entries that match both a va and asn 27213531Sjairo.balart@metempsy.com * @param mva virtual address to flush 27313531Sjairo.balart@metempsy.com * @param asn contextid/asn to flush on match 27413531Sjairo.balart@metempsy.com * @param secure_lookup if the operation affects the secure world 27513756Sjairo.balart@metempsy.com */ 27613531Sjairo.balart@metempsy.com void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, 27713531Sjairo.balart@metempsy.com uint8_t target_el); 27813531Sjairo.balart@metempsy.com 27913531Sjairo.balart@metempsy.com /** Remove any entries that match the asn 28013531Sjairo.balart@metempsy.com * @param asn contextid/asn to flush on match 28113531Sjairo.balart@metempsy.com * @param secure_lookup if the operation affects the secure world 28213531Sjairo.balart@metempsy.com */ 28313531Sjairo.balart@metempsy.com void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el); 28413531Sjairo.balart@metempsy.com 28513531Sjairo.balart@metempsy.com /** Remove all entries that match the va regardless of asn 28613756Sjairo.balart@metempsy.com * @param mva address to flush from cache 28713756Sjairo.balart@metempsy.com * @param secure_lookup if the operation affects the secure world 28813531Sjairo.balart@metempsy.com * @param hyp if the operation affects hyp mode 28913531Sjairo.balart@metempsy.com */ 29013531Sjairo.balart@metempsy.com void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); 29113531Sjairo.balart@metempsy.com 29213531Sjairo.balart@metempsy.com /** 29313531Sjairo.balart@metempsy.com * Invalidate all entries in the stage 2 TLB that match the given ipa 29413531Sjairo.balart@metempsy.com * and the current VMID 29513531Sjairo.balart@metempsy.com * @param ipa the address to invalidate 29613531Sjairo.balart@metempsy.com * @param secure_lookup if the operation affects the secure world 29713531Sjairo.balart@metempsy.com * @param hyp if the operation affects hyp mode 29813531Sjairo.balart@metempsy.com */ 29913756Sjairo.balart@metempsy.com void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el); 30013531Sjairo.balart@metempsy.com 30113531Sjairo.balart@metempsy.com Fault trickBoxCheck(const RequestPtr &req, Mode mode, 30213531Sjairo.balart@metempsy.com TlbEntry::DomainType domain); 30313531Sjairo.balart@metempsy.com 30413531Sjairo.balart@metempsy.com Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, 30513531Sjairo.balart@metempsy.com bool is_exec, bool is_write, 30613531Sjairo.balart@metempsy.com TlbEntry::DomainType domain, 30713531Sjairo.balart@metempsy.com LookupLevel lookup_level); 30813531Sjairo.balart@metempsy.com 30913756Sjairo.balart@metempsy.com void printTlb() const; 31013756Sjairo.balart@metempsy.com 31113531Sjairo.balart@metempsy.com void demapPage(Addr vaddr, uint64_t asn) override 31213531Sjairo.balart@metempsy.com { 31313531Sjairo.balart@metempsy.com // needed for x86 only 31413531Sjairo.balart@metempsy.com panic("demapPage() is not implemented.\n"); 31513531Sjairo.balart@metempsy.com } 31613531Sjairo.balart@metempsy.com 31713531Sjairo.balart@metempsy.com /** 31813531Sjairo.balart@metempsy.com * Do a functional lookup on the TLB (for debugging) 31913531Sjairo.balart@metempsy.com * and don't modify any internal state 32013531Sjairo.balart@metempsy.com * @param tc thread context to get the context id from 32113531Sjairo.balart@metempsy.com * @param vaddr virtual address to translate 32213531Sjairo.balart@metempsy.com * @param pa returned physical address 32313531Sjairo.balart@metempsy.com * @return if the translation was successful 32413531Sjairo.balart@metempsy.com */ 32513531Sjairo.balart@metempsy.com bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); 32613531Sjairo.balart@metempsy.com 32713531Sjairo.balart@metempsy.com /** 32813531Sjairo.balart@metempsy.com * Do a functional lookup on the TLB (for checker cpu) that 32913531Sjairo.balart@metempsy.com * behaves like a normal lookup without modifying any page table state. 33013531Sjairo.balart@metempsy.com */ 33113531Sjairo.balart@metempsy.com Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, 33213531Sjairo.balart@metempsy.com Mode mode, ArmTranslationType tranType); 33313756Sjairo.balart@metempsy.com Fault 33413531Sjairo.balart@metempsy.com translateFunctional(const RequestPtr &req, 33513531Sjairo.balart@metempsy.com ThreadContext *tc, Mode mode) override 33613531Sjairo.balart@metempsy.com { 33713531Sjairo.balart@metempsy.com return translateFunctional(req, tc, mode, NormalTran); 33813531Sjairo.balart@metempsy.com } 33913531Sjairo.balart@metempsy.com 34013531Sjairo.balart@metempsy.com /** Accessor functions for memory attributes for last accessed TLB entry 34113531Sjairo.balart@metempsy.com */ 34213531Sjairo.balart@metempsy.com void 34313531Sjairo.balart@metempsy.com setAttr(uint64_t attr) 34413756Sjairo.balart@metempsy.com { 34513756Sjairo.balart@metempsy.com _attr = attr; 34613531Sjairo.balart@metempsy.com } 34713531Sjairo.balart@metempsy.com 34813531Sjairo.balart@metempsy.com uint64_t 34913531Sjairo.balart@metempsy.com getAttr() const 35013531Sjairo.balart@metempsy.com { 35113531Sjairo.balart@metempsy.com return _attr; 35213531Sjairo.balart@metempsy.com } 35313531Sjairo.balart@metempsy.com 35413531Sjairo.balart@metempsy.com Fault translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, 35513531Sjairo.balart@metempsy.com Translation *translation, bool &delay, 35613531Sjairo.balart@metempsy.com bool timing, ArmTranslationType tranType, bool functional = false); 35713531Sjairo.balart@metempsy.com Fault translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, 35813531Sjairo.balart@metempsy.com Translation *translation, bool &delay, bool timing); 35913531Sjairo.balart@metempsy.com Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, 36013531Sjairo.balart@metempsy.com ArmTranslationType tranType); 36113531Sjairo.balart@metempsy.com Fault 36213531Sjairo.balart@metempsy.com translateAtomic(const RequestPtr &req, 36313531Sjairo.balart@metempsy.com ThreadContext *tc, Mode mode) override 36413531Sjairo.balart@metempsy.com { 36513531Sjairo.balart@metempsy.com return translateAtomic(req, tc, mode, NormalTran); 36613531Sjairo.balart@metempsy.com } 36713531Sjairo.balart@metempsy.com void translateTiming( 36813531Sjairo.balart@metempsy.com const RequestPtr &req, ThreadContext *tc, 36913531Sjairo.balart@metempsy.com Translation *translation, Mode mode, 37013531Sjairo.balart@metempsy.com ArmTranslationType tranType); 37113531Sjairo.balart@metempsy.com void 37213531Sjairo.balart@metempsy.com translateTiming(const RequestPtr &req, ThreadContext *tc, 37313531Sjairo.balart@metempsy.com Translation *translation, Mode mode) override 37413531Sjairo.balart@metempsy.com { 37513531Sjairo.balart@metempsy.com translateTiming(req, tc, translation, mode, NormalTran); 37613756Sjairo.balart@metempsy.com } 37713531Sjairo.balart@metempsy.com Fault translateComplete(const RequestPtr &req, ThreadContext *tc, 37813531Sjairo.balart@metempsy.com Translation *translation, Mode mode, ArmTranslationType tranType, 37913531Sjairo.balart@metempsy.com bool callFromS2); 38013531Sjairo.balart@metempsy.com Fault finalizePhysical( 38113531Sjairo.balart@metempsy.com const RequestPtr &req, 38213531Sjairo.balart@metempsy.com ThreadContext *tc, Mode mode) const override; 38313756Sjairo.balart@metempsy.com 38413531Sjairo.balart@metempsy.com void drainResume() override; 38513531Sjairo.balart@metempsy.com 38613531Sjairo.balart@metempsy.com // Checkpointing 38713531Sjairo.balart@metempsy.com void serialize(CheckpointOut &cp) const override; 38813531Sjairo.balart@metempsy.com void unserialize(CheckpointIn &cp) override; 38913531Sjairo.balart@metempsy.com 39013531Sjairo.balart@metempsy.com void regStats() override; 39113531Sjairo.balart@metempsy.com 39213531Sjairo.balart@metempsy.com void regProbePoints() override; 39313531Sjairo.balart@metempsy.com 39413531Sjairo.balart@metempsy.com /** 39513531Sjairo.balart@metempsy.com * Get the table walker master port. This is used for migrating 39613531Sjairo.balart@metempsy.com * port connections during a CPU takeOverFrom() call. For 39713531Sjairo.balart@metempsy.com * architectures that do not have a table walker, NULL is 39813531Sjairo.balart@metempsy.com * returned, hence the use of a pointer rather than a 39913756Sjairo.balart@metempsy.com * reference. For ARM this method will always return a valid port 40013531Sjairo.balart@metempsy.com * pointer. 40113531Sjairo.balart@metempsy.com * 40213531Sjairo.balart@metempsy.com * @return A pointer to the walker master port 40313531Sjairo.balart@metempsy.com */ 40413531Sjairo.balart@metempsy.com BaseMasterPort* getMasterPort() override; 40513531Sjairo.balart@metempsy.com 40613531Sjairo.balart@metempsy.com // Caching misc register values here. 40713531Sjairo.balart@metempsy.com // Writing to misc registers needs to invalidate them. 40813531Sjairo.balart@metempsy.com // translateFunctional/translateSe/translateFs checks if they are 40913531Sjairo.balart@metempsy.com // invalid and call updateMiscReg if necessary. 41013531Sjairo.balart@metempsy.comprotected: 41113531Sjairo.balart@metempsy.com CPSR cpsr; 41213531Sjairo.balart@metempsy.com bool aarch64; 41313531Sjairo.balart@metempsy.com ExceptionLevel aarch64EL; 41413531Sjairo.balart@metempsy.com SCTLR sctlr; 41513531Sjairo.balart@metempsy.com SCR scr; 41613531Sjairo.balart@metempsy.com bool isPriv; 41713531Sjairo.balart@metempsy.com bool isSecure; 41813531Sjairo.balart@metempsy.com bool isHyp; 41913531Sjairo.balart@metempsy.com TTBCR ttbcr; 42013531Sjairo.balart@metempsy.com uint16_t asid; 42113531Sjairo.balart@metempsy.com uint8_t vmid; 42213531Sjairo.balart@metempsy.com PRRR prrr; 42313531Sjairo.balart@metempsy.com NMRR nmrr; 42413531Sjairo.balart@metempsy.com HCR hcr; 42513531Sjairo.balart@metempsy.com uint32_t dacr; 42613531Sjairo.balart@metempsy.com bool miscRegValid; 42713531Sjairo.balart@metempsy.com ContextID miscRegContext; 42813531Sjairo.balart@metempsy.com ArmTranslationType curTranType; 42913531Sjairo.balart@metempsy.com 43013531Sjairo.balart@metempsy.com // Cached copies of system-level properties 43113531Sjairo.balart@metempsy.com bool haveLPAE; 43213531Sjairo.balart@metempsy.com bool haveVirtualization; 43313531Sjairo.balart@metempsy.com bool haveLargeAsid64; 43413531Sjairo.balart@metempsy.com 43513531Sjairo.balart@metempsy.com AddrRange m5opRange; 43613531Sjairo.balart@metempsy.com 43713531Sjairo.balart@metempsy.com void updateMiscReg(ThreadContext *tc, 43813531Sjairo.balart@metempsy.com ArmTranslationType tranType = NormalTran); 43913531Sjairo.balart@metempsy.com 44013531Sjairo.balart@metempsy.compublic: 44113531Sjairo.balart@metempsy.com const Params * 44213531Sjairo.balart@metempsy.com params() const 44313531Sjairo.balart@metempsy.com { 44413531Sjairo.balart@metempsy.com return dynamic_cast<const Params *>(_params); 44513531Sjairo.balart@metempsy.com } 44613531Sjairo.balart@metempsy.com inline void invalidateMiscReg() { miscRegValid = false; } 44713531Sjairo.balart@metempsy.com 44813531Sjairo.balart@metempsy.comprivate: 44913531Sjairo.balart@metempsy.com /** Remove any entries that match both a va and asn 45013531Sjairo.balart@metempsy.com * @param mva virtual address to flush 45113531Sjairo.balart@metempsy.com * @param asn contextid/asn to flush on match 45213531Sjairo.balart@metempsy.com * @param secure_lookup if the operation affects the secure world 45313531Sjairo.balart@metempsy.com * @param hyp if the operation affects hyp mode 45413531Sjairo.balart@metempsy.com * @param ignore_asn if the flush should ignore the asn 45513531Sjairo.balart@metempsy.com */ 45613531Sjairo.balart@metempsy.com void _flushMva(Addr mva, uint64_t asn, bool secure_lookup, 45713531Sjairo.balart@metempsy.com bool hyp, bool ignore_asn, uint8_t target_el); 45813531Sjairo.balart@metempsy.com 45913531Sjairo.balart@metempsy.com bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el); 46013531Sjairo.balart@metempsy.com 46113531Sjairo.balart@metempsy.com public: /* Testing */ 46213531Sjairo.balart@metempsy.com Fault testTranslation(const RequestPtr &req, Mode mode, 46313531Sjairo.balart@metempsy.com TlbEntry::DomainType domain); 46413531Sjairo.balart@metempsy.com Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, 46513531Sjairo.balart@metempsy.com TlbEntry::DomainType domain, 46613531Sjairo.balart@metempsy.com LookupLevel lookup_level); 46713531Sjairo.balart@metempsy.com}; 46813531Sjairo.balart@metempsy.com 46913531Sjairo.balart@metempsy.comtemplate<typename T> 47014257Sgiacomo.travaglini@arm.comTLB * 47113531Sjairo.balart@metempsy.comgetITBPtr(T *tc) 47213531Sjairo.balart@metempsy.com{ 47313531Sjairo.balart@metempsy.com auto tlb = static_cast<TLB *>(tc->getITBPtr()); 47413531Sjairo.balart@metempsy.com assert(tlb); 47513531Sjairo.balart@metempsy.com return tlb; 47613531Sjairo.balart@metempsy.com} 47713531Sjairo.balart@metempsy.com 47813531Sjairo.balart@metempsy.comtemplate<typename T> 47913531Sjairo.balart@metempsy.comTLB * 48013756Sjairo.balart@metempsy.comgetDTBPtr(T *tc) 48114167Sgiacomo.travaglini@arm.com{ 48213531Sjairo.balart@metempsy.com auto tlb = static_cast<TLB *>(tc->getDTBPtr()); 48314167Sgiacomo.travaglini@arm.com assert(tlb); 48414167Sgiacomo.travaglini@arm.com return tlb; 48513531Sjairo.balart@metempsy.com} 48614167Sgiacomo.travaglini@arm.com 48714167Sgiacomo.travaglini@arm.com} // namespace ArmISA 48813531Sjairo.balart@metempsy.com 48913531Sjairo.balart@metempsy.com#endif // __ARCH_ARM_TLB_HH__ 49014167Sgiacomo.travaglini@arm.com