tlb.cc revision 7694:de057cccee82
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Steve Reinhardt 43 */ 44 45#include <string> 46#include <vector> 47 48#include "arch/arm/faults.hh" 49#include "arch/arm/pagetable.hh" 50#include "arch/arm/tlb.hh" 51#include "arch/arm/utility.hh" 52#include "base/inifile.hh" 53#include "base/str.hh" 54#include "base/trace.hh" 55#include "cpu/thread_context.hh" 56#include "mem/page_table.hh" 57#include "params/ArmTLB.hh" 58#include "sim/process.hh" 59 60#if FULL_SYSTEM 61#include "arch/arm/table_walker.hh" 62#endif 63 64using namespace std; 65using namespace ArmISA; 66 67TLB::TLB(const Params *p) 68 : BaseTLB(p), size(p->size), nlu(0) 69#if FULL_SYSTEM 70 , tableWalker(p->walker) 71#endif 72{ 73 table = new TlbEntry[size]; 74 memset(table, 0, sizeof(TlbEntry[size])); 75 76#if FULL_SYSTEM 77 tableWalker->setTlb(this); 78#endif 79} 80 81TLB::~TLB() 82{ 83 if (table) 84 delete [] table; 85} 86 87bool 88TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 89{ 90 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 91 TlbEntry *e = lookup(va, context_id, true); 92 if (!e) 93 return false; 94 pa = e->pAddr(va); 95 return true; 96} 97 98TlbEntry* 99TLB::lookup(Addr va, uint8_t cid, bool functional) 100{ 101 // XXX This should either turn into a TlbMap or add caching 102 103 TlbEntry *retval = NULL; 104 105 // Do some kind of caching, fast indexing, anything 106 107 int x = 0; 108 while (retval == NULL && x < size) { 109 if (table[x].match(va, cid)) { 110 retval = &table[x]; 111 if (x == nlu && !functional) 112 nextnlu(); 113 114 break; 115 } 116 x++; 117 } 118 119 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 120 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 121 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 122 retval ? retval->ap : 0); 123 ; 124 return retval; 125} 126 127// insert a new TLB entry 128void 129TLB::insert(Addr addr, TlbEntry &entry) 130{ 131 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 132 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 133 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 134 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 135 entry.xn, entry.ap, entry.domain); 136 137 if (table[nlu].valid) 138 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 139 table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N, 140 table[nlu].size, table[nlu].ap); 141 142 // XXX Update caching, lookup table etc 143 table[nlu] = entry; 144 145 // XXX Figure out how entries are generally inserted in ARM 146 nextnlu(); 147} 148 149void 150TLB::printTlb() 151{ 152 int x = 0; 153 TlbEntry *te; 154 DPRINTF(TLB, "Current TLB contents:\n"); 155 while (x < size) { 156 te = &table[x]; 157 if (te->valid) 158 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 159 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 160 x++; 161 } 162} 163 164 165void 166TLB::flushAll() 167{ 168 DPRINTF(TLB, "Flushing all TLB entries\n"); 169 int x = 0; 170 TlbEntry *te; 171 while (x < size) { 172 te = &table[x]; 173 if (te->valid) 174 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 175 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 176 x++; 177 } 178 179 memset(table, 0, sizeof(TlbEntry[size])); 180 nlu = 0; 181} 182 183 184void 185TLB::flushMvaAsid(Addr mva, uint64_t asn) 186{ 187 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 188 TlbEntry *te; 189 190 te = lookup(mva, asn); 191 while (te != NULL) { 192 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 193 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 194 te->valid = false; 195 te = lookup(mva,asn); 196 } 197} 198 199void 200TLB::flushAsid(uint64_t asn) 201{ 202 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 203 204 int x = 0; 205 TlbEntry *te; 206 207 while (x < size) { 208 te = &table[x]; 209 if (te->asid == asn) { 210 te->valid = false; 211 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 212 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 213 } 214 x++; 215 } 216} 217 218void 219TLB::flushMva(Addr mva) 220{ 221 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 222 223 int x = 0; 224 TlbEntry *te; 225 226 while (x < size) { 227 te = &table[x]; 228 Addr v = te->vpn << te->N; 229 if (mva >= v && mva < v + te->size) { 230 te->valid = false; 231 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 232 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 233 } 234 x++; 235 } 236} 237 238void 239TLB::serialize(ostream &os) 240{ 241 panic("Implement Serialize\n"); 242} 243 244void 245TLB::unserialize(Checkpoint *cp, const string §ion) 246{ 247 248 panic("Need to properly unserialize TLB\n"); 249} 250 251void 252TLB::regStats() 253{ 254 read_hits 255 .name(name() + ".read_hits") 256 .desc("DTB read hits") 257 ; 258 259 read_misses 260 .name(name() + ".read_misses") 261 .desc("DTB read misses") 262 ; 263 264 265 read_accesses 266 .name(name() + ".read_accesses") 267 .desc("DTB read accesses") 268 ; 269 270 write_hits 271 .name(name() + ".write_hits") 272 .desc("DTB write hits") 273 ; 274 275 write_misses 276 .name(name() + ".write_misses") 277 .desc("DTB write misses") 278 ; 279 280 281 write_accesses 282 .name(name() + ".write_accesses") 283 .desc("DTB write accesses") 284 ; 285 286 hits 287 .name(name() + ".hits") 288 .desc("DTB hits") 289 ; 290 291 misses 292 .name(name() + ".misses") 293 .desc("DTB misses") 294 ; 295 296 accesses 297 .name(name() + ".accesses") 298 .desc("DTB accesses") 299 ; 300 301 hits = read_hits + write_hits; 302 misses = read_misses + write_misses; 303 accesses = read_accesses + write_accesses; 304} 305 306#if !FULL_SYSTEM 307Fault 308TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 309 Translation *translation, bool &delay, bool timing) 310{ 311 // XXX Cache misc registers and have miscreg write function inv cache 312 Addr vaddr = req->getVaddr() & ~PcModeMask; 313 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 314 uint32_t flags = req->getFlags(); 315 316 bool is_fetch = (mode == Execute); 317 bool is_write = (mode == Write); 318 319 if (!is_fetch) { 320 assert(flags & MustBeOne); 321 if (sctlr.a || !(flags & AllowUnaligned)) { 322 if (vaddr & flags & AlignmentMask) { 323 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 324 } 325 } 326 } 327 328 Addr paddr; 329 Process *p = tc->getProcessPtr(); 330 331 if (!p->pTable->translate(vaddr, paddr)) 332 return Fault(new GenericPageTableFault(vaddr)); 333 req->setPaddr(paddr); 334 335 return NoFault; 336} 337 338#else // FULL_SYSTEM 339 340Fault 341TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 342{ 343 return NoFault; 344} 345 346Fault 347TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 348 bool is_write, uint8_t domain, bool sNp) 349{ 350 return NoFault; 351} 352 353Fault 354TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 355 Translation *translation, bool &delay, bool timing) 356{ 357 // XXX Cache misc registers and have miscreg write function inv cache 358 Addr vaddr = req->getVaddr() & ~PcModeMask; 359 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 360 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 361 uint32_t flags = req->getFlags(); 362 363 bool is_fetch = (mode == Execute); 364 bool is_write = (mode == Write); 365 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode); 366 367 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags 368 & UserMode); 369 // If this is a clrex instruction, provide a PA of 0 with no fault 370 // This will force the monitor to set the tracked address to 0 371 // a bit of a hack but this effectively clrears this processors monitor 372 if (flags & Request::CLREX){ 373 req->setPaddr(0); 374 req->setFlags(Request::UNCACHEABLE); 375 req->setFlags(Request::CLREX); 376 return NoFault; 377 } 378 if ((req->isInstFetch() && (!sctlr.i)) || 379 ((!req->isInstFetch()) && (!sctlr.c))){ 380 req->setFlags(Request::UNCACHEABLE); 381 } 382 if (!is_fetch) { 383 assert(flags & MustBeOne); 384 if (sctlr.a || !(flags & AllowUnaligned)) { 385 if (vaddr & flags & AlignmentMask) { 386 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 387 } 388 } 389 } 390 391 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 392 Fault fault; 393 394 395 if (!sctlr.m) { 396 req->setPaddr(vaddr); 397 if (sctlr.tre == 0) { 398 req->setFlags(Request::UNCACHEABLE); 399 } else { 400 PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 401 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 402 403 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 404 req->setFlags(Request::UNCACHEABLE); 405 } 406 407 // Set memory attributes 408 TlbEntry temp_te; 409 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 410 temp_te.shareable = true; 411 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 412 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 413 temp_te.innerAttrs, temp_te.outerAttrs); 414 setAttr(temp_te.attributes); 415 416 return trickBoxCheck(req, mode, 0, false); 417 } 418 419 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 420 // Translation enabled 421 422 TlbEntry *te = lookup(vaddr, context_id); 423 if (te == NULL) { 424 if (req->isPrefetch()){ 425 //if the request is a prefetch don't attempt to fill the TLB 426 //or go any further with the memory access 427 return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 428 } 429 // start translation table walk, pass variables rather than 430 // re-retreaving in table walker for speed 431 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 432 vaddr, context_id); 433 fault = tableWalker->walk(req, tc, context_id, mode, translation, 434 timing); 435 if (timing) { 436 delay = true; 437 // for timing mode, return and wait for table walk 438 return fault; 439 } 440 if (fault) 441 return fault; 442 443 te = lookup(vaddr, context_id); 444 if (!te) 445 printTlb(); 446 assert(te); 447 } 448 449 // Set memory attributes 450 DPRINTF(TLBVerbose, 451 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 452 outerAttrs: %d\n", 453 te->shareable, te->innerAttrs, te->outerAttrs); 454 setAttr(te->attributes); 455 if (te->nonCacheable) 456 req->setFlags(Request::UNCACHEABLE); 457 uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 458 switch ( (dacr >> (te->domain * 2)) & 0x3) { 459 case 0: 460 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 461 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 462 if (is_fetch) 463 return new PrefetchAbort(vaddr, 464 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 465 else 466 return new DataAbort(vaddr, te->domain, is_write, 467 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 468 case 1: 469 // Continue with permissions check 470 break; 471 case 2: 472 panic("UNPRED domain\n"); 473 case 3: 474 req->setPaddr(te->pAddr(vaddr)); 475 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 476 if (fault) 477 return fault; 478 return NoFault; 479 } 480 481 uint8_t ap = te->ap; 482 483 if (sctlr.afe == 1) 484 ap |= 1; 485 486 bool abt; 487 488 /* if (!sctlr.xp) 489 ap &= 0x3; 490*/ 491 switch (ap) { 492 case 0: 493 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 494 if (!sctlr.xp) { 495 switch ((int)sctlr.rs) { 496 case 2: 497 abt = is_write; 498 break; 499 case 1: 500 abt = is_write || !is_priv; 501 break; 502 case 0: 503 case 3: 504 default: 505 abt = true; 506 break; 507 } 508 } else { 509 abt = true; 510 } 511 break; 512 case 1: 513 abt = !is_priv; 514 break; 515 case 2: 516 abt = !is_priv && is_write; 517 break; 518 case 3: 519 abt = false; 520 break; 521 case 4: 522 panic("UNPRED premissions\n"); 523 case 5: 524 abt = !is_priv || is_write; 525 break; 526 case 6: 527 case 7: 528 abt = is_write; 529 break; 530 default: 531 panic("Unknown permissions\n"); 532 } 533 if ((is_fetch) && (abt || te->xn)) { 534 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 535 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 536 return new PrefetchAbort(vaddr, 537 (te->sNp ? ArmFault::Permission0 : 538 ArmFault::Permission1)); 539 } else if (abt) { 540 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 541 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 542 return new DataAbort(vaddr, te->domain, is_write, 543 (te->sNp ? ArmFault::Permission0 : 544 ArmFault::Permission1)); 545 } 546 547 req->setPaddr(te->pAddr(vaddr)); 548 // Check for a trickbox generated address fault 549 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 550 if (fault) 551 return fault; 552 553 return NoFault; 554} 555 556#endif 557 558Fault 559TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 560{ 561 bool delay = false; 562 Fault fault; 563#if FULL_SYSTEM 564 fault = translateFs(req, tc, mode, NULL, delay, false); 565#else 566 fault = translateSe(req, tc, mode, NULL, delay, false); 567#endif 568 assert(!delay); 569 return fault; 570} 571 572Fault 573TLB::translateTiming(RequestPtr req, ThreadContext *tc, 574 Translation *translation, Mode mode) 575{ 576 assert(translation); 577 bool delay = false; 578 Fault fault; 579#if FULL_SYSTEM 580 fault = translateFs(req, tc, mode, translation, delay, true); 581#else 582 fault = translateSe(req, tc, mode, translation, delay, true); 583#endif 584 if (!delay) 585 translation->finish(fault, req, tc, mode); 586 return fault; 587} 588 589ArmISA::TLB * 590ArmTLBParams::create() 591{ 592 return new ArmISA::TLB(this); 593} 594