tlb.cc revision 7461:5a07045d0af2
12139SN/A/* 22139SN/A * Copyright (c) 2010 ARM Limited 32139SN/A * All rights reserved 42139SN/A * 52139SN/A * The license below extends only to copyright in the software and shall 62139SN/A * not be construed as granting a license to any other intellectual 72139SN/A * property including but not limited to intellectual property relating 82139SN/A * to a hardware implementation of the functionality of the software 92139SN/A * licensed hereunder. You may use the software subject to the license 102139SN/A * terms below provided that you ensure that this notice is replicated 112139SN/A * unmodified and in its entirety in all distributions of the software, 122139SN/A * modified or unmodified, in source code or in binary form. 132139SN/A * 142139SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 152139SN/A * All rights reserved. 162139SN/A * 172139SN/A * Redistribution and use in source and binary forms, with or without 182139SN/A * modification, are permitted provided that the following conditions are 192139SN/A * met: redistributions of source code must retain the above copyright 202139SN/A * notice, this list of conditions and the following disclaimer; 212139SN/A * redistributions in binary form must reproduce the above copyright 222139SN/A * notice, this list of conditions and the following disclaimer in the 232139SN/A * documentation and/or other materials provided with the distribution; 242139SN/A * neither the name of the copyright holders nor the names of its 252139SN/A * contributors may be used to endorse or promote products derived from 262139SN/A * this software without specific prior written permission. 272139SN/A * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302139SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314202Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322139SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334202Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342152SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352152SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362139SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372139SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382139SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392139SN/A * 402139SN/A * Authors: Ali Saidi 412152SN/A * Nathan Binkert 422152SN/A * Steve Reinhardt 432139SN/A */ 442139SN/A 452139SN/A#include <string> 464781Snate@binkert.org#include <vector> 474781Snate@binkert.org 487799Sgblack@eecs.umich.edu#include "arch/arm/faults.hh" 494781Snate@binkert.org#include "arch/arm/pagetable.hh" 504781Snate@binkert.org#include "arch/arm/tlb.hh" 513170Sstever@eecs.umich.edu#include "arch/arm/utility.hh" 525664Sgblack@eecs.umich.edu#include "base/inifile.hh" 538105Sgblack@eecs.umich.edu#include "base/str.hh" 546179Sksewell@umich.edu#include "base/trace.hh" 554781Snate@binkert.org#include "cpu/thread_context.hh" 564781Snate@binkert.org#include "mem/page_table.hh" 576329Sgblack@eecs.umich.edu#include "params/ArmTLB.hh" 584781Snate@binkert.org#include "sim/process.hh" 594781Snate@binkert.org 604781Snate@binkert.org#if FULL_SYSTEM 614781Snate@binkert.org#include "arch/arm/table_walker.hh" 624781Snate@binkert.org#endif 634781Snate@binkert.org 642139SN/Ausing namespace std; 652139SN/Ausing namespace ArmISA; 663546Sgblack@eecs.umich.edu 674202Sbinkertn@umich.eduTLB::TLB(const Params *p) 682152SN/A : BaseTLB(p), size(p->size), nlu(0) 692152SN/A#if FULL_SYSTEM 702152SN/A , tableWalker(p->walker) 712152SN/A#endif 722152SN/A{ 732152SN/A table = new TlbEntry[size]; 742152SN/A memset(table, 0, sizeof(TlbEntry[size])); 752152SN/A 762152SN/A#if FULL_SYSTEM 772152SN/A tableWalker->setTlb(this); 782152SN/A#endif 792152SN/A} 802504SN/A 812504SN/ATLB::~TLB() 822504SN/A{ 832504SN/A if (table) 842152SN/A delete [] table; 852504SN/A} 862152SN/A 872152SN/ATlbEntry* 882152SN/ATLB::lookup(Addr va, uint8_t cid) 892152SN/A{ 902152SN/A // XXX This should either turn into a TlbMap or add caching 912152SN/A 926993Snate@binkert.org TlbEntry *retval = NULL; 936993Snate@binkert.org 946993Snate@binkert.org // Do some kind of caching, fast indexing, anything 956993Snate@binkert.org 966993Snate@binkert.org int x = 0; 976993Snate@binkert.org while (retval == NULL && x < size) { 986993Snate@binkert.org if (table[x].match(va, cid)) { 996993Snate@binkert.org retval = &table[x]; 1006993Snate@binkert.org if (x == nlu) 1016993Snate@binkert.org nextnlu(); 1026993Snate@binkert.org 1036993Snate@binkert.org break; 1046993Snate@binkert.org } 1056993Snate@binkert.org x++; 1066993Snate@binkert.org } 1076993Snate@binkert.org 1086993Snate@binkert.org DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 1096998Snate@binkert.org va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 1106998Snate@binkert.org retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 1116998Snate@binkert.org retval ? retval->ap : 0); 1127756SAli.Saidi@ARM.com ; 1136993Snate@binkert.org return retval; 1146993Snate@binkert.org} 1156993Snate@binkert.org 1166993Snate@binkert.org// insert a new TLB entry 1176993Snate@binkert.orgvoid 1186993Snate@binkert.orgTLB::insert(Addr addr, TlbEntry &entry) 1196993Snate@binkert.org{ 1206993Snate@binkert.org DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 1217816Ssteve.reinhardt@amd.com " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 1222152SN/A " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 1232766Sktlim@umich.edu entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 1242766Sktlim@umich.edu entry.xn, entry.ap, entry.domain); 1256993Snate@binkert.org 1262152SN/A if (table[nlu].valid) 1272152SN/A DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 1285944Sgblack@eecs.umich.edu table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N, 1295944Sgblack@eecs.umich.edu table[nlu].size, table[nlu].ap); 1305944Sgblack@eecs.umich.edu 1315944Sgblack@eecs.umich.edu // XXX Update caching, lookup table etc 1325944Sgblack@eecs.umich.edu table[nlu] = entry; 133 134 // XXX Figure out how entries are generally inserted in ARM 135 nextnlu(); 136} 137 138void 139TLB::printTlb() 140{ 141 int x = 0; 142 TlbEntry *te; 143 DPRINTF(TLB, "Current TLB contents:\n"); 144 while (x < size) { 145 te = &table[x]; 146 if (te->valid) 147 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 148 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 149 x++; 150 } 151} 152 153 154void 155TLB::flushAll() 156{ 157 DPRINTF(TLB, "Flushing all TLB entries\n"); 158 int x = 0; 159 TlbEntry *te; 160 while (x < size) { 161 te = &table[x]; 162 if (te->valid) 163 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 164 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 165 x++; 166 } 167 168 memset(table, 0, sizeof(TlbEntry[size])); 169 nlu = 0; 170} 171 172 173void 174TLB::flushMvaAsid(Addr mva, uint64_t asn) 175{ 176 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 177 TlbEntry *te; 178 179 te = lookup(mva, asn); 180 while (te != NULL) { 181 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 182 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 183 te->valid = false; 184 te = lookup(mva,asn); 185 } 186} 187 188void 189TLB::flushAsid(uint64_t asn) 190{ 191 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 192 193 int x = 0; 194 TlbEntry *te; 195 196 while (x < size) { 197 te = &table[x]; 198 if (te->asid == asn) { 199 te->valid = false; 200 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 201 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 202 } 203 x++; 204 } 205} 206 207void 208TLB::flushMva(Addr mva) 209{ 210 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 211 212 int x = 0; 213 TlbEntry *te; 214 215 while (x < size) { 216 te = &table[x]; 217 Addr v = te->vpn << te->N; 218 if (mva >= v && mva < v + te->size) { 219 te->valid = false; 220 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 221 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 222 } 223 x++; 224 } 225} 226 227void 228TLB::serialize(ostream &os) 229{ 230 panic("Implement Serialize\n"); 231} 232 233void 234TLB::unserialize(Checkpoint *cp, const string §ion) 235{ 236 237 panic("Need to properly unserialize TLB\n"); 238} 239 240void 241TLB::regStats() 242{ 243 read_hits 244 .name(name() + ".read_hits") 245 .desc("DTB read hits") 246 ; 247 248 read_misses 249 .name(name() + ".read_misses") 250 .desc("DTB read misses") 251 ; 252 253 254 read_accesses 255 .name(name() + ".read_accesses") 256 .desc("DTB read accesses") 257 ; 258 259 write_hits 260 .name(name() + ".write_hits") 261 .desc("DTB write hits") 262 ; 263 264 write_misses 265 .name(name() + ".write_misses") 266 .desc("DTB write misses") 267 ; 268 269 270 write_accesses 271 .name(name() + ".write_accesses") 272 .desc("DTB write accesses") 273 ; 274 275 hits 276 .name(name() + ".hits") 277 .desc("DTB hits") 278 ; 279 280 misses 281 .name(name() + ".misses") 282 .desc("DTB misses") 283 ; 284 285 accesses 286 .name(name() + ".accesses") 287 .desc("DTB accesses") 288 ; 289 290 hits = read_hits + write_hits; 291 misses = read_misses + write_misses; 292 accesses = read_accesses + write_accesses; 293} 294 295#if !FULL_SYSTEM 296Fault 297TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 298 Translation *translation, bool &delay, bool timing) 299{ 300 // XXX Cache misc registers and have miscreg write function inv cache 301 Addr vaddr = req->getVaddr() & ~PcModeMask; 302 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 303 uint32_t flags = req->getFlags(); 304 305 bool is_fetch = (mode == Execute); 306 bool is_write = (mode == Write); 307 308 if (!is_fetch) { 309 assert(flags & MustBeOne); 310 if (sctlr.a || !(flags & AllowUnaligned)) { 311 if (vaddr & flags & AlignmentMask) { 312 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 313 } 314 } 315 } 316 317 Addr paddr; 318 Process *p = tc->getProcessPtr(); 319 320 if (!p->pTable->translate(vaddr, paddr)) 321 return Fault(new GenericPageTableFault(vaddr)); 322 req->setPaddr(paddr); 323 324 return NoFault; 325} 326 327#else // FULL_SYSTEM 328 329Fault 330TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 331{ 332 return NoFault; 333} 334 335Fault 336TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 337 bool is_write, uint8_t domain, bool sNp) 338{ 339 return NoFault; 340} 341 342Fault 343TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 344 Translation *translation, bool &delay, bool timing) 345{ 346 // XXX Cache misc registers and have miscreg write function inv cache 347 Addr vaddr = req->getVaddr() & ~PcModeMask; 348 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 349 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 350 uint32_t flags = req->getFlags(); 351 352 bool is_fetch = (mode == Execute); 353 bool is_write = (mode == Write); 354 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode); 355 356 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags 357 & UserMode); 358 if (!is_fetch) { 359 assert(flags & MustBeOne); 360 if (sctlr.a || !(flags & AllowUnaligned)) { 361 if (vaddr & flags & AlignmentMask) { 362 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 363 } 364 } 365 } 366 367 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 368 Fault fault; 369 370 371 if (!sctlr.m) { 372 req->setPaddr(vaddr); 373 if (sctlr.tre == 0) { 374 req->setFlags(Request::UNCACHEABLE); 375 } else { 376 PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 377 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 378 379 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 380 req->setFlags(Request::UNCACHEABLE); 381 } 382 383 // Set memory attributes 384 TlbEntry temp_te; 385 tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 386 temp_te.shareable = true; 387 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 388 %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 389 temp_te.innerAttrs, temp_te.outerAttrs); 390 setAttr(temp_te.attributes); 391 392 return trickBoxCheck(req, mode, 0, false); 393 } 394 395 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 396 // Translation enabled 397 398 TlbEntry *te = lookup(vaddr, context_id); 399 if (te == NULL) { 400 // start translation table walk, pass variables rather than 401 // re-retreaving in table walker for speed 402 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 403 vaddr, context_id); 404 fault = tableWalker->walk(req, tc, context_id, mode, translation, 405 timing); 406 if (timing) { 407 delay = true; 408 // for timing mode, return and wait for table walk 409 return fault; 410 } 411 if (fault) 412 return fault; 413 414 te = lookup(vaddr, context_id); 415 if (!te) 416 printTlb(); 417 assert(te); 418 } 419 420 // Set memory attributes 421 DPRINTF(TLBVerbose, 422 "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 423 outerAttrs: %d\n", 424 te->shareable, te->innerAttrs, te->outerAttrs); 425 setAttr(te->attributes); 426 427 uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 428 switch ( (dacr >> (te->domain * 2)) & 0x3) { 429 case 0: 430 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 431 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 432 if (is_fetch) 433 return new PrefetchAbort(vaddr, 434 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 435 else 436 return new DataAbort(vaddr, te->domain, is_write, 437 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 438 case 1: 439 // Continue with permissions check 440 break; 441 case 2: 442 panic("UNPRED domain\n"); 443 case 3: 444 req->setPaddr(te->pAddr(vaddr)); 445 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 446 if (fault) 447 return fault; 448 return NoFault; 449 } 450 451 uint8_t ap = te->ap; 452 453 if (sctlr.afe == 1) 454 ap |= 1; 455 456 bool abt; 457 458 /* if (!sctlr.xp) 459 ap &= 0x3; 460*/ 461 switch (ap) { 462 case 0: 463 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 464 if (!sctlr.xp) { 465 switch ((int)sctlr.rs) { 466 case 2: 467 abt = is_write; 468 break; 469 case 1: 470 abt = is_write || !is_priv; 471 break; 472 case 0: 473 case 3: 474 default: 475 abt = true; 476 break; 477 } 478 } else { 479 abt = true; 480 } 481 break; 482 case 1: 483 abt = !is_priv; 484 break; 485 case 2: 486 abt = !is_priv && is_write; 487 break; 488 case 3: 489 abt = false; 490 break; 491 case 4: 492 panic("UNPRED premissions\n"); 493 case 5: 494 abt = !is_priv || is_write; 495 break; 496 case 6: 497 case 7: 498 abt = is_write; 499 break; 500 default: 501 panic("Unknown permissions\n"); 502 } 503 if ((is_fetch) && (abt || te->xn)) { 504 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 505 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 506 return new PrefetchAbort(vaddr, 507 (te->sNp ? ArmFault::Permission0 : 508 ArmFault::Permission1)); 509 } else if (abt) { 510 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 511 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 512 return new DataAbort(vaddr, te->domain, is_write, 513 (te->sNp ? ArmFault::Permission0 : 514 ArmFault::Permission1)); 515 } 516 517 req->setPaddr(te->pAddr(vaddr)); 518 // Check for a trickbox generated address fault 519 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 520 if (fault) 521 return fault; 522 523 return NoFault; 524} 525 526#endif 527 528Fault 529TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 530{ 531 bool delay = false; 532 Fault fault; 533#if FULL_SYSTEM 534 fault = translateFs(req, tc, mode, NULL, delay, false); 535#else 536 fault = translateSe(req, tc, mode, NULL, delay, false); 537#endif 538 assert(!delay); 539 return fault; 540} 541 542Fault 543TLB::translateTiming(RequestPtr req, ThreadContext *tc, 544 Translation *translation, Mode mode) 545{ 546 assert(translation); 547 bool delay = false; 548 Fault fault; 549#if FULL_SYSTEM 550 fault = translateFs(req, tc, mode, translation, delay, true); 551#else 552 fault = translateSe(req, tc, mode, translation, delay, true); 553#endif 554 if (!delay) 555 translation->finish(fault, req, tc, mode); 556 return fault; 557} 558 559ArmISA::TLB * 560ArmTLBParams::create() 561{ 562 return new ArmISA::TLB(this); 563} 564