tlb.cc revision 7406:ddc26bd4ea7d
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Steve Reinhardt 43 */ 44 45#include <string> 46#include <vector> 47 48#include "arch/arm/faults.hh" 49#include "arch/arm/pagetable.hh" 50#include "arch/arm/tlb.hh" 51#include "arch/arm/utility.hh" 52#include "base/inifile.hh" 53#include "base/str.hh" 54#include "base/trace.hh" 55#include "cpu/thread_context.hh" 56#include "mem/page_table.hh" 57#include "params/ArmTLB.hh" 58#include "sim/process.hh" 59 60#if FULL_SYSTEM 61#include "arch/arm/table_walker.hh" 62#endif 63 64using namespace std; 65using namespace ArmISA; 66 67TLB::TLB(const Params *p) 68 : BaseTLB(p), size(p->size), nlu(0) 69#if FULL_SYSTEM 70 , tableWalker(p->walker) 71#endif 72{ 73 table = new TlbEntry[size]; 74 memset(table, 0, sizeof(TlbEntry[size])); 75 76#if FULL_SYSTEM 77 tableWalker->setTlb(this); 78#endif 79} 80 81TLB::~TLB() 82{ 83 if (table) 84 delete [] table; 85} 86 87TlbEntry* 88TLB::lookup(Addr va, uint8_t cid) 89{ 90 // XXX This should either turn into a TlbMap or add caching 91 92 TlbEntry *retval = NULL; 93 94 // Do some kind of caching, fast indexing, anything 95 96 int x = 0; 97 while (retval == NULL && x < size) { 98 if (table[x].match(va, cid)) { 99 retval = &table[x]; 100 if (x == nlu) 101 nextnlu(); 102 103 break; 104 } 105 x++; 106 } 107 108 DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 109 va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 110 retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 111 retval ? retval->ap : 0); 112 ; 113 return retval; 114} 115 116// insert a new TLB entry 117void 118TLB::insert(Addr addr, TlbEntry &entry) 119{ 120 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 121 " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 122 " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 123 entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 124 entry.xn, entry.ap, entry.domain); 125 126 if (table[nlu].valid) 127 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 128 table[nlu].vpn << table[nlu].N, table[nlu].asid, table[nlu].pfn << table[nlu].N, 129 table[nlu].size, table[nlu].ap); 130 131 // XXX Update caching, lookup table etc 132 table[nlu] = entry; 133 134 // XXX Figure out how entries are generally inserted in ARM 135 nextnlu(); 136} 137 138void 139TLB::printTlb() 140{ 141 int x = 0; 142 TlbEntry *te; 143 DPRINTF(TLB, "Current TLB contents:\n"); 144 while (x < size) { 145 te = &table[x]; 146 if (te->valid) 147 DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 148 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 149 x++; 150 } 151} 152 153 154void 155TLB::flushAll() 156{ 157 DPRINTF(TLB, "Flushing all TLB entries\n"); 158 int x = 0; 159 TlbEntry *te; 160 while (x < size) { 161 te = &table[x]; 162 if (te->valid) 163 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 164 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 165 x++; 166 } 167 168 memset(table, 0, sizeof(TlbEntry[size])); 169 nlu = 0; 170} 171 172 173void 174TLB::flushMvaAsid(Addr mva, uint64_t asn) 175{ 176 DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 177 TlbEntry *te; 178 179 te = lookup(mva, asn); 180 while (te != NULL) { 181 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 182 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 183 te->valid = false; 184 te = lookup(mva,asn); 185 } 186} 187 188void 189TLB::flushAsid(uint64_t asn) 190{ 191 DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 192 193 int x = 0; 194 TlbEntry *te; 195 196 while (x < size) { 197 te = &table[x]; 198 if (te->asid == asn) { 199 te->valid = false; 200 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 201 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 202 } 203 x++; 204 } 205} 206 207void 208TLB::flushMva(Addr mva) 209{ 210 DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 211 212 int x = 0; 213 TlbEntry *te; 214 215 while (x < size) { 216 te = &table[x]; 217 Addr v = te->vpn << te->N; 218 if (mva >= v && mva < v + te->size) { 219 te->valid = false; 220 DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 221 te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 222 } 223 x++; 224 } 225} 226 227void 228TLB::serialize(ostream &os) 229{ 230 panic("Implement Serialize\n"); 231} 232 233void 234TLB::unserialize(Checkpoint *cp, const string §ion) 235{ 236 237 panic("Need to properly unserialize TLB\n"); 238} 239 240void 241TLB::regStats() 242{ 243 read_hits 244 .name(name() + ".read_hits") 245 .desc("DTB read hits") 246 ; 247 248 read_misses 249 .name(name() + ".read_misses") 250 .desc("DTB read misses") 251 ; 252 253 254 read_accesses 255 .name(name() + ".read_accesses") 256 .desc("DTB read accesses") 257 ; 258 259 write_hits 260 .name(name() + ".write_hits") 261 .desc("DTB write hits") 262 ; 263 264 write_misses 265 .name(name() + ".write_misses") 266 .desc("DTB write misses") 267 ; 268 269 270 write_accesses 271 .name(name() + ".write_accesses") 272 .desc("DTB write accesses") 273 ; 274 275 hits 276 .name(name() + ".hits") 277 .desc("DTB hits") 278 ; 279 280 misses 281 .name(name() + ".misses") 282 .desc("DTB misses") 283 ; 284 285 invalids 286 .name(name() + ".invalids") 287 .desc("DTB access violations") 288 ; 289 290 accesses 291 .name(name() + ".accesses") 292 .desc("DTB accesses") 293 ; 294 295 hits = read_hits + write_hits; 296 misses = read_misses + write_misses; 297 accesses = read_accesses + write_accesses; 298} 299 300#if !FULL_SYSTEM 301Fault 302TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 303 Translation *translation, bool &delay, bool timing) 304{ 305 // XXX Cache misc registers and have miscreg write function inv cache 306 Addr vaddr = req->getVaddr() & ~PcModeMask; 307 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 308 uint32_t flags = req->getFlags(); 309 310 bool is_fetch = (mode == Execute); 311 bool is_write = (mode == Write); 312 313 if (!is_fetch) { 314 assert(flags & MustBeOne); 315 if (sctlr.a || !(flags & AllowUnaligned)) { 316 if (vaddr & flags & AlignmentMask) { 317 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 318 } 319 } 320 } 321 322 Addr paddr; 323 Process *p = tc->getProcessPtr(); 324 325 if (!p->pTable->translate(vaddr, paddr)) 326 return Fault(new GenericPageTableFault(vaddr)); 327 req->setPaddr(paddr); 328 329 return NoFault; 330} 331 332#else // FULL_SYSTEM 333 334Fault 335TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 336{ 337 return NoFault; 338} 339 340Fault 341TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 342 bool is_write, uint8_t domain, bool sNp) 343{ 344 return NoFault; 345} 346 347Fault 348TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 349 Translation *translation, bool &delay, bool timing) 350{ 351 // XXX Cache misc registers and have miscreg write function inv cache 352 Addr vaddr = req->getVaddr() & ~PcModeMask; 353 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 354 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 355 uint32_t flags = req->getFlags(); 356 357 bool is_fetch = (mode == Execute); 358 bool is_write = (mode == Write); 359 bool is_priv = (cpsr.mode != MODE_USER) && !(flags & UserMode); 360 361 DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags 362 & UserMode); 363 if (!is_fetch) { 364 assert(flags & MustBeOne); 365 if (sctlr.a || !(flags & AllowUnaligned)) { 366 if (vaddr & flags & AlignmentMask) { 367 return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 368 } 369 } 370 } 371 372 uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR); 373 Fault fault; 374 375 376 if (!sctlr.m) { 377 req->setPaddr(vaddr); 378 if (sctlr.tre == 0) { 379 req->setFlags(Request::UNCACHEABLE); 380 } else { 381 PRRR prrr = tc->readMiscReg(MISCREG_PRRR); 382 NMRR nmrr = tc->readMiscReg(MISCREG_NMRR); 383 384 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 385 req->setFlags(Request::UNCACHEABLE); 386 } 387 return trickBoxCheck(req, mode, 0, false); 388 } 389 390 DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, context_id); 391 // Translation enabled 392 393 TlbEntry *te = lookup(vaddr, context_id); 394 if (te == NULL) { 395 // start translation table walk, pass variables rather than 396 // re-retreaving in table walker for speed 397 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 398 vaddr, context_id); 399 fault = tableWalker->walk(req, tc, context_id, mode, translation, 400 timing); 401 if (timing) 402 delay = true; 403 if (fault) 404 return fault; 405 406 te = lookup(vaddr, context_id); 407 if (!te) 408 printTlb(); 409 assert(te); 410 } 411 412 uint32_t dacr = tc->readMiscReg(MISCREG_DACR); 413 switch ( (dacr >> (te->domain * 2)) & 0x3) { 414 case 0: 415 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 416 " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 417 if (is_fetch) 418 return new PrefetchAbort(vaddr, 419 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 420 else 421 return new DataAbort(vaddr, te->domain, is_write, 422 (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 423 case 1: 424 // Continue with permissions check 425 break; 426 case 2: 427 panic("UNPRED domain\n"); 428 case 3: 429 req->setPaddr(te->pAddr(vaddr)); 430 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 431 if (fault) 432 return fault; 433 return NoFault; 434 } 435 436 uint8_t ap = te->ap; 437 438 if (sctlr.afe == 1) 439 ap |= 1; 440 441 bool abt; 442 443 /* if (!sctlr.xp) 444 ap &= 0x3; 445*/ 446 switch (ap) { 447 case 0: 448 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 449 if (!sctlr.xp) { 450 switch ((int)sctlr.rs) { 451 case 2: 452 abt = is_write; 453 break; 454 case 1: 455 abt = is_write || !is_priv; 456 break; 457 case 0: 458 case 3: 459 default: 460 abt = true; 461 break; 462 } 463 } else { 464 abt = true; 465 } 466 break; 467 case 1: 468 abt = !is_priv; 469 break; 470 case 2: 471 abt = !is_priv && is_write; 472 break; 473 case 3: 474 abt = false; 475 break; 476 case 4: 477 panic("UNPRED premissions\n"); 478 case 5: 479 abt = !is_priv || is_write; 480 break; 481 case 6: 482 case 7: 483 abt = is_write; 484 break; 485 default: 486 panic("Unknown permissions\n"); 487 } 488 if ((is_fetch) && (abt || te->xn)) { 489 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 490 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 491 return new PrefetchAbort(vaddr, 492 (te->sNp ? ArmFault::Permission0 : 493 ArmFault::Permission1)); 494 } else if (abt) { 495 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 496 " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 497 return new DataAbort(vaddr, te->domain, is_write, 498 (te->sNp ? ArmFault::Permission0 : 499 ArmFault::Permission1)); 500 } 501 502 req->setPaddr(te->pAddr(vaddr)); 503 // Check for a trickbox generated address fault 504 fault = trickBoxCheck(req, mode, te->domain, te->sNp); 505 if (fault) 506 return fault; 507 508 return NoFault; 509} 510 511#endif 512 513Fault 514TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 515{ 516 bool delay = false; 517 Fault fault; 518#if FULL_SYSTEM 519 fault = translateFs(req, tc, mode, NULL, delay, false); 520#else 521 fault = translateSe(req, tc, mode, NULL, delay, false); 522#endif 523 assert(!delay); 524 return fault; 525} 526 527Fault 528TLB::translateTiming(RequestPtr req, ThreadContext *tc, 529 Translation *translation, Mode mode) 530{ 531 assert(translation); 532 bool delay = false; 533 Fault fault; 534#if FULL_SYSTEM 535 fault = translateFs(req, tc, mode, translation, delay, true); 536#else 537 fault = translateSe(req, tc, mode, translation, delay, true); 538#endif 539 if (!delay) 540 translation->finish(fault, req, tc, mode); 541 return fault; 542} 543 544ArmISA::TLB * 545ArmTLBParams::create() 546{ 547 return new ArmISA::TLB(this); 548} 549