tlb.cc revision 6020:0647c8b31a99
19356Snilay@cs.wisc.edu/* 29356Snilay@cs.wisc.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 39983Sstever@gmail.com * Copyright (c) 2007 MIPS Technologies, Inc. 49983Sstever@gmail.com * Copyright (c) 2007-2008 The Florida State University 59356Snilay@cs.wisc.edu * All rights reserved. 69356Snilay@cs.wisc.edu * 79356Snilay@cs.wisc.edu * Redistribution and use in source and binary forms, with or without 89356Snilay@cs.wisc.edu * modification, are permitted provided that the following conditions are 99356Snilay@cs.wisc.edu * met: redistributions of source code must retain the above copyright 109356Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer; 119356Snilay@cs.wisc.edu * redistributions in binary form must reproduce the above copyright 129356Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer in the 139356Snilay@cs.wisc.edu * documentation and/or other materials provided with the distribution; 149356Snilay@cs.wisc.edu * neither the name of the copyright holders nor the names of its 159356Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 169356Snilay@cs.wisc.edu * this software without specific prior written permission. 179356Snilay@cs.wisc.edu * 189356Snilay@cs.wisc.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 199356Snilay@cs.wisc.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 209356Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 219356Snilay@cs.wisc.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 229356Snilay@cs.wisc.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 239356Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 249356Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 259356Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 269356Snilay@cs.wisc.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 279356Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 289356Snilay@cs.wisc.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 299356Snilay@cs.wisc.edu * 309356Snilay@cs.wisc.edu * Authors: Nathan Binkert 319356Snilay@cs.wisc.edu * Steve Reinhardt 329356Snilay@cs.wisc.edu * Jaidev Patwardhan 339356Snilay@cs.wisc.edu * Stephen Hines 349356Snilay@cs.wisc.edu */ 359356Snilay@cs.wisc.edu 369356Snilay@cs.wisc.edu#include <string> 379356Snilay@cs.wisc.edu#include <vector> 389356Snilay@cs.wisc.edu 399356Snilay@cs.wisc.edu#include "arch/arm/pagetable.hh" 409356Snilay@cs.wisc.edu#include "arch/arm/tlb.hh" 419356Snilay@cs.wisc.edu#include "arch/arm/faults.hh" 429983Sstever@gmail.com#include "arch/arm/utility.hh" 439356Snilay@cs.wisc.edu#include "base/inifile.hh" 449356Snilay@cs.wisc.edu#include "base/str.hh" 459356Snilay@cs.wisc.edu#include "base/trace.hh" 469356Snilay@cs.wisc.edu#include "cpu/thread_context.hh" 479356Snilay@cs.wisc.edu#include "sim/process.hh" 489356Snilay@cs.wisc.edu#include "mem/page_table.hh" 499983Sstever@gmail.com#include "params/ArmDTB.hh" 509983Sstever@gmail.com#include "params/ArmITB.hh" 519983Sstever@gmail.com#include "params/ArmTLB.hh" 529983Sstever@gmail.com#include "params/ArmUTB.hh" 539983Sstever@gmail.com 549983Sstever@gmail.com 559983Sstever@gmail.comusing namespace std; 569983Sstever@gmail.comusing namespace ArmISA; 579983Sstever@gmail.com 589983Sstever@gmail.com/////////////////////////////////////////////////////////////////////// 599983Sstever@gmail.com// 609983Sstever@gmail.com// ARM TLB 619356Snilay@cs.wisc.edu// 6212040Sandreas.sandberg@arm.com 639356Snilay@cs.wisc.edu#define MODE2MASK(X) (1 << (X)) 649356Snilay@cs.wisc.edu 659356Snilay@cs.wisc.eduTLB::TLB(const Params *p) 669356Snilay@cs.wisc.edu : BaseTLB(p), size(p->size), nlu(0) 679356Snilay@cs.wisc.edu{ 689356Snilay@cs.wisc.edu table = new ArmISA::PTE[size]; 699356Snilay@cs.wisc.edu memset(table, 0, sizeof(ArmISA::PTE[size])); 709356Snilay@cs.wisc.edu smallPages=0; 719356Snilay@cs.wisc.edu} 729356Snilay@cs.wisc.edu 739983Sstever@gmail.comTLB::~TLB() 749356Snilay@cs.wisc.edu{ 759356Snilay@cs.wisc.edu if (table) 769356Snilay@cs.wisc.edu delete [] table; 779356Snilay@cs.wisc.edu} 789356Snilay@cs.wisc.edu 799356Snilay@cs.wisc.edu// look up an entry in the TLB 809356Snilay@cs.wisc.eduArmISA::PTE * 819356Snilay@cs.wisc.eduTLB::lookup(Addr vpn, uint8_t asn) const 829356Snilay@cs.wisc.edu{ 8312040Sandreas.sandberg@arm.com // assume not found... 849356Snilay@cs.wisc.edu ArmISA::PTE *retval = NULL; 859356Snilay@cs.wisc.edu PageTable::const_iterator i = lookupTable.find(vpn); 869356Snilay@cs.wisc.edu if (i != lookupTable.end()) { 879356Snilay@cs.wisc.edu while (i->first == vpn) { 889356Snilay@cs.wisc.edu int index = i->second; 899356Snilay@cs.wisc.edu ArmISA::PTE *pte = &table[index]; 909356Snilay@cs.wisc.edu 919356Snilay@cs.wisc.edu /* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */ 929983Sstever@gmail.com Addr Mask = pte->Mask; 939356Snilay@cs.wisc.edu Addr InvMask = ~Mask; 9412040Sandreas.sandberg@arm.com Addr VPN = pte->VPN; 959356Snilay@cs.wisc.edu // warn("Valid: %d - %d\n",pte->V0,pte->V1); 9612040Sandreas.sandberg@arm.com if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid))) 9712040Sandreas.sandberg@arm.com { // We have a VPN + ASID Match 9812040Sandreas.sandberg@arm.com retval = pte; 999356Snilay@cs.wisc.edu break; 1009356Snilay@cs.wisc.edu } 1019356Snilay@cs.wisc.edu ++i; 1029356Snilay@cs.wisc.edu } 1039356Snilay@cs.wisc.edu } 1049356Snilay@cs.wisc.edu 1059356Snilay@cs.wisc.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1069356Snilay@cs.wisc.edu retval ? "hit" : "miss", retval ? retval->PFN1 : 0); 1079356Snilay@cs.wisc.edu return retval; 1089356Snilay@cs.wisc.edu} 1099356Snilay@cs.wisc.edu 110ArmISA::PTE* TLB::getEntry(unsigned Index) const 111{ 112 // Make sure that Index is valid 113 assert(Index<size); 114 return &table[Index]; 115} 116 117int TLB::probeEntry(Addr vpn,uint8_t asn) const 118{ 119 // assume not found... 120 ArmISA::PTE *retval = NULL; 121 int Ind=-1; 122 PageTable::const_iterator i = lookupTable.find(vpn); 123 if (i != lookupTable.end()) { 124 while (i->first == vpn) { 125 int index = i->second; 126 ArmISA::PTE *pte = &table[index]; 127 128 /* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */ 129 Addr Mask = pte->Mask; 130 Addr InvMask = ~Mask; 131 Addr VPN = pte->VPN; 132 if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid))) 133 { // We have a VPN + ASID Match 134 retval = pte; 135 Ind = index; 136 break; 137 } 138 139 ++i; 140 } 141 } 142 DPRINTF(Arm,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind); 143 return Ind; 144} 145Fault inline 146TLB::checkCacheability(RequestPtr &req) 147{ 148 Addr VAddrUncacheable = 0xA0000000; 149 // In ARM, cacheability is controlled by certain bits of the virtual address 150 // or by the TLB entry 151 if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { 152 // mark request as uncacheable 153 req->setFlags(req->getFlags() | Request::UNCACHEABLE); 154 } 155 return NoFault; 156} 157void TLB::insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages) 158{ 159 smallPages=_smallPages; 160 if(Index > size){ 161 warn("Attempted to write at index (%d) beyond TLB size (%d)",Index,size); 162 } else { 163 // Update TLB 164 DPRINTF(TLB,"TLB[%d]: %x %x %x %x\n",Index,pte.Mask<<11,((pte.VPN << 11) | pte.asid),((pte.PFN0 <<6) | (pte.C0 << 3) | (pte.D0 << 2) | (pte.V0 <<1) | pte.G), 165 ((pte.PFN1 <<6) | (pte.C1 << 3) | (pte.D1 << 2) | (pte.V1 <<1) | pte.G)); 166 if(table[Index].V0 == true || table[Index].V1 == true){ // Previous entry is valid 167 PageTable::iterator i = lookupTable.find(table[Index].VPN); 168 lookupTable.erase(i); 169 } 170 table[Index]=pte; 171 // Update fast lookup table 172 lookupTable.insert(make_pair(table[Index].VPN, Index)); 173 // int TestIndex=probeEntry(pte.VPN,pte.asid); 174 // warn("Inserted at: %d, Found at: %d (%x)\n",Index,TestIndex,pte.Mask); 175 } 176 177} 178 179// insert a new TLB entry 180void 181TLB::insert(Addr addr, ArmISA::PTE &pte) 182{ 183 fatal("TLB Insert not yet implemented\n"); 184} 185 186void 187TLB::flushAll() 188{ 189 DPRINTF(TLB, "flushAll\n"); 190 memset(table, 0, sizeof(ArmISA::PTE[size])); 191 lookupTable.clear(); 192 nlu = 0; 193} 194 195void 196TLB::serialize(ostream &os) 197{ 198 SERIALIZE_SCALAR(size); 199 SERIALIZE_SCALAR(nlu); 200 201 for (int i = 0; i < size; i++) { 202 nameOut(os, csprintf("%s.PTE%d", name(), i)); 203 table[i].serialize(os); 204 } 205} 206 207void 208TLB::unserialize(Checkpoint *cp, const string §ion) 209{ 210 UNSERIALIZE_SCALAR(size); 211 UNSERIALIZE_SCALAR(nlu); 212 213 for (int i = 0; i < size; i++) { 214 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 215 if (table[i].V0 || table[i].V1) { 216 lookupTable.insert(make_pair(table[i].VPN, i)); 217 } 218 } 219} 220 221void 222TLB::regStats() 223{ 224 read_hits 225 .name(name() + ".read_hits") 226 .desc("DTB read hits") 227 ; 228 229 read_misses 230 .name(name() + ".read_misses") 231 .desc("DTB read misses") 232 ; 233 234 235 read_accesses 236 .name(name() + ".read_accesses") 237 .desc("DTB read accesses") 238 ; 239 240 write_hits 241 .name(name() + ".write_hits") 242 .desc("DTB write hits") 243 ; 244 245 write_misses 246 .name(name() + ".write_misses") 247 .desc("DTB write misses") 248 ; 249 250 251 write_accesses 252 .name(name() + ".write_accesses") 253 .desc("DTB write accesses") 254 ; 255 256 hits 257 .name(name() + ".hits") 258 .desc("DTB hits") 259 ; 260 261 misses 262 .name(name() + ".misses") 263 .desc("DTB misses") 264 ; 265 266 invalids 267 .name(name() + ".invalids") 268 .desc("DTB access violations") 269 ; 270 271 accesses 272 .name(name() + ".accesses") 273 .desc("DTB accesses") 274 ; 275 276 hits = read_hits + write_hits; 277 misses = read_misses + write_misses; 278 accesses = read_accesses + write_accesses; 279} 280 281Fault 282ITB::translateAtomic(RequestPtr req, ThreadContext *tc) 283{ 284#if !FULL_SYSTEM 285 Process * p = tc->getProcessPtr(); 286 287 Fault fault = p->pTable->translate(req); 288 if(fault != NoFault) 289 return fault; 290 291 return NoFault; 292#else 293 fatal("ITB translate not yet implemented\n"); 294#endif 295} 296 297void 298ITB::translateTiming(RequestPtr req, ThreadContext *tc, 299 Translation *translation) 300{ 301 assert(translation); 302 translation->finish(translateAtomic(req, tc), req, tc, false); 303} 304 305 306Fault 307DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write) 308{ 309#if !FULL_SYSTEM 310 Process * p = tc->getProcessPtr(); 311 312 Fault fault = p->pTable->translate(req); 313 if(fault != NoFault) 314 return fault; 315 316 return NoFault; 317#else 318 fatal("DTB translate not yet implemented\n"); 319#endif 320} 321 322void 323DTB::translateTiming(RequestPtr req, ThreadContext *tc, 324 Translation *translation, bool write) 325{ 326 assert(translation); 327 translation->finish(translateAtomic(req, tc, write), req, tc, write); 328} 329 330/////////////////////////////////////////////////////////////////////// 331// 332// Arm ITB 333// 334ITB::ITB(const Params *p) 335 : TLB(p) 336{} 337 338 339/////////////////////////////////////////////////////////////////////// 340// 341// Arm DTB 342// 343DTB::DTB(const Params *p) 344 : TLB(p) 345{} 346 347/////////////////////////////////////////////////////////////////////// 348// 349// Arm UTB 350// 351UTB::UTB(const Params *p) 352 : ITB(p), DTB(p) 353{} 354 355ArmISA::PTE & 356TLB::index(bool advance) 357{ 358 ArmISA::PTE *pte = &table[nlu]; 359 360 if (advance) 361 nextnlu(); 362 363 return *pte; 364} 365 366ArmISA::ITB * 367ArmITBParams::create() 368{ 369 return new ArmISA::ITB(this); 370} 371 372ArmISA::DTB * 373ArmDTBParams::create() 374{ 375 return new ArmISA::DTB(this); 376} 377 378ArmISA::UTB * 379ArmUTBParams::create() 380{ 381 return new ArmISA::UTB(this); 382} 383