tlb.cc revision 10611:3bba9f2d0c7d
1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Steve Reinhardt 43 */ 44 45#include <memory> 46#include <string> 47#include <vector> 48 49#include "arch/arm/faults.hh" 50#include "arch/arm/pagetable.hh" 51#include "arch/arm/system.hh" 52#include "arch/arm/table_walker.hh" 53#include "arch/arm/stage2_lookup.hh" 54#include "arch/arm/stage2_mmu.hh" 55#include "arch/arm/tlb.hh" 56#include "arch/arm/utility.hh" 57#include "base/inifile.hh" 58#include "base/str.hh" 59#include "base/trace.hh" 60#include "cpu/base.hh" 61#include "cpu/thread_context.hh" 62#include "debug/Checkpoint.hh" 63#include "debug/TLB.hh" 64#include "debug/TLBVerbose.hh" 65#include "mem/page_table.hh" 66#include "params/ArmTLB.hh" 67#include "sim/full_system.hh" 68#include "sim/process.hh" 69 70using namespace std; 71using namespace ArmISA; 72 73TLB::TLB(const ArmTLBParams *p) 74 : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size), 75 isStage2(p->is_stage2), stage2Req(false), _attr(0), 76 directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL), 77 stage2Mmu(NULL), rangeMRU(1), bootUncacheability(false), 78 aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false), 79 isHyp(false), asid(0), vmid(0), dacr(0), 80 miscRegValid(false), curTranType(NormalTran) 81{ 82 tableWalker->setTlb(this); 83 84 // Cache system-level properties 85 haveLPAE = tableWalker->haveLPAE(); 86 haveVirtualization = tableWalker->haveVirtualization(); 87 haveLargeAsid64 = tableWalker->haveLargeAsid64(); 88} 89 90TLB::~TLB() 91{ 92 delete[] table; 93} 94 95void 96TLB::init() 97{ 98 if (stage2Mmu && !isStage2) 99 stage2Tlb = stage2Mmu->stage2Tlb(); 100} 101 102void 103TLB::setMMU(Stage2MMU *m) 104{ 105 stage2Mmu = m; 106 tableWalker->setMMU(m); 107} 108 109bool 110TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 111{ 112 updateMiscReg(tc); 113 114 if (directToStage2) { 115 assert(stage2Tlb); 116 return stage2Tlb->translateFunctional(tc, va, pa); 117 } 118 119 TlbEntry *e = lookup(va, asid, vmid, isHyp, isSecure, true, false, 120 aarch64 ? aarch64EL : EL1); 121 if (!e) 122 return false; 123 pa = e->pAddr(va); 124 return true; 125} 126 127Fault 128TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 129{ 130 return NoFault; 131} 132 133TlbEntry* 134TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure, 135 bool functional, bool ignore_asn, uint8_t target_el) 136{ 137 138 TlbEntry *retval = NULL; 139 140 // Maintaining LRU array 141 int x = 0; 142 while (retval == NULL && x < size) { 143 if ((!ignore_asn && table[x].match(va, asn, vmid, hyp, secure, false, 144 target_el)) || 145 (ignore_asn && table[x].match(va, vmid, hyp, secure, target_el))) { 146 // We only move the hit entry ahead when the position is higher 147 // than rangeMRU 148 if (x > rangeMRU && !functional) { 149 TlbEntry tmp_entry = table[x]; 150 for(int i = x; i > 0; i--) 151 table[i] = table[i - 1]; 152 table[0] = tmp_entry; 153 retval = &table[0]; 154 } else { 155 retval = &table[x]; 156 } 157 break; 158 } 159 ++x; 160 } 161 162 DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x hyp %d secure %d " 163 "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d " 164 "el: %d\n", 165 va, asn, retval ? "hit" : "miss", vmid, hyp, secure, 166 retval ? retval->pfn : 0, retval ? retval->size : 0, 167 retval ? retval->pAddr(va) : 0, retval ? retval->ap : 0, 168 retval ? retval->ns : 0, retval ? retval->nstid : 0, 169 retval ? retval->global : 0, retval ? retval->asid : 0, 170 retval ? retval->el : 0); 171 172 return retval; 173} 174 175// insert a new TLB entry 176void 177TLB::insert(Addr addr, TlbEntry &entry) 178{ 179 DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 180 " asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d" 181 " ap:%#x domain:%#x ns:%d nstid:%d isHyp:%d\n", entry.pfn, 182 entry.size, entry.vpn, entry.asid, entry.vmid, entry.N, 183 entry.global, entry.valid, entry.nonCacheable, entry.xn, 184 entry.ap, static_cast<uint8_t>(entry.domain), entry.ns, entry.nstid, 185 entry.isHyp); 186 187 if (table[size - 1].valid) 188 DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x " 189 "size: %#x ap:%d ns:%d nstid:%d g:%d isHyp:%d el: %d\n", 190 table[size-1].vpn << table[size-1].N, table[size-1].asid, 191 table[size-1].vmid, table[size-1].pfn << table[size-1].N, 192 table[size-1].size, table[size-1].ap, table[size-1].ns, 193 table[size-1].nstid, table[size-1].global, table[size-1].isHyp, 194 table[size-1].el); 195 196 //inserting to MRU position and evicting the LRU one 197 198 for (int i = size - 1; i > 0; --i) 199 table[i] = table[i-1]; 200 table[0] = entry; 201 202 inserts++; 203 ppRefills->notify(1); 204} 205 206void 207TLB::printTlb() const 208{ 209 int x = 0; 210 TlbEntry *te; 211 DPRINTF(TLB, "Current TLB contents:\n"); 212 while (x < size) { 213 te = &table[x]; 214 if (te->valid) 215 DPRINTF(TLB, " * %s\n", te->print()); 216 ++x; 217 } 218} 219 220void 221TLB::flushAllSecurity(bool secure_lookup, uint8_t target_el, bool ignore_el) 222{ 223 DPRINTF(TLB, "Flushing all TLB entries (%s lookup)\n", 224 (secure_lookup ? "secure" : "non-secure")); 225 int x = 0; 226 TlbEntry *te; 227 while (x < size) { 228 te = &table[x]; 229 if (te->valid && secure_lookup == !te->nstid && 230 (te->vmid == vmid || secure_lookup) && 231 checkELMatch(target_el, te->el, ignore_el)) { 232 233 DPRINTF(TLB, " - %s\n", te->print()); 234 te->valid = false; 235 flushedEntries++; 236 } 237 ++x; 238 } 239 240 flushTlb++; 241 242 // If there's a second stage TLB (and we're not it) then flush it as well 243 // if we're currently in hyp mode 244 if (!isStage2 && isHyp) { 245 stage2Tlb->flushAllSecurity(secure_lookup, true); 246 } 247} 248 249void 250TLB::flushAllNs(bool hyp, uint8_t target_el, bool ignore_el) 251{ 252 DPRINTF(TLB, "Flushing all NS TLB entries (%s lookup)\n", 253 (hyp ? "hyp" : "non-hyp")); 254 int x = 0; 255 TlbEntry *te; 256 while (x < size) { 257 te = &table[x]; 258 if (te->valid && te->nstid && te->isHyp == hyp && 259 checkELMatch(target_el, te->el, ignore_el)) { 260 261 DPRINTF(TLB, " - %s\n", te->print()); 262 flushedEntries++; 263 te->valid = false; 264 } 265 ++x; 266 } 267 268 flushTlb++; 269 270 // If there's a second stage TLB (and we're not it) then flush it as well 271 if (!isStage2 && !hyp) { 272 stage2Tlb->flushAllNs(false, true); 273 } 274} 275 276void 277TLB::flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, uint8_t target_el) 278{ 279 DPRINTF(TLB, "Flushing TLB entries with mva: %#x, asid: %#x " 280 "(%s lookup)\n", mva, asn, (secure_lookup ? 281 "secure" : "non-secure")); 282 _flushMva(mva, asn, secure_lookup, false, false, target_el); 283 flushTlbMvaAsid++; 284} 285 286void 287TLB::flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el) 288{ 289 DPRINTF(TLB, "Flushing TLB entries with asid: %#x (%s lookup)\n", asn, 290 (secure_lookup ? "secure" : "non-secure")); 291 292 int x = 0 ; 293 TlbEntry *te; 294 295 while (x < size) { 296 te = &table[x]; 297 if (te->valid && te->asid == asn && secure_lookup == !te->nstid && 298 (te->vmid == vmid || secure_lookup) && 299 checkELMatch(target_el, te->el, false)) { 300 301 te->valid = false; 302 DPRINTF(TLB, " - %s\n", te->print()); 303 flushedEntries++; 304 } 305 ++x; 306 } 307 flushTlbAsid++; 308} 309 310void 311TLB::flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el) 312{ 313 DPRINTF(TLB, "Flushing TLB entries with mva: %#x (%s lookup)\n", mva, 314 (secure_lookup ? "secure" : "non-secure")); 315 _flushMva(mva, 0xbeef, secure_lookup, hyp, true, target_el); 316 flushTlbMva++; 317} 318 319void 320TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool hyp, 321 bool ignore_asn, uint8_t target_el) 322{ 323 TlbEntry *te; 324 // D5.7.2: Sign-extend address to 64 bits 325 mva = sext<56>(mva); 326 te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 327 target_el); 328 while (te != NULL) { 329 if (secure_lookup == !te->nstid) { 330 DPRINTF(TLB, " - %s\n", te->print()); 331 te->valid = false; 332 flushedEntries++; 333 } 334 te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn, 335 target_el); 336 } 337} 338 339bool 340TLB::checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el) 341{ 342 bool elMatch = true; 343 if (!ignore_el) { 344 if (target_el == 2 || target_el == 3) { 345 elMatch = (tentry_el == target_el); 346 } else { 347 elMatch = (tentry_el == 0) || (tentry_el == 1); 348 } 349 } 350 return elMatch; 351} 352 353void 354TLB::drainResume() 355{ 356 // We might have unserialized something or switched CPUs, so make 357 // sure to re-read the misc regs. 358 miscRegValid = false; 359} 360 361void 362TLB::takeOverFrom(BaseTLB *_otlb) 363{ 364 TLB *otlb = dynamic_cast<TLB*>(_otlb); 365 /* Make sure we actually have a valid type */ 366 if (otlb) { 367 _attr = otlb->_attr; 368 haveLPAE = otlb->haveLPAE; 369 directToStage2 = otlb->directToStage2; 370 stage2Req = otlb->stage2Req; 371 bootUncacheability = otlb->bootUncacheability; 372 373 /* Sync the stage2 MMU if they exist in both 374 * the old CPU and the new 375 */ 376 if (!isStage2 && 377 stage2Tlb && otlb->stage2Tlb) { 378 stage2Tlb->takeOverFrom(otlb->stage2Tlb); 379 } 380 } else { 381 panic("Incompatible TLB type!"); 382 } 383} 384 385void 386TLB::serialize(ostream &os) 387{ 388 DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 389 390 SERIALIZE_SCALAR(_attr); 391 SERIALIZE_SCALAR(haveLPAE); 392 SERIALIZE_SCALAR(directToStage2); 393 SERIALIZE_SCALAR(stage2Req); 394 SERIALIZE_SCALAR(bootUncacheability); 395 396 int num_entries = size; 397 SERIALIZE_SCALAR(num_entries); 398 for(int i = 0; i < size; i++){ 399 nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 400 table[i].serialize(os); 401 } 402} 403 404void 405TLB::unserialize(Checkpoint *cp, const string §ion) 406{ 407 DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 408 409 UNSERIALIZE_SCALAR(_attr); 410 UNSERIALIZE_SCALAR(haveLPAE); 411 UNSERIALIZE_SCALAR(directToStage2); 412 UNSERIALIZE_SCALAR(stage2Req); 413 UNSERIALIZE_SCALAR(bootUncacheability); 414 415 int num_entries; 416 UNSERIALIZE_SCALAR(num_entries); 417 for(int i = 0; i < min(size, num_entries); i++){ 418 table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 419 } 420} 421 422void 423TLB::regStats() 424{ 425 instHits 426 .name(name() + ".inst_hits") 427 .desc("ITB inst hits") 428 ; 429 430 instMisses 431 .name(name() + ".inst_misses") 432 .desc("ITB inst misses") 433 ; 434 435 instAccesses 436 .name(name() + ".inst_accesses") 437 .desc("ITB inst accesses") 438 ; 439 440 readHits 441 .name(name() + ".read_hits") 442 .desc("DTB read hits") 443 ; 444 445 readMisses 446 .name(name() + ".read_misses") 447 .desc("DTB read misses") 448 ; 449 450 readAccesses 451 .name(name() + ".read_accesses") 452 .desc("DTB read accesses") 453 ; 454 455 writeHits 456 .name(name() + ".write_hits") 457 .desc("DTB write hits") 458 ; 459 460 writeMisses 461 .name(name() + ".write_misses") 462 .desc("DTB write misses") 463 ; 464 465 writeAccesses 466 .name(name() + ".write_accesses") 467 .desc("DTB write accesses") 468 ; 469 470 hits 471 .name(name() + ".hits") 472 .desc("DTB hits") 473 ; 474 475 misses 476 .name(name() + ".misses") 477 .desc("DTB misses") 478 ; 479 480 accesses 481 .name(name() + ".accesses") 482 .desc("DTB accesses") 483 ; 484 485 flushTlb 486 .name(name() + ".flush_tlb") 487 .desc("Number of times complete TLB was flushed") 488 ; 489 490 flushTlbMva 491 .name(name() + ".flush_tlb_mva") 492 .desc("Number of times TLB was flushed by MVA") 493 ; 494 495 flushTlbMvaAsid 496 .name(name() + ".flush_tlb_mva_asid") 497 .desc("Number of times TLB was flushed by MVA & ASID") 498 ; 499 500 flushTlbAsid 501 .name(name() + ".flush_tlb_asid") 502 .desc("Number of times TLB was flushed by ASID") 503 ; 504 505 flushedEntries 506 .name(name() + ".flush_entries") 507 .desc("Number of entries that have been flushed from TLB") 508 ; 509 510 alignFaults 511 .name(name() + ".align_faults") 512 .desc("Number of TLB faults due to alignment restrictions") 513 ; 514 515 prefetchFaults 516 .name(name() + ".prefetch_faults") 517 .desc("Number of TLB faults due to prefetch") 518 ; 519 520 domainFaults 521 .name(name() + ".domain_faults") 522 .desc("Number of TLB faults due to domain restrictions") 523 ; 524 525 permsFaults 526 .name(name() + ".perms_faults") 527 .desc("Number of TLB faults due to permissions restrictions") 528 ; 529 530 instAccesses = instHits + instMisses; 531 readAccesses = readHits + readMisses; 532 writeAccesses = writeHits + writeMisses; 533 hits = readHits + writeHits + instHits; 534 misses = readMisses + writeMisses + instMisses; 535 accesses = readAccesses + writeAccesses + instAccesses; 536} 537 538void 539TLB::regProbePoints() 540{ 541 ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills")); 542} 543 544Fault 545TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 546 Translation *translation, bool &delay, bool timing) 547{ 548 updateMiscReg(tc); 549 Addr vaddr_tainted = req->getVaddr(); 550 Addr vaddr = 0; 551 if (aarch64) 552 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); 553 else 554 vaddr = vaddr_tainted; 555 uint32_t flags = req->getFlags(); 556 557 bool is_fetch = (mode == Execute); 558 bool is_write = (mode == Write); 559 560 if (!is_fetch) { 561 assert(flags & MustBeOne); 562 if (sctlr.a || !(flags & AllowUnaligned)) { 563 if (vaddr & mask(flags & AlignmentMask)) { 564 // LPAE is always disabled in SE mode 565 return std::make_shared<DataAbort>( 566 vaddr_tainted, 567 TlbEntry::DomainType::NoAccess, is_write, 568 ArmFault::AlignmentFault, isStage2, 569 ArmFault::VmsaTran); 570 } 571 } 572 } 573 574 Addr paddr; 575 Process *p = tc->getProcessPtr(); 576 577 if (!p->pTable->translate(vaddr, paddr)) 578 return std::make_shared<GenericPageTableFault>(vaddr_tainted); 579 req->setPaddr(paddr); 580 581 return NoFault; 582} 583 584Fault 585TLB::trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain) 586{ 587 return NoFault; 588} 589 590Fault 591TLB::walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, 592 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level) 593{ 594 return NoFault; 595} 596 597Fault 598TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) 599{ 600 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify 601 uint32_t flags = req->getFlags(); 602 bool is_fetch = (mode == Execute); 603 bool is_write = (mode == Write); 604 bool is_priv = isPriv && !(flags & UserMode); 605 606 // Get the translation type from the actuall table entry 607 ArmFault::TranMethod tranMethod = te->longDescFormat ? ArmFault::LpaeTran 608 : ArmFault::VmsaTran; 609 610 // If this is the second stage of translation and the request is for a 611 // stage 1 page table walk then we need to check the HCR.PTW bit. This 612 // allows us to generate a fault if the request targets an area marked 613 // as a device or strongly ordered. 614 if (isStage2 && req->isPTWalk() && hcr.ptw && 615 (te->mtype != TlbEntry::MemoryType::Normal)) { 616 return std::make_shared<DataAbort>( 617 vaddr, te->domain, is_write, 618 ArmFault::PermissionLL + te->lookupLevel, 619 isStage2, tranMethod); 620 } 621 622 // Generate an alignment fault for unaligned data accesses to device or 623 // strongly ordered memory 624 if (!is_fetch) { 625 if (te->mtype != TlbEntry::MemoryType::Normal) { 626 if (vaddr & mask(flags & AlignmentMask)) { 627 alignFaults++; 628 return std::make_shared<DataAbort>( 629 vaddr, TlbEntry::DomainType::NoAccess, is_write, 630 ArmFault::AlignmentFault, isStage2, 631 tranMethod); 632 } 633 } 634 } 635 636 if (te->nonCacheable) { 637 // Prevent prefetching from I/O devices. 638 if (req->isPrefetch()) { 639 // Here we can safely use the fault status for the short 640 // desc. format in all cases 641 return std::make_shared<PrefetchAbort>( 642 vaddr, ArmFault::PrefetchUncacheable, 643 isStage2, tranMethod); 644 } 645 } 646 647 if (!te->longDescFormat) { 648 switch ((dacr >> (static_cast<uint8_t>(te->domain) * 2)) & 0x3) { 649 case 0: 650 domainFaults++; 651 DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x" 652 " domain: %#x write:%d\n", dacr, 653 static_cast<uint8_t>(te->domain), is_write); 654 if (is_fetch) 655 return std::make_shared<PrefetchAbort>( 656 vaddr, 657 ArmFault::DomainLL + te->lookupLevel, 658 isStage2, tranMethod); 659 else 660 return std::make_shared<DataAbort>( 661 vaddr, te->domain, is_write, 662 ArmFault::DomainLL + te->lookupLevel, 663 isStage2, tranMethod); 664 case 1: 665 // Continue with permissions check 666 break; 667 case 2: 668 panic("UNPRED domain\n"); 669 case 3: 670 return NoFault; 671 } 672 } 673 674 // The 'ap' variable is AP[2:0] or {AP[2,1],1b'0}, i.e. always three bits 675 uint8_t ap = te->longDescFormat ? te->ap << 1 : te->ap; 676 uint8_t hap = te->hap; 677 678 if (sctlr.afe == 1 || te->longDescFormat) 679 ap |= 1; 680 681 bool abt; 682 bool isWritable = true; 683 // If this is a stage 2 access (eg for reading stage 1 page table entries) 684 // then don't perform the AP permissions check, we stil do the HAP check 685 // below. 686 if (isStage2) { 687 abt = false; 688 } else { 689 switch (ap) { 690 case 0: 691 DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", 692 (int)sctlr.rs); 693 if (!sctlr.xp) { 694 switch ((int)sctlr.rs) { 695 case 2: 696 abt = is_write; 697 break; 698 case 1: 699 abt = is_write || !is_priv; 700 break; 701 case 0: 702 case 3: 703 default: 704 abt = true; 705 break; 706 } 707 } else { 708 abt = true; 709 } 710 break; 711 case 1: 712 abt = !is_priv; 713 break; 714 case 2: 715 abt = !is_priv && is_write; 716 isWritable = is_priv; 717 break; 718 case 3: 719 abt = false; 720 break; 721 case 4: 722 panic("UNPRED premissions\n"); 723 case 5: 724 abt = !is_priv || is_write; 725 isWritable = false; 726 break; 727 case 6: 728 case 7: 729 abt = is_write; 730 isWritable = false; 731 break; 732 default: 733 panic("Unknown permissions %#x\n", ap); 734 } 735 } 736 737 bool hapAbt = is_write ? !(hap & 2) : !(hap & 1); 738 bool xn = te->xn || (isWritable && sctlr.wxn) || 739 (ap == 3 && sctlr.uwxn && is_priv); 740 if (is_fetch && (abt || xn || 741 (te->longDescFormat && te->pxn && !is_priv) || 742 (isSecure && te->ns && scr.sif))) { 743 permsFaults++; 744 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d " 745 "priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n", 746 ap, is_priv, is_write, te->ns, scr.sif,sctlr.afe); 747 return std::make_shared<PrefetchAbort>( 748 vaddr, 749 ArmFault::PermissionLL + te->lookupLevel, 750 isStage2, tranMethod); 751 } else if (abt | hapAbt) { 752 permsFaults++; 753 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 754 " write:%d\n", ap, is_priv, is_write); 755 return std::make_shared<DataAbort>( 756 vaddr, te->domain, is_write, 757 ArmFault::PermissionLL + te->lookupLevel, 758 isStage2 | !abt, tranMethod); 759 } 760 return NoFault; 761} 762 763 764Fault 765TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, 766 ThreadContext *tc) 767{ 768 assert(aarch64); 769 770 Addr vaddr_tainted = req->getVaddr(); 771 Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); 772 773 uint32_t flags = req->getFlags(); 774 bool is_fetch = (mode == Execute); 775 bool is_write = (mode == Write); 776 bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode); 777 778 updateMiscReg(tc, curTranType); 779 780 // If this is the second stage of translation and the request is for a 781 // stage 1 page table walk then we need to check the HCR.PTW bit. This 782 // allows us to generate a fault if the request targets an area marked 783 // as a device or strongly ordered. 784 if (isStage2 && req->isPTWalk() && hcr.ptw && 785 (te->mtype != TlbEntry::MemoryType::Normal)) { 786 return std::make_shared<DataAbort>( 787 vaddr_tainted, te->domain, is_write, 788 ArmFault::PermissionLL + te->lookupLevel, 789 isStage2, ArmFault::LpaeTran); 790 } 791 792 // Generate an alignment fault for unaligned accesses to device or 793 // strongly ordered memory 794 if (!is_fetch) { 795 if (te->mtype != TlbEntry::MemoryType::Normal) { 796 if (vaddr & mask(flags & AlignmentMask)) { 797 alignFaults++; 798 return std::make_shared<DataAbort>( 799 vaddr_tainted, 800 TlbEntry::DomainType::NoAccess, is_write, 801 ArmFault::AlignmentFault, isStage2, 802 ArmFault::LpaeTran); 803 } 804 } 805 } 806 807 if (te->nonCacheable) { 808 // Prevent prefetching from I/O devices. 809 if (req->isPrefetch()) { 810 // Here we can safely use the fault status for the short 811 // desc. format in all cases 812 return std::make_shared<PrefetchAbort>( 813 vaddr_tainted, 814 ArmFault::PrefetchUncacheable, 815 isStage2, ArmFault::LpaeTran); 816 } 817 } 818 819 uint8_t ap = 0x3 & (te->ap); // 2-bit access protection field 820 bool grant = false; 821 822 uint8_t xn = te->xn; 823 uint8_t pxn = te->pxn; 824 bool r = !is_write && !is_fetch; 825 bool w = is_write; 826 bool x = is_fetch; 827 DPRINTF(TLBVerbose, "Checking permissions: ap:%d, xn:%d, pxn:%d, r:%d, " 828 "w:%d, x:%d\n", ap, xn, pxn, r, w, x); 829 830 if (isStage2) { 831 panic("Virtualization in AArch64 state is not supported yet"); 832 } else { 833 switch (aarch64EL) { 834 case EL0: 835 { 836 uint8_t perm = (ap << 2) | (xn << 1) | pxn; 837 switch (perm) { 838 case 0: 839 case 1: 840 case 8: 841 case 9: 842 grant = x; 843 break; 844 case 4: 845 case 5: 846 grant = r || w || (x && !sctlr.wxn); 847 break; 848 case 6: 849 case 7: 850 grant = r || w; 851 break; 852 case 12: 853 case 13: 854 grant = r || x; 855 break; 856 case 14: 857 case 15: 858 grant = r; 859 break; 860 default: 861 grant = false; 862 } 863 } 864 break; 865 case EL1: 866 { 867 uint8_t perm = (ap << 2) | (xn << 1) | pxn; 868 switch (perm) { 869 case 0: 870 case 2: 871 grant = r || w || (x && !sctlr.wxn); 872 break; 873 case 1: 874 case 3: 875 case 4: 876 case 5: 877 case 6: 878 case 7: 879 // regions that are writeable at EL0 should not be 880 // executable at EL1 881 grant = r || w; 882 break; 883 case 8: 884 case 10: 885 case 12: 886 case 14: 887 grant = r || x; 888 break; 889 case 9: 890 case 11: 891 case 13: 892 case 15: 893 grant = r; 894 break; 895 default: 896 grant = false; 897 } 898 } 899 break; 900 case EL2: 901 case EL3: 902 { 903 uint8_t perm = (ap & 0x2) | xn; 904 switch (perm) { 905 case 0: 906 grant = r || w || (x && !sctlr.wxn) ; 907 break; 908 case 1: 909 grant = r || w; 910 break; 911 case 2: 912 grant = r || x; 913 break; 914 case 3: 915 grant = r; 916 break; 917 default: 918 grant = false; 919 } 920 } 921 break; 922 } 923 } 924 925 if (!grant) { 926 if (is_fetch) { 927 permsFaults++; 928 DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. " 929 "AP:%d priv:%d write:%d ns:%d sif:%d " 930 "sctlr.afe: %d\n", 931 ap, is_priv, is_write, te->ns, scr.sif, sctlr.afe); 932 // Use PC value instead of vaddr because vaddr might be aligned to 933 // cache line and should not be the address reported in FAR 934 return std::make_shared<PrefetchAbort>( 935 req->getPC(), 936 ArmFault::PermissionLL + te->lookupLevel, 937 isStage2, ArmFault::LpaeTran); 938 } else { 939 permsFaults++; 940 DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d " 941 "priv:%d write:%d\n", ap, is_priv, is_write); 942 return std::make_shared<DataAbort>( 943 vaddr_tainted, te->domain, is_write, 944 ArmFault::PermissionLL + te->lookupLevel, 945 isStage2, ArmFault::LpaeTran); 946 } 947 } 948 949 return NoFault; 950} 951 952Fault 953TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 954 Translation *translation, bool &delay, bool timing, 955 TLB::ArmTranslationType tranType, bool functional) 956{ 957 // No such thing as a functional timing access 958 assert(!(timing && functional)); 959 960 updateMiscReg(tc, tranType); 961 962 Addr vaddr_tainted = req->getVaddr(); 963 Addr vaddr = 0; 964 if (aarch64) 965 vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL); 966 else 967 vaddr = vaddr_tainted; 968 uint32_t flags = req->getFlags(); 969 970 bool is_fetch = (mode == Execute); 971 bool is_write = (mode == Write); 972 bool long_desc_format = aarch64 || (haveLPAE && ttbcr.eae); 973 ArmFault::TranMethod tranMethod = long_desc_format ? ArmFault::LpaeTran 974 : ArmFault::VmsaTran; 975 976 req->setAsid(asid); 977 978 DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n", 979 isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran); 980 981 DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " 982 "flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2, 983 scr, sctlr, flags, tranType); 984 985 // If this is a clrex instruction, provide a PA of 0 with no fault 986 // This will force the monitor to set the tracked address to 0 987 // a bit of a hack but this effectively clrears this processors monitor 988 if (flags & Request::CLEAR_LL){ 989 // @todo: check implications of security extensions 990 req->setPaddr(0); 991 req->setFlags(Request::UNCACHEABLE); 992 req->setFlags(Request::CLEAR_LL); 993 return NoFault; 994 } 995 if ((req->isInstFetch() && (!sctlr.i)) || 996 ((!req->isInstFetch()) && (!sctlr.c))){ 997 req->setFlags(Request::UNCACHEABLE); 998 } 999 if (!is_fetch) { 1000 assert(flags & MustBeOne); 1001 if (sctlr.a || !(flags & AllowUnaligned)) { 1002 if (vaddr & mask(flags & AlignmentMask)) { 1003 alignFaults++; 1004 return std::make_shared<DataAbort>( 1005 vaddr_tainted, 1006 TlbEntry::DomainType::NoAccess, is_write, 1007 ArmFault::AlignmentFault, isStage2, 1008 tranMethod); 1009 } 1010 } 1011 } 1012 1013 // If guest MMU is off or hcr.vm=0 go straight to stage2 1014 if ((isStage2 && !hcr.vm) || (!isStage2 && !sctlr.m)) { 1015 1016 req->setPaddr(vaddr); 1017 // When the MMU is off the security attribute corresponds to the 1018 // security state of the processor 1019 if (isSecure) 1020 req->setFlags(Request::SECURE); 1021 1022 // @todo: double check this (ARM ARM issue C B3.2.1) 1023 if (long_desc_format || sctlr.tre == 0) { 1024 req->setFlags(Request::UNCACHEABLE); 1025 } else { 1026 if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 1027 req->setFlags(Request::UNCACHEABLE); 1028 } 1029 1030 // Set memory attributes 1031 TlbEntry temp_te; 1032 temp_te.ns = !isSecure; 1033 if (isStage2 || hcr.dc == 0 || isSecure || 1034 (isHyp && !(tranType & S1CTran))) { 1035 1036 temp_te.mtype = is_fetch ? TlbEntry::MemoryType::Normal 1037 : TlbEntry::MemoryType::StronglyOrdered; 1038 temp_te.innerAttrs = 0x0; 1039 temp_te.outerAttrs = 0x0; 1040 temp_te.shareable = true; 1041 temp_te.outerShareable = true; 1042 } else { 1043 temp_te.mtype = TlbEntry::MemoryType::Normal; 1044 temp_te.innerAttrs = 0x3; 1045 temp_te.outerAttrs = 0x3; 1046 temp_te.shareable = false; 1047 temp_te.outerShareable = false; 1048 } 1049 temp_te.setAttributes(long_desc_format); 1050 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: " 1051 "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n", 1052 temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs, 1053 isStage2); 1054 setAttr(temp_te.attributes); 1055 1056 return trickBoxCheck(req, mode, TlbEntry::DomainType::NoAccess); 1057 } 1058 1059 DPRINTF(TLBVerbose, "Translating %s=%#x context=%d\n", 1060 isStage2 ? "IPA" : "VA", vaddr_tainted, asid); 1061 // Translation enabled 1062 1063 TlbEntry *te = NULL; 1064 TlbEntry mergeTe; 1065 Fault fault = getResultTe(&te, req, tc, mode, translation, timing, 1066 functional, &mergeTe); 1067 // only proceed if we have a valid table entry 1068 if ((te == NULL) && (fault == NoFault)) delay = true; 1069 1070 // If we have the table entry transfer some of the attributes to the 1071 // request that triggered the translation 1072 if (te != NULL) { 1073 // Set memory attributes 1074 DPRINTF(TLBVerbose, 1075 "Setting memory attributes: shareable: %d, innerAttrs: %d, " 1076 "outerAttrs: %d, mtype: %d, isStage2: %d\n", 1077 te->shareable, te->innerAttrs, te->outerAttrs, 1078 static_cast<uint8_t>(te->mtype), isStage2); 1079 setAttr(te->attributes); 1080 if (te->nonCacheable) { 1081 req->setFlags(Request::UNCACHEABLE); 1082 } 1083 1084 if (!bootUncacheability && 1085 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) { 1086 req->setFlags(Request::UNCACHEABLE); 1087 } 1088 1089 Addr pa = te->pAddr(vaddr); 1090 req->setPaddr(pa); 1091 1092 if (!bootUncacheability && 1093 ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(pa)) { 1094 req->setFlags(Request::UNCACHEABLE); 1095 } 1096 1097 if (isSecure && !te->ns) { 1098 req->setFlags(Request::SECURE); 1099 } 1100 if ((!is_fetch) && (vaddr & mask(flags & AlignmentMask)) && 1101 (te->mtype != TlbEntry::MemoryType::Normal)) { 1102 // Unaligned accesses to Device memory should always cause an 1103 // abort regardless of sctlr.a 1104 alignFaults++; 1105 return std::make_shared<DataAbort>( 1106 vaddr_tainted, 1107 TlbEntry::DomainType::NoAccess, is_write, 1108 ArmFault::AlignmentFault, isStage2, 1109 tranMethod); 1110 } 1111 1112 // Check for a trickbox generated address fault 1113 if (fault == NoFault) { 1114 fault = trickBoxCheck(req, mode, te->domain); 1115 } 1116 } 1117 1118 // Generate Illegal Inst Set State fault if IL bit is set in CPSR 1119 if (fault == NoFault) { 1120 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1121 if (aarch64 && is_fetch && cpsr.il == 1) { 1122 return std::make_shared<IllegalInstSetStateFault>(); 1123 } 1124 } 1125 1126 return fault; 1127} 1128 1129Fault 1130TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode, 1131 TLB::ArmTranslationType tranType) 1132{ 1133 updateMiscReg(tc, tranType); 1134 1135 if (directToStage2) { 1136 assert(stage2Tlb); 1137 return stage2Tlb->translateAtomic(req, tc, mode, tranType); 1138 } 1139 1140 bool delay = false; 1141 Fault fault; 1142 if (FullSystem) 1143 fault = translateFs(req, tc, mode, NULL, delay, false, tranType); 1144 else 1145 fault = translateSe(req, tc, mode, NULL, delay, false); 1146 assert(!delay); 1147 return fault; 1148} 1149 1150Fault 1151TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode, 1152 TLB::ArmTranslationType tranType) 1153{ 1154 updateMiscReg(tc, tranType); 1155 1156 if (directToStage2) { 1157 assert(stage2Tlb); 1158 return stage2Tlb->translateFunctional(req, tc, mode, tranType); 1159 } 1160 1161 bool delay = false; 1162 Fault fault; 1163 if (FullSystem) 1164 fault = translateFs(req, tc, mode, NULL, delay, false, tranType, true); 1165 else 1166 fault = translateSe(req, tc, mode, NULL, delay, false); 1167 assert(!delay); 1168 return fault; 1169} 1170 1171Fault 1172TLB::translateTiming(RequestPtr req, ThreadContext *tc, 1173 Translation *translation, Mode mode, TLB::ArmTranslationType tranType) 1174{ 1175 updateMiscReg(tc, tranType); 1176 1177 if (directToStage2) { 1178 assert(stage2Tlb); 1179 return stage2Tlb->translateTiming(req, tc, translation, mode, tranType); 1180 } 1181 1182 assert(translation); 1183 1184 return translateComplete(req, tc, translation, mode, tranType, isStage2); 1185} 1186 1187Fault 1188TLB::translateComplete(RequestPtr req, ThreadContext *tc, 1189 Translation *translation, Mode mode, TLB::ArmTranslationType tranType, 1190 bool callFromS2) 1191{ 1192 bool delay = false; 1193 Fault fault; 1194 if (FullSystem) 1195 fault = translateFs(req, tc, mode, translation, delay, true, tranType); 1196 else 1197 fault = translateSe(req, tc, mode, translation, delay, true); 1198 DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 1199 NoFault); 1200 // If we have a translation, and we're not in the middle of doing a stage 1201 // 2 translation tell the translation that we've either finished or its 1202 // going to take a while. By not doing this when we're in the middle of a 1203 // stage 2 translation we prevent marking the translation as delayed twice, 1204 // one when the translation starts and again when the stage 1 translation 1205 // completes. 1206 if (translation && (callFromS2 || !stage2Req || req->hasPaddr() || fault != NoFault)) { 1207 if (!delay) 1208 translation->finish(fault, req, tc, mode); 1209 else 1210 translation->markDelayed(); 1211 } 1212 return fault; 1213} 1214 1215BaseMasterPort* 1216TLB::getMasterPort() 1217{ 1218 return &tableWalker->getMasterPort("port"); 1219} 1220 1221DmaPort& 1222TLB::getWalkerPort() 1223{ 1224 return tableWalker->getWalkerPort(); 1225} 1226 1227void 1228TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) 1229{ 1230 // check if the regs have changed, or the translation mode is different. 1231 // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle 1232 // one type of translation anyway 1233 if (miscRegValid && ((tranType == curTranType) || isStage2)) { 1234 return; 1235 } 1236 1237 DPRINTF(TLBVerbose, "TLB variables changed!\n"); 1238 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1239 // Dependencies: SCR/SCR_EL3, CPSR 1240 isSecure = inSecureState(tc); 1241 isSecure &= (tranType & HypMode) == 0; 1242 isSecure &= (tranType & S1S2NsTran) == 0; 1243 aarch64 = !cpsr.width; 1244 if (aarch64) { // AArch64 1245 aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el; 1246 switch (aarch64EL) { 1247 case EL0: 1248 case EL1: 1249 { 1250 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 1251 ttbcr = tc->readMiscReg(MISCREG_TCR_EL1); 1252 uint64_t ttbr_asid = ttbcr.a1 ? 1253 tc->readMiscReg(MISCREG_TTBR1_EL1) : 1254 tc->readMiscReg(MISCREG_TTBR0_EL1); 1255 asid = bits(ttbr_asid, 1256 (haveLargeAsid64 && ttbcr.as) ? 63 : 55, 48); 1257 } 1258 break; 1259 case EL2: 1260 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2); 1261 ttbcr = tc->readMiscReg(MISCREG_TCR_EL2); 1262 asid = -1; 1263 break; 1264 case EL3: 1265 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3); 1266 ttbcr = tc->readMiscReg(MISCREG_TCR_EL3); 1267 asid = -1; 1268 break; 1269 } 1270 scr = tc->readMiscReg(MISCREG_SCR_EL3); 1271 isPriv = aarch64EL != EL0; 1272 // @todo: modify this behaviour to support Virtualization in 1273 // AArch64 1274 vmid = 0; 1275 isHyp = false; 1276 directToStage2 = false; 1277 stage2Req = false; 1278 } else { // AArch32 1279 sctlr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc, 1280 !isSecure)); 1281 ttbcr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR, tc, 1282 !isSecure)); 1283 scr = tc->readMiscReg(MISCREG_SCR); 1284 isPriv = cpsr.mode != MODE_USER; 1285 if (haveLPAE && ttbcr.eae) { 1286 // Long-descriptor translation table format in use 1287 uint64_t ttbr_asid = tc->readMiscReg( 1288 flattenMiscRegNsBanked(ttbcr.a1 ? MISCREG_TTBR1 1289 : MISCREG_TTBR0, 1290 tc, !isSecure)); 1291 asid = bits(ttbr_asid, 55, 48); 1292 } else { 1293 // Short-descriptor translation table format in use 1294 CONTEXTIDR context_id = tc->readMiscReg(flattenMiscRegNsBanked( 1295 MISCREG_CONTEXTIDR, tc,!isSecure)); 1296 asid = context_id.asid; 1297 } 1298 prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, tc, 1299 !isSecure)); 1300 nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, tc, 1301 !isSecure)); 1302 dacr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_DACR, tc, 1303 !isSecure)); 1304 hcr = tc->readMiscReg(MISCREG_HCR); 1305 1306 if (haveVirtualization) { 1307 vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48); 1308 isHyp = cpsr.mode == MODE_HYP; 1309 isHyp |= tranType & HypMode; 1310 isHyp &= (tranType & S1S2NsTran) == 0; 1311 isHyp &= (tranType & S1CTran) == 0; 1312 if (isHyp) { 1313 sctlr = tc->readMiscReg(MISCREG_HSCTLR); 1314 } 1315 // Work out if we should skip the first stage of translation and go 1316 // directly to stage 2. This value is cached so we don't have to 1317 // compute it for every translation. 1318 stage2Req = hcr.vm && !isStage2 && !isHyp && !isSecure && 1319 !(tranType & S1CTran); 1320 directToStage2 = stage2Req && !sctlr.m; 1321 } else { 1322 vmid = 0; 1323 stage2Req = false; 1324 isHyp = false; 1325 directToStage2 = false; 1326 } 1327 } 1328 miscRegValid = true; 1329 curTranType = tranType; 1330} 1331 1332Fault 1333TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 1334 Translation *translation, bool timing, bool functional, 1335 bool is_secure, TLB::ArmTranslationType tranType) 1336{ 1337 bool is_fetch = (mode == Execute); 1338 bool is_write = (mode == Write); 1339 1340 Addr vaddr_tainted = req->getVaddr(); 1341 Addr vaddr = 0; 1342 ExceptionLevel target_el = aarch64 ? aarch64EL : EL1; 1343 if (aarch64) { 1344 vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el); 1345 } else { 1346 vaddr = vaddr_tainted; 1347 } 1348 *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 1349 if (*te == NULL) { 1350 if (req->isPrefetch()) { 1351 // if the request is a prefetch don't attempt to fill the TLB or go 1352 // any further with the memory access (here we can safely use the 1353 // fault status for the short desc. format in all cases) 1354 prefetchFaults++; 1355 return std::make_shared<PrefetchAbort>( 1356 vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2); 1357 } 1358 1359 if (is_fetch) 1360 instMisses++; 1361 else if (is_write) 1362 writeMisses++; 1363 else 1364 readMisses++; 1365 1366 // start translation table walk, pass variables rather than 1367 // re-retreaving in table walker for speed 1368 DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d:%d)\n", 1369 vaddr_tainted, asid, vmid); 1370 Fault fault; 1371 fault = tableWalker->walk(req, tc, asid, vmid, isHyp, mode, 1372 translation, timing, functional, is_secure, 1373 tranType); 1374 // for timing mode, return and wait for table walk, 1375 if (timing || fault != NoFault) { 1376 return fault; 1377 } 1378 1379 *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el); 1380 if (!*te) 1381 printTlb(); 1382 assert(*te); 1383 } else { 1384 if (is_fetch) 1385 instHits++; 1386 else if (is_write) 1387 writeHits++; 1388 else 1389 readHits++; 1390 } 1391 return NoFault; 1392} 1393 1394Fault 1395TLB::getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, 1396 Translation *translation, bool timing, bool functional, 1397 TlbEntry *mergeTe) 1398{ 1399 Fault fault; 1400 TlbEntry *s1Te = NULL; 1401 1402 Addr vaddr_tainted = req->getVaddr(); 1403 1404 // Get the stage 1 table entry 1405 fault = getTE(&s1Te, req, tc, mode, translation, timing, functional, 1406 isSecure, curTranType); 1407 // only proceed if we have a valid table entry 1408 if ((s1Te != NULL) && (fault == NoFault)) { 1409 // Check stage 1 permissions before checking stage 2 1410 if (aarch64) 1411 fault = checkPermissions64(s1Te, req, mode, tc); 1412 else 1413 fault = checkPermissions(s1Te, req, mode); 1414 if (stage2Req & (fault == NoFault)) { 1415 Stage2LookUp *s2Lookup = new Stage2LookUp(this, stage2Tlb, *s1Te, 1416 req, translation, mode, timing, functional, curTranType); 1417 fault = s2Lookup->getTe(tc, mergeTe); 1418 if (s2Lookup->isComplete()) { 1419 *te = mergeTe; 1420 // We've finished with the lookup so delete it 1421 delete s2Lookup; 1422 } else { 1423 // The lookup hasn't completed, so we can't delete it now. We 1424 // get round this by asking the object to self delete when the 1425 // translation is complete. 1426 s2Lookup->setSelfDelete(); 1427 } 1428 } else { 1429 // This case deals with an S1 hit (or bypass), followed by 1430 // an S2 hit-but-perms issue 1431 if (isStage2) { 1432 DPRINTF(TLBVerbose, "s2TLB: reqVa %#x, reqPa %#x, fault %p\n", 1433 vaddr_tainted, req->hasPaddr() ? req->getPaddr() : ~0, fault); 1434 if (fault != NoFault) { 1435 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1436 armFault->annotate(ArmFault::S1PTW, false); 1437 armFault->annotate(ArmFault::OVA, vaddr_tainted); 1438 } 1439 } 1440 *te = s1Te; 1441 } 1442 } 1443 return fault; 1444} 1445 1446ArmISA::TLB * 1447ArmTLBParams::create() 1448{ 1449 return new ArmISA::TLB(this); 1450} 1451