tlb.cc revision 9439
16019Shines@cs.fsu.edu/* 29439SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 417399SAli.Saidi@ARM.com * Nathan Binkert 426019Shines@cs.fsu.edu * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#include <string> 466019Shines@cs.fsu.edu#include <vector> 476019Shines@cs.fsu.edu 486116Snate@binkert.org#include "arch/arm/faults.hh" 496019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 508782Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 518756Sgblack@eecs.umich.edu#include "arch/arm/table_walker.hh" 526019Shines@cs.fsu.edu#include "arch/arm/tlb.hh" 536019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 546019Shines@cs.fsu.edu#include "base/inifile.hh" 556019Shines@cs.fsu.edu#include "base/str.hh" 566019Shines@cs.fsu.edu#include "base/trace.hh" 576019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 588232Snate@binkert.org#include "debug/Checkpoint.hh" 598232Snate@binkert.org#include "debug/TLB.hh" 608232Snate@binkert.org#include "debug/TLBVerbose.hh" 616116Snate@binkert.org#include "mem/page_table.hh" 626116Snate@binkert.org#include "params/ArmTLB.hh" 638756Sgblack@eecs.umich.edu#include "sim/full_system.hh" 646019Shines@cs.fsu.edu#include "sim/process.hh" 656019Shines@cs.fsu.edu 666019Shines@cs.fsu.eduusing namespace std; 676019Shines@cs.fsu.eduusing namespace ArmISA; 686019Shines@cs.fsu.edu 696019Shines@cs.fsu.eduTLB::TLB(const Params *p) 708756Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size) , tableWalker(p->walker), 718756Sgblack@eecs.umich.edu rangeMRU(1), bootUncacheability(false), miscRegValid(false) 726019Shines@cs.fsu.edu{ 737404SAli.Saidi@ARM.com table = new TlbEntry[size]; 748352SChander.Sudanthi@ARM.com memset(table, 0, sizeof(TlbEntry) * size); 757399SAli.Saidi@ARM.com 767404SAli.Saidi@ARM.com tableWalker->setTlb(this); 776019Shines@cs.fsu.edu} 786019Shines@cs.fsu.edu 796019Shines@cs.fsu.eduTLB::~TLB() 806019Shines@cs.fsu.edu{ 816019Shines@cs.fsu.edu if (table) 826019Shines@cs.fsu.edu delete [] table; 836019Shines@cs.fsu.edu} 846019Shines@cs.fsu.edu 857694SAli.Saidi@ARM.combool 867694SAli.Saidi@ARM.comTLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 877694SAli.Saidi@ARM.com{ 887749SAli.Saidi@ARM.com if (!miscRegValid) 897749SAli.Saidi@ARM.com updateMiscReg(tc); 907749SAli.Saidi@ARM.com TlbEntry *e = lookup(va, contextId, true); 917694SAli.Saidi@ARM.com if (!e) 927694SAli.Saidi@ARM.com return false; 937694SAli.Saidi@ARM.com pa = e->pAddr(va); 947694SAli.Saidi@ARM.com return true; 957694SAli.Saidi@ARM.com} 967694SAli.Saidi@ARM.com 977404SAli.Saidi@ARM.comTlbEntry* 987694SAli.Saidi@ARM.comTLB::lookup(Addr va, uint8_t cid, bool functional) 996019Shines@cs.fsu.edu{ 1007404SAli.Saidi@ARM.com 1017404SAli.Saidi@ARM.com TlbEntry *retval = NULL; 1027404SAli.Saidi@ARM.com 1037697SAli.Saidi@ARM.com // Maitaining LRU array 1047404SAli.Saidi@ARM.com 1057404SAli.Saidi@ARM.com int x = 0; 1067404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 1077404SAli.Saidi@ARM.com if (table[x].match(va, cid)) { 1087404SAli.Saidi@ARM.com 1097697SAli.Saidi@ARM.com // We only move the hit entry ahead when the position is higher than rangeMRU 1107697SAli.Saidi@ARM.com if (x > rangeMRU) { 1117697SAli.Saidi@ARM.com TlbEntry tmp_entry = table[x]; 1127697SAli.Saidi@ARM.com for(int i = x; i > 0; i--) 1137697SAli.Saidi@ARM.com table[i] = table[i-1]; 1147697SAli.Saidi@ARM.com table[0] = tmp_entry; 1157697SAli.Saidi@ARM.com retval = &table[0]; 1167697SAli.Saidi@ARM.com } else { 1177697SAli.Saidi@ARM.com retval = &table[x]; 1187697SAli.Saidi@ARM.com } 1197404SAli.Saidi@ARM.com break; 1207404SAli.Saidi@ARM.com } 1217404SAli.Saidi@ARM.com x++; 1227404SAli.Saidi@ARM.com } 1237404SAli.Saidi@ARM.com 1247404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 1257404SAli.Saidi@ARM.com va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 1267404SAli.Saidi@ARM.com retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 1277404SAli.Saidi@ARM.com retval ? retval->ap : 0); 1287404SAli.Saidi@ARM.com ; 1297404SAli.Saidi@ARM.com return retval; 1306019Shines@cs.fsu.edu} 1316019Shines@cs.fsu.edu 1326019Shines@cs.fsu.edu// insert a new TLB entry 1336019Shines@cs.fsu.eduvoid 1347404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1356019Shines@cs.fsu.edu{ 1367404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 1377404SAli.Saidi@ARM.com " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 1387404SAli.Saidi@ARM.com " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 1397404SAli.Saidi@ARM.com entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 1407404SAli.Saidi@ARM.com entry.xn, entry.ap, entry.domain); 1417404SAli.Saidi@ARM.com 1427697SAli.Saidi@ARM.com if (table[size-1].valid) 1437404SAli.Saidi@ARM.com DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 1447697SAli.Saidi@ARM.com table[size-1].vpn << table[size-1].N, table[size-1].asid, 1457697SAli.Saidi@ARM.com table[size-1].pfn << table[size-1].N, table[size-1].size, 1467697SAli.Saidi@ARM.com table[size-1].ap); 1477404SAli.Saidi@ARM.com 1487697SAli.Saidi@ARM.com //inserting to MRU position and evicting the LRU one 1497404SAli.Saidi@ARM.com 1507697SAli.Saidi@ARM.com for(int i = size-1; i > 0; i--) 1517697SAli.Saidi@ARM.com table[i] = table[i-1]; 1527697SAli.Saidi@ARM.com table[0] = entry; 1537734SAli.Saidi@ARM.com 1547734SAli.Saidi@ARM.com inserts++; 1556019Shines@cs.fsu.edu} 1566019Shines@cs.fsu.edu 1576019Shines@cs.fsu.eduvoid 1587404SAli.Saidi@ARM.comTLB::printTlb() 1597404SAli.Saidi@ARM.com{ 1607404SAli.Saidi@ARM.com int x = 0; 1617404SAli.Saidi@ARM.com TlbEntry *te; 1627404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 1637404SAli.Saidi@ARM.com while (x < size) { 1647404SAli.Saidi@ARM.com te = &table[x]; 1657404SAli.Saidi@ARM.com if (te->valid) 1667404SAli.Saidi@ARM.com DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 1677404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1687404SAli.Saidi@ARM.com x++; 1697404SAli.Saidi@ARM.com } 1707404SAli.Saidi@ARM.com} 1717404SAli.Saidi@ARM.com 1727404SAli.Saidi@ARM.com 1737404SAli.Saidi@ARM.comvoid 1746019Shines@cs.fsu.eduTLB::flushAll() 1756019Shines@cs.fsu.edu{ 1767404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all TLB entries\n"); 1777404SAli.Saidi@ARM.com int x = 0; 1787404SAli.Saidi@ARM.com TlbEntry *te; 1797404SAli.Saidi@ARM.com while (x < size) { 1807404SAli.Saidi@ARM.com te = &table[x]; 1817734SAli.Saidi@ARM.com if (te->valid) { 1827404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 1837404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1847734SAli.Saidi@ARM.com flushedEntries++; 1857734SAli.Saidi@ARM.com } 1867404SAli.Saidi@ARM.com x++; 1877404SAli.Saidi@ARM.com } 1887404SAli.Saidi@ARM.com 1898352SChander.Sudanthi@ARM.com memset(table, 0, sizeof(TlbEntry) * size); 1907734SAli.Saidi@ARM.com 1917734SAli.Saidi@ARM.com flushTlb++; 1926019Shines@cs.fsu.edu} 1936019Shines@cs.fsu.edu 1947404SAli.Saidi@ARM.com 1957404SAli.Saidi@ARM.comvoid 1967404SAli.Saidi@ARM.comTLB::flushMvaAsid(Addr mva, uint64_t asn) 1977404SAli.Saidi@ARM.com{ 1987404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 1997404SAli.Saidi@ARM.com TlbEntry *te; 2007404SAli.Saidi@ARM.com 2017404SAli.Saidi@ARM.com te = lookup(mva, asn); 2027404SAli.Saidi@ARM.com while (te != NULL) { 2037404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2047404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2057404SAli.Saidi@ARM.com te->valid = false; 2067734SAli.Saidi@ARM.com flushedEntries++; 2077404SAli.Saidi@ARM.com te = lookup(mva,asn); 2087404SAli.Saidi@ARM.com } 2097734SAli.Saidi@ARM.com flushTlbMvaAsid++; 2107404SAli.Saidi@ARM.com} 2117404SAli.Saidi@ARM.com 2127404SAli.Saidi@ARM.comvoid 2137404SAli.Saidi@ARM.comTLB::flushAsid(uint64_t asn) 2147404SAli.Saidi@ARM.com{ 2157404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 2167404SAli.Saidi@ARM.com 2177404SAli.Saidi@ARM.com int x = 0; 2187404SAli.Saidi@ARM.com TlbEntry *te; 2197404SAli.Saidi@ARM.com 2207404SAli.Saidi@ARM.com while (x < size) { 2217404SAli.Saidi@ARM.com te = &table[x]; 2227404SAli.Saidi@ARM.com if (te->asid == asn) { 2237404SAli.Saidi@ARM.com te->valid = false; 2247404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2257404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2267734SAli.Saidi@ARM.com flushedEntries++; 2277404SAli.Saidi@ARM.com } 2287404SAli.Saidi@ARM.com x++; 2297404SAli.Saidi@ARM.com } 2307734SAli.Saidi@ARM.com flushTlbAsid++; 2317404SAli.Saidi@ARM.com} 2327404SAli.Saidi@ARM.com 2337404SAli.Saidi@ARM.comvoid 2347404SAli.Saidi@ARM.comTLB::flushMva(Addr mva) 2357404SAli.Saidi@ARM.com{ 2367404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 2377404SAli.Saidi@ARM.com 2387404SAli.Saidi@ARM.com int x = 0; 2397404SAli.Saidi@ARM.com TlbEntry *te; 2407404SAli.Saidi@ARM.com 2417404SAli.Saidi@ARM.com while (x < size) { 2427404SAli.Saidi@ARM.com te = &table[x]; 2437404SAli.Saidi@ARM.com Addr v = te->vpn << te->N; 2447404SAli.Saidi@ARM.com if (mva >= v && mva < v + te->size) { 2457404SAli.Saidi@ARM.com te->valid = false; 2467404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2477404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2487734SAli.Saidi@ARM.com flushedEntries++; 2497404SAli.Saidi@ARM.com } 2507404SAli.Saidi@ARM.com x++; 2517404SAli.Saidi@ARM.com } 2527734SAli.Saidi@ARM.com flushTlbMva++; 2537404SAli.Saidi@ARM.com} 2547404SAli.Saidi@ARM.com 2556019Shines@cs.fsu.eduvoid 2569439SAndreas.Sandberg@ARM.comTLB::drainResume() 2579439SAndreas.Sandberg@ARM.com{ 2589439SAndreas.Sandberg@ARM.com // We might have unserialized something or switched CPUs, so make 2599439SAndreas.Sandberg@ARM.com // sure to re-read the misc regs. 2609439SAndreas.Sandberg@ARM.com miscRegValid = false; 2619439SAndreas.Sandberg@ARM.com} 2629439SAndreas.Sandberg@ARM.com 2639439SAndreas.Sandberg@ARM.comvoid 2646019Shines@cs.fsu.eduTLB::serialize(ostream &os) 2656019Shines@cs.fsu.edu{ 2667733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 2677733SAli.Saidi@ARM.com 2687733SAli.Saidi@ARM.com SERIALIZE_SCALAR(_attr); 2698353SAli.Saidi@ARM.com 2708353SAli.Saidi@ARM.com int num_entries = size; 2718353SAli.Saidi@ARM.com SERIALIZE_SCALAR(num_entries); 2727733SAli.Saidi@ARM.com for(int i = 0; i < size; i++){ 2737733SAli.Saidi@ARM.com nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 2747733SAli.Saidi@ARM.com table[i].serialize(os); 2757733SAli.Saidi@ARM.com } 2766019Shines@cs.fsu.edu} 2776019Shines@cs.fsu.edu 2786019Shines@cs.fsu.eduvoid 2796019Shines@cs.fsu.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2806019Shines@cs.fsu.edu{ 2817733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 2826019Shines@cs.fsu.edu 2837733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_attr); 2848353SAli.Saidi@ARM.com int num_entries; 2858353SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(num_entries); 2868353SAli.Saidi@ARM.com for(int i = 0; i < min(size, num_entries); i++){ 2877733SAli.Saidi@ARM.com table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 2887733SAli.Saidi@ARM.com } 2896019Shines@cs.fsu.edu} 2906019Shines@cs.fsu.edu 2916019Shines@cs.fsu.eduvoid 2926019Shines@cs.fsu.eduTLB::regStats() 2936019Shines@cs.fsu.edu{ 2947734SAli.Saidi@ARM.com instHits 2957734SAli.Saidi@ARM.com .name(name() + ".inst_hits") 2967734SAli.Saidi@ARM.com .desc("ITB inst hits") 2977734SAli.Saidi@ARM.com ; 2987734SAli.Saidi@ARM.com 2997734SAli.Saidi@ARM.com instMisses 3007734SAli.Saidi@ARM.com .name(name() + ".inst_misses") 3017734SAli.Saidi@ARM.com .desc("ITB inst misses") 3027734SAli.Saidi@ARM.com ; 3037734SAli.Saidi@ARM.com 3047734SAli.Saidi@ARM.com instAccesses 3057734SAli.Saidi@ARM.com .name(name() + ".inst_accesses") 3067734SAli.Saidi@ARM.com .desc("ITB inst accesses") 3077734SAli.Saidi@ARM.com ; 3087734SAli.Saidi@ARM.com 3097734SAli.Saidi@ARM.com readHits 3106019Shines@cs.fsu.edu .name(name() + ".read_hits") 3116019Shines@cs.fsu.edu .desc("DTB read hits") 3126019Shines@cs.fsu.edu ; 3136019Shines@cs.fsu.edu 3147734SAli.Saidi@ARM.com readMisses 3156019Shines@cs.fsu.edu .name(name() + ".read_misses") 3166019Shines@cs.fsu.edu .desc("DTB read misses") 3176019Shines@cs.fsu.edu ; 3186019Shines@cs.fsu.edu 3197734SAli.Saidi@ARM.com readAccesses 3206019Shines@cs.fsu.edu .name(name() + ".read_accesses") 3216019Shines@cs.fsu.edu .desc("DTB read accesses") 3226019Shines@cs.fsu.edu ; 3236019Shines@cs.fsu.edu 3247734SAli.Saidi@ARM.com writeHits 3256019Shines@cs.fsu.edu .name(name() + ".write_hits") 3266019Shines@cs.fsu.edu .desc("DTB write hits") 3276019Shines@cs.fsu.edu ; 3286019Shines@cs.fsu.edu 3297734SAli.Saidi@ARM.com writeMisses 3306019Shines@cs.fsu.edu .name(name() + ".write_misses") 3316019Shines@cs.fsu.edu .desc("DTB write misses") 3326019Shines@cs.fsu.edu ; 3336019Shines@cs.fsu.edu 3347734SAli.Saidi@ARM.com writeAccesses 3356019Shines@cs.fsu.edu .name(name() + ".write_accesses") 3366019Shines@cs.fsu.edu .desc("DTB write accesses") 3376019Shines@cs.fsu.edu ; 3386019Shines@cs.fsu.edu 3396019Shines@cs.fsu.edu hits 3406019Shines@cs.fsu.edu .name(name() + ".hits") 3416019Shines@cs.fsu.edu .desc("DTB hits") 3426019Shines@cs.fsu.edu ; 3436019Shines@cs.fsu.edu 3446019Shines@cs.fsu.edu misses 3456019Shines@cs.fsu.edu .name(name() + ".misses") 3466019Shines@cs.fsu.edu .desc("DTB misses") 3476019Shines@cs.fsu.edu ; 3486019Shines@cs.fsu.edu 3496019Shines@cs.fsu.edu accesses 3506019Shines@cs.fsu.edu .name(name() + ".accesses") 3516019Shines@cs.fsu.edu .desc("DTB accesses") 3526019Shines@cs.fsu.edu ; 3536019Shines@cs.fsu.edu 3547734SAli.Saidi@ARM.com flushTlb 3557734SAli.Saidi@ARM.com .name(name() + ".flush_tlb") 3567734SAli.Saidi@ARM.com .desc("Number of times complete TLB was flushed") 3577734SAli.Saidi@ARM.com ; 3587734SAli.Saidi@ARM.com 3597734SAli.Saidi@ARM.com flushTlbMva 3607734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva") 3617734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA") 3627734SAli.Saidi@ARM.com ; 3637734SAli.Saidi@ARM.com 3647734SAli.Saidi@ARM.com flushTlbMvaAsid 3657734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva_asid") 3667734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA & ASID") 3677734SAli.Saidi@ARM.com ; 3687734SAli.Saidi@ARM.com 3697734SAli.Saidi@ARM.com flushTlbAsid 3707734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_asid") 3717734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by ASID") 3727734SAli.Saidi@ARM.com ; 3737734SAli.Saidi@ARM.com 3747734SAli.Saidi@ARM.com flushedEntries 3757734SAli.Saidi@ARM.com .name(name() + ".flush_entries") 3767734SAli.Saidi@ARM.com .desc("Number of entries that have been flushed from TLB") 3777734SAli.Saidi@ARM.com ; 3787734SAli.Saidi@ARM.com 3797734SAli.Saidi@ARM.com alignFaults 3807734SAli.Saidi@ARM.com .name(name() + ".align_faults") 3817734SAli.Saidi@ARM.com .desc("Number of TLB faults due to alignment restrictions") 3827734SAli.Saidi@ARM.com ; 3837734SAli.Saidi@ARM.com 3847734SAli.Saidi@ARM.com prefetchFaults 3857734SAli.Saidi@ARM.com .name(name() + ".prefetch_faults") 3867734SAli.Saidi@ARM.com .desc("Number of TLB faults due to prefetch") 3877734SAli.Saidi@ARM.com ; 3887734SAli.Saidi@ARM.com 3897734SAli.Saidi@ARM.com domainFaults 3907734SAli.Saidi@ARM.com .name(name() + ".domain_faults") 3917734SAli.Saidi@ARM.com .desc("Number of TLB faults due to domain restrictions") 3927734SAli.Saidi@ARM.com ; 3937734SAli.Saidi@ARM.com 3947734SAli.Saidi@ARM.com permsFaults 3957734SAli.Saidi@ARM.com .name(name() + ".perms_faults") 3967734SAli.Saidi@ARM.com .desc("Number of TLB faults due to permissions restrictions") 3977734SAli.Saidi@ARM.com ; 3987734SAli.Saidi@ARM.com 3997734SAli.Saidi@ARM.com instAccesses = instHits + instMisses; 4007734SAli.Saidi@ARM.com readAccesses = readHits + readMisses; 4017734SAli.Saidi@ARM.com writeAccesses = writeHits + writeMisses; 4027734SAli.Saidi@ARM.com hits = readHits + writeHits + instHits; 4037734SAli.Saidi@ARM.com misses = readMisses + writeMisses + instMisses; 4047734SAli.Saidi@ARM.com accesses = readAccesses + writeAccesses + instAccesses; 4056019Shines@cs.fsu.edu} 4066019Shines@cs.fsu.edu 4077404SAli.Saidi@ARM.comFault 4087404SAli.Saidi@ARM.comTLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 4097404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing) 4107404SAli.Saidi@ARM.com{ 4117749SAli.Saidi@ARM.com if (!miscRegValid) 4127749SAli.Saidi@ARM.com updateMiscReg(tc); 4137720Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 4147294Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 4157294Sgblack@eecs.umich.edu 4167404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 4177404SAli.Saidi@ARM.com bool is_write = (mode == Write); 4187404SAli.Saidi@ARM.com 4197404SAli.Saidi@ARM.com if (!is_fetch) { 4207294Sgblack@eecs.umich.edu assert(flags & MustBeOne); 4217404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 4227404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 4237404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 4247294Sgblack@eecs.umich.edu } 4257294Sgblack@eecs.umich.edu } 4267294Sgblack@eecs.umich.edu } 4276019Shines@cs.fsu.edu 4287093Sgblack@eecs.umich.edu Addr paddr; 4297404SAli.Saidi@ARM.com Process *p = tc->getProcessPtr(); 4307404SAli.Saidi@ARM.com 4317093Sgblack@eecs.umich.edu if (!p->pTable->translate(vaddr, paddr)) 4327093Sgblack@eecs.umich.edu return Fault(new GenericPageTableFault(vaddr)); 4337093Sgblack@eecs.umich.edu req->setPaddr(paddr); 4346019Shines@cs.fsu.edu 4356019Shines@cs.fsu.edu return NoFault; 4367404SAli.Saidi@ARM.com} 4377404SAli.Saidi@ARM.com 4387404SAli.Saidi@ARM.comFault 4397406SAli.Saidi@ARM.comTLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 4407406SAli.Saidi@ARM.com{ 4417406SAli.Saidi@ARM.com return NoFault; 4427406SAli.Saidi@ARM.com} 4437406SAli.Saidi@ARM.com 4447406SAli.Saidi@ARM.comFault 4457406SAli.Saidi@ARM.comTLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 4467406SAli.Saidi@ARM.com bool is_write, uint8_t domain, bool sNp) 4477406SAli.Saidi@ARM.com{ 4487406SAli.Saidi@ARM.com return NoFault; 4497406SAli.Saidi@ARM.com} 4507406SAli.Saidi@ARM.com 4517406SAli.Saidi@ARM.comFault 4527404SAli.Saidi@ARM.comTLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 4538733Sgeoffrey.blake@arm.com Translation *translation, bool &delay, bool timing, bool functional) 4547404SAli.Saidi@ARM.com{ 4558733Sgeoffrey.blake@arm.com // No such thing as a functional timing access 4568733Sgeoffrey.blake@arm.com assert(!(timing && functional)); 4578733Sgeoffrey.blake@arm.com 4588202SAli.Saidi@ARM.com if (!miscRegValid) { 4597749SAli.Saidi@ARM.com updateMiscReg(tc); 4608202SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "TLB variables changed!\n"); 4618202SAli.Saidi@ARM.com } 4627749SAli.Saidi@ARM.com 4637720Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 4647404SAli.Saidi@ARM.com uint32_t flags = req->getFlags(); 4657404SAli.Saidi@ARM.com 4667404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 4677404SAli.Saidi@ARM.com bool is_write = (mode == Write); 4687749SAli.Saidi@ARM.com bool is_priv = isPriv && !(flags & UserMode); 4697404SAli.Saidi@ARM.com 4708552Sdaniel.johnson@arm.com req->setAsid(contextId.asid); 4718552Sdaniel.johnson@arm.com 4728202SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", 4737749SAli.Saidi@ARM.com isPriv, flags & UserMode); 4747603SGene.Wu@arm.com // If this is a clrex instruction, provide a PA of 0 with no fault 4757603SGene.Wu@arm.com // This will force the monitor to set the tracked address to 0 4767603SGene.Wu@arm.com // a bit of a hack but this effectively clrears this processors monitor 4777705Sgblack@eecs.umich.edu if (flags & Request::CLEAR_LL){ 4787603SGene.Wu@arm.com req->setPaddr(0); 4797606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 4807705Sgblack@eecs.umich.edu req->setFlags(Request::CLEAR_LL); 4817603SGene.Wu@arm.com return NoFault; 4827603SGene.Wu@arm.com } 4837608SGene.Wu@arm.com if ((req->isInstFetch() && (!sctlr.i)) || 4847608SGene.Wu@arm.com ((!req->isInstFetch()) && (!sctlr.c))){ 4857608SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 4867608SGene.Wu@arm.com } 4877404SAli.Saidi@ARM.com if (!is_fetch) { 4887404SAli.Saidi@ARM.com assert(flags & MustBeOne); 4897404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 4907404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 4917734SAli.Saidi@ARM.com alignFaults++; 4927404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 4937404SAli.Saidi@ARM.com } 4947404SAli.Saidi@ARM.com } 4957404SAli.Saidi@ARM.com } 4967404SAli.Saidi@ARM.com 4977404SAli.Saidi@ARM.com Fault fault; 4987404SAli.Saidi@ARM.com 4996757SAli.Saidi@ARM.com if (!sctlr.m) { 5007093Sgblack@eecs.umich.edu req->setPaddr(vaddr); 5017404SAli.Saidi@ARM.com if (sctlr.tre == 0) { 5027404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 5037404SAli.Saidi@ARM.com } else { 5047404SAli.Saidi@ARM.com if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 5057404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 5067404SAli.Saidi@ARM.com } 5077436Sdam.sunwoo@arm.com 5087436Sdam.sunwoo@arm.com // Set memory attributes 5097436Sdam.sunwoo@arm.com TlbEntry temp_te; 5107439Sdam.sunwoo@arm.com tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 5117436Sdam.sunwoo@arm.com temp_te.shareable = true; 5127436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 5137436Sdam.sunwoo@arm.com %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 5147436Sdam.sunwoo@arm.com temp_te.innerAttrs, temp_te.outerAttrs); 5157436Sdam.sunwoo@arm.com setAttr(temp_te.attributes); 5167436Sdam.sunwoo@arm.com 5177404SAli.Saidi@ARM.com return trickBoxCheck(req, mode, 0, false); 5187404SAli.Saidi@ARM.com } 5197404SAli.Saidi@ARM.com 5207749SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId); 5217404SAli.Saidi@ARM.com // Translation enabled 5227404SAli.Saidi@ARM.com 5237749SAli.Saidi@ARM.com TlbEntry *te = lookup(vaddr, contextId); 5247404SAli.Saidi@ARM.com if (te == NULL) { 5257611SGene.Wu@arm.com if (req->isPrefetch()){ 5267611SGene.Wu@arm.com //if the request is a prefetch don't attempt to fill the TLB 5277611SGene.Wu@arm.com //or go any further with the memory access 5287734SAli.Saidi@ARM.com prefetchFaults++; 5297611SGene.Wu@arm.com return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 5307611SGene.Wu@arm.com } 5317734SAli.Saidi@ARM.com 5327734SAli.Saidi@ARM.com if (is_fetch) 5337734SAli.Saidi@ARM.com instMisses++; 5347734SAli.Saidi@ARM.com else if (is_write) 5357734SAli.Saidi@ARM.com writeMisses++; 5367734SAli.Saidi@ARM.com else 5377734SAli.Saidi@ARM.com readMisses++; 5387734SAli.Saidi@ARM.com 5397404SAli.Saidi@ARM.com // start translation table walk, pass variables rather than 5407404SAli.Saidi@ARM.com // re-retreaving in table walker for speed 5417404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 5427749SAli.Saidi@ARM.com vaddr, contextId); 5437749SAli.Saidi@ARM.com fault = tableWalker->walk(req, tc, contextId, mode, translation, 5448733Sgeoffrey.blake@arm.com timing, functional); 5458067SAli.Saidi@ARM.com if (timing && fault == NoFault) { 5467404SAli.Saidi@ARM.com delay = true; 5477437Sdam.sunwoo@arm.com // for timing mode, return and wait for table walk 5487437Sdam.sunwoo@arm.com return fault; 5497437Sdam.sunwoo@arm.com } 5507404SAli.Saidi@ARM.com if (fault) 5517404SAli.Saidi@ARM.com return fault; 5527404SAli.Saidi@ARM.com 5537749SAli.Saidi@ARM.com te = lookup(vaddr, contextId); 5547404SAli.Saidi@ARM.com if (!te) 5557404SAli.Saidi@ARM.com printTlb(); 5567404SAli.Saidi@ARM.com assert(te); 5577734SAli.Saidi@ARM.com } else { 5587734SAli.Saidi@ARM.com if (is_fetch) 5597734SAli.Saidi@ARM.com instHits++; 5607734SAli.Saidi@ARM.com else if (is_write) 5617734SAli.Saidi@ARM.com writeHits++; 5627734SAli.Saidi@ARM.com else 5637734SAli.Saidi@ARM.com readHits++; 5647404SAli.Saidi@ARM.com } 5657404SAli.Saidi@ARM.com 5667436Sdam.sunwoo@arm.com // Set memory attributes 5677436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, 5687436Sdam.sunwoo@arm.com "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 5697436Sdam.sunwoo@arm.com outerAttrs: %d\n", 5707436Sdam.sunwoo@arm.com te->shareable, te->innerAttrs, te->outerAttrs); 5717436Sdam.sunwoo@arm.com setAttr(te->attributes); 5727850SMatt.Horsnell@arm.com if (te->nonCacheable) { 5737606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 5747749SAli.Saidi@ARM.com 5757850SMatt.Horsnell@arm.com // Prevent prefetching from I/O devices. 5767850SMatt.Horsnell@arm.com if (req->isPrefetch()) { 5777850SMatt.Horsnell@arm.com return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable); 5787850SMatt.Horsnell@arm.com } 5797850SMatt.Horsnell@arm.com } 5807850SMatt.Horsnell@arm.com 5818527SAli.Saidi@ARM.com if (!bootUncacheability && 5828527SAli.Saidi@ARM.com ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) 5838527SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 5848527SAli.Saidi@ARM.com 5857404SAli.Saidi@ARM.com switch ( (dacr >> (te->domain * 2)) & 0x3) { 5867404SAli.Saidi@ARM.com case 0: 5877734SAli.Saidi@ARM.com domainFaults++; 5887404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 5897404SAli.Saidi@ARM.com " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 5907404SAli.Saidi@ARM.com if (is_fetch) 5917404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 5927404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 5937404SAli.Saidi@ARM.com else 5947404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 5957404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 5967404SAli.Saidi@ARM.com case 1: 5977404SAli.Saidi@ARM.com // Continue with permissions check 5987404SAli.Saidi@ARM.com break; 5997404SAli.Saidi@ARM.com case 2: 6007404SAli.Saidi@ARM.com panic("UNPRED domain\n"); 6017404SAli.Saidi@ARM.com case 3: 6027404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 6037404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 6047404SAli.Saidi@ARM.com if (fault) 6057404SAli.Saidi@ARM.com return fault; 6066757SAli.Saidi@ARM.com return NoFault; 6076757SAli.Saidi@ARM.com } 6087404SAli.Saidi@ARM.com 6097404SAli.Saidi@ARM.com uint8_t ap = te->ap; 6107404SAli.Saidi@ARM.com 6117404SAli.Saidi@ARM.com if (sctlr.afe == 1) 6127404SAli.Saidi@ARM.com ap |= 1; 6137404SAli.Saidi@ARM.com 6147404SAli.Saidi@ARM.com bool abt; 6157404SAli.Saidi@ARM.com 6167406SAli.Saidi@ARM.com /* if (!sctlr.xp) 6177406SAli.Saidi@ARM.com ap &= 0x3; 6187406SAli.Saidi@ARM.com*/ 6197404SAli.Saidi@ARM.com switch (ap) { 6207404SAli.Saidi@ARM.com case 0: 6217406SAli.Saidi@ARM.com DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 6227406SAli.Saidi@ARM.com if (!sctlr.xp) { 6237406SAli.Saidi@ARM.com switch ((int)sctlr.rs) { 6247406SAli.Saidi@ARM.com case 2: 6257406SAli.Saidi@ARM.com abt = is_write; 6267406SAli.Saidi@ARM.com break; 6277406SAli.Saidi@ARM.com case 1: 6287406SAli.Saidi@ARM.com abt = is_write || !is_priv; 6297406SAli.Saidi@ARM.com break; 6307406SAli.Saidi@ARM.com case 0: 6317406SAli.Saidi@ARM.com case 3: 6327406SAli.Saidi@ARM.com default: 6337406SAli.Saidi@ARM.com abt = true; 6347406SAli.Saidi@ARM.com break; 6357406SAli.Saidi@ARM.com } 6367406SAli.Saidi@ARM.com } else { 6377406SAli.Saidi@ARM.com abt = true; 6387406SAli.Saidi@ARM.com } 6397404SAli.Saidi@ARM.com break; 6407404SAli.Saidi@ARM.com case 1: 6417404SAli.Saidi@ARM.com abt = !is_priv; 6427404SAli.Saidi@ARM.com break; 6437404SAli.Saidi@ARM.com case 2: 6447404SAli.Saidi@ARM.com abt = !is_priv && is_write; 6457404SAli.Saidi@ARM.com break; 6467404SAli.Saidi@ARM.com case 3: 6477404SAli.Saidi@ARM.com abt = false; 6487404SAli.Saidi@ARM.com break; 6497404SAli.Saidi@ARM.com case 4: 6507404SAli.Saidi@ARM.com panic("UNPRED premissions\n"); 6517404SAli.Saidi@ARM.com case 5: 6527404SAli.Saidi@ARM.com abt = !is_priv || is_write; 6537404SAli.Saidi@ARM.com break; 6547404SAli.Saidi@ARM.com case 6: 6557404SAli.Saidi@ARM.com case 7: 6567404SAli.Saidi@ARM.com abt = is_write; 6577404SAli.Saidi@ARM.com break; 6587404SAli.Saidi@ARM.com default: 6597404SAli.Saidi@ARM.com panic("Unknown permissions\n"); 6607404SAli.Saidi@ARM.com } 6617404SAli.Saidi@ARM.com if ((is_fetch) && (abt || te->xn)) { 6627734SAli.Saidi@ARM.com permsFaults++; 6637404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 6647404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 6657404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 6667404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 6677404SAli.Saidi@ARM.com ArmFault::Permission1)); 6687404SAli.Saidi@ARM.com } else if (abt) { 6697734SAli.Saidi@ARM.com permsFaults++; 6707404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 6717404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 6727404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 6737404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 6747404SAli.Saidi@ARM.com ArmFault::Permission1)); 6757404SAli.Saidi@ARM.com } 6767404SAli.Saidi@ARM.com 6777404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 6787404SAli.Saidi@ARM.com // Check for a trickbox generated address fault 6797404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 6807404SAli.Saidi@ARM.com if (fault) 6817404SAli.Saidi@ARM.com return fault; 6827404SAli.Saidi@ARM.com 6836757SAli.Saidi@ARM.com return NoFault; 6847404SAli.Saidi@ARM.com} 6856757SAli.Saidi@ARM.com 6867404SAli.Saidi@ARM.comFault 6877404SAli.Saidi@ARM.comTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 6887404SAli.Saidi@ARM.com{ 6897404SAli.Saidi@ARM.com bool delay = false; 6907404SAli.Saidi@ARM.com Fault fault; 6918756Sgblack@eecs.umich.edu if (FullSystem) 6928756Sgblack@eecs.umich.edu fault = translateFs(req, tc, mode, NULL, delay, false); 6938756Sgblack@eecs.umich.edu else 6948756Sgblack@eecs.umich.edu fault = translateSe(req, tc, mode, NULL, delay, false); 6957404SAli.Saidi@ARM.com assert(!delay); 6967404SAli.Saidi@ARM.com return fault; 6976019Shines@cs.fsu.edu} 6986019Shines@cs.fsu.edu 6997404SAli.Saidi@ARM.comFault 7008733Sgeoffrey.blake@arm.comTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 7018733Sgeoffrey.blake@arm.com{ 7028733Sgeoffrey.blake@arm.com bool delay = false; 7038733Sgeoffrey.blake@arm.com Fault fault; 7048809Sgblack@eecs.umich.edu if (FullSystem) 7058809Sgblack@eecs.umich.edu fault = translateFs(req, tc, mode, NULL, delay, false, true); 7068809Sgblack@eecs.umich.edu else 7078809Sgblack@eecs.umich.edu fault = translateSe(req, tc, mode, NULL, delay, false); 7088733Sgeoffrey.blake@arm.com assert(!delay); 7098733Sgeoffrey.blake@arm.com return fault; 7108733Sgeoffrey.blake@arm.com} 7118733Sgeoffrey.blake@arm.com 7128733Sgeoffrey.blake@arm.comFault 7136116Snate@binkert.orgTLB::translateTiming(RequestPtr req, ThreadContext *tc, 7146116Snate@binkert.org Translation *translation, Mode mode) 7156020Sgblack@eecs.umich.edu{ 7166020Sgblack@eecs.umich.edu assert(translation); 7177404SAli.Saidi@ARM.com bool delay = false; 7187404SAli.Saidi@ARM.com Fault fault; 7198756Sgblack@eecs.umich.edu if (FullSystem) 7208756Sgblack@eecs.umich.edu fault = translateFs(req, tc, mode, translation, delay, true); 7218756Sgblack@eecs.umich.edu else 7228756Sgblack@eecs.umich.edu fault = translateSe(req, tc, mode, translation, delay, true); 7238527SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 7248067SAli.Saidi@ARM.com NoFault); 7257404SAli.Saidi@ARM.com if (!delay) 7267404SAli.Saidi@ARM.com translation->finish(fault, req, tc, mode); 7277944SGiacomo.Gabrielli@arm.com else 7287944SGiacomo.Gabrielli@arm.com translation->markDelayed(); 7297404SAli.Saidi@ARM.com return fault; 7306020Sgblack@eecs.umich.edu} 7316020Sgblack@eecs.umich.edu 7329294Sandreas.hansson@arm.comBaseMasterPort* 7338922Swilliam.wang@arm.comTLB::getMasterPort() 7347781SAli.Saidi@ARM.com{ 7358922Swilliam.wang@arm.com return &tableWalker->getMasterPort("port"); 7367781SAli.Saidi@ARM.com} 7377781SAli.Saidi@ARM.com 7387781SAli.Saidi@ARM.com 7397781SAli.Saidi@ARM.com 7406116Snate@binkert.orgArmISA::TLB * 7416116Snate@binkert.orgArmTLBParams::create() 7426019Shines@cs.fsu.edu{ 7436116Snate@binkert.org return new ArmISA::TLB(this); 7446019Shines@cs.fsu.edu} 745