tlb.cc revision 10024
16019Shines@cs.fsu.edu/* 29439SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Ali Saidi 417399SAli.Saidi@ARM.com * Nathan Binkert 426019Shines@cs.fsu.edu * Steve Reinhardt 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#include <string> 466019Shines@cs.fsu.edu#include <vector> 476019Shines@cs.fsu.edu 486116Snate@binkert.org#include "arch/arm/faults.hh" 496019Shines@cs.fsu.edu#include "arch/arm/pagetable.hh" 508782Sgblack@eecs.umich.edu#include "arch/arm/system.hh" 518756Sgblack@eecs.umich.edu#include "arch/arm/table_walker.hh" 526019Shines@cs.fsu.edu#include "arch/arm/tlb.hh" 536019Shines@cs.fsu.edu#include "arch/arm/utility.hh" 546019Shines@cs.fsu.edu#include "base/inifile.hh" 556019Shines@cs.fsu.edu#include "base/str.hh" 566019Shines@cs.fsu.edu#include "base/trace.hh" 5710024Sdam.sunwoo@arm.com#include "cpu/base.hh" 586019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 598232Snate@binkert.org#include "debug/Checkpoint.hh" 608232Snate@binkert.org#include "debug/TLB.hh" 618232Snate@binkert.org#include "debug/TLBVerbose.hh" 626116Snate@binkert.org#include "mem/page_table.hh" 636116Snate@binkert.org#include "params/ArmTLB.hh" 648756Sgblack@eecs.umich.edu#include "sim/full_system.hh" 656019Shines@cs.fsu.edu#include "sim/process.hh" 666019Shines@cs.fsu.edu 676019Shines@cs.fsu.eduusing namespace std; 686019Shines@cs.fsu.eduusing namespace ArmISA; 696019Shines@cs.fsu.edu 706019Shines@cs.fsu.eduTLB::TLB(const Params *p) 718756Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size) , tableWalker(p->walker), 728756Sgblack@eecs.umich.edu rangeMRU(1), bootUncacheability(false), miscRegValid(false) 736019Shines@cs.fsu.edu{ 747404SAli.Saidi@ARM.com table = new TlbEntry[size]; 758352SChander.Sudanthi@ARM.com memset(table, 0, sizeof(TlbEntry) * size); 767399SAli.Saidi@ARM.com 777404SAli.Saidi@ARM.com tableWalker->setTlb(this); 786019Shines@cs.fsu.edu} 796019Shines@cs.fsu.edu 806019Shines@cs.fsu.eduTLB::~TLB() 816019Shines@cs.fsu.edu{ 826019Shines@cs.fsu.edu if (table) 836019Shines@cs.fsu.edu delete [] table; 846019Shines@cs.fsu.edu} 856019Shines@cs.fsu.edu 867694SAli.Saidi@ARM.combool 877694SAli.Saidi@ARM.comTLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) 887694SAli.Saidi@ARM.com{ 897749SAli.Saidi@ARM.com if (!miscRegValid) 907749SAli.Saidi@ARM.com updateMiscReg(tc); 917749SAli.Saidi@ARM.com TlbEntry *e = lookup(va, contextId, true); 927694SAli.Saidi@ARM.com if (!e) 937694SAli.Saidi@ARM.com return false; 947694SAli.Saidi@ARM.com pa = e->pAddr(va); 957694SAli.Saidi@ARM.com return true; 967694SAli.Saidi@ARM.com} 977694SAli.Saidi@ARM.com 989738Sandreas@sandberg.pp.seFault 999738Sandreas@sandberg.pp.seTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 1009738Sandreas@sandberg.pp.se{ 1019738Sandreas@sandberg.pp.se return NoFault; 1029738Sandreas@sandberg.pp.se} 1039738Sandreas@sandberg.pp.se 1047404SAli.Saidi@ARM.comTlbEntry* 1057694SAli.Saidi@ARM.comTLB::lookup(Addr va, uint8_t cid, bool functional) 1066019Shines@cs.fsu.edu{ 1077404SAli.Saidi@ARM.com 1087404SAli.Saidi@ARM.com TlbEntry *retval = NULL; 1097404SAli.Saidi@ARM.com 1107697SAli.Saidi@ARM.com // Maitaining LRU array 1117404SAli.Saidi@ARM.com 1127404SAli.Saidi@ARM.com int x = 0; 1137404SAli.Saidi@ARM.com while (retval == NULL && x < size) { 1147404SAli.Saidi@ARM.com if (table[x].match(va, cid)) { 1157404SAli.Saidi@ARM.com 1167697SAli.Saidi@ARM.com // We only move the hit entry ahead when the position is higher than rangeMRU 1179535Smrinmoy.ghosh@arm.com if (x > rangeMRU && !functional) { 1187697SAli.Saidi@ARM.com TlbEntry tmp_entry = table[x]; 1197697SAli.Saidi@ARM.com for(int i = x; i > 0; i--) 1207697SAli.Saidi@ARM.com table[i] = table[i-1]; 1217697SAli.Saidi@ARM.com table[0] = tmp_entry; 1227697SAli.Saidi@ARM.com retval = &table[0]; 1237697SAli.Saidi@ARM.com } else { 1247697SAli.Saidi@ARM.com retval = &table[x]; 1257697SAli.Saidi@ARM.com } 1267404SAli.Saidi@ARM.com break; 1277404SAli.Saidi@ARM.com } 1287404SAli.Saidi@ARM.com x++; 1297404SAli.Saidi@ARM.com } 1307404SAli.Saidi@ARM.com 1317404SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n", 1327404SAli.Saidi@ARM.com va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0, 1337404SAli.Saidi@ARM.com retval ? retval->size : 0, retval ? retval->pAddr(va) : 0, 1347404SAli.Saidi@ARM.com retval ? retval->ap : 0); 1357404SAli.Saidi@ARM.com ; 1367404SAli.Saidi@ARM.com return retval; 1376019Shines@cs.fsu.edu} 1386019Shines@cs.fsu.edu 1396019Shines@cs.fsu.edu// insert a new TLB entry 1406019Shines@cs.fsu.eduvoid 1417404SAli.Saidi@ARM.comTLB::insert(Addr addr, TlbEntry &entry) 1426019Shines@cs.fsu.edu{ 1437404SAli.Saidi@ARM.com DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x" 1447404SAli.Saidi@ARM.com " asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x" 1457404SAli.Saidi@ARM.com " domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid, 1467404SAli.Saidi@ARM.com entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp, 1477404SAli.Saidi@ARM.com entry.xn, entry.ap, entry.domain); 1487404SAli.Saidi@ARM.com 1497697SAli.Saidi@ARM.com if (table[size-1].valid) 1507404SAli.Saidi@ARM.com DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n", 1517697SAli.Saidi@ARM.com table[size-1].vpn << table[size-1].N, table[size-1].asid, 1527697SAli.Saidi@ARM.com table[size-1].pfn << table[size-1].N, table[size-1].size, 1537697SAli.Saidi@ARM.com table[size-1].ap); 1547404SAli.Saidi@ARM.com 1557697SAli.Saidi@ARM.com //inserting to MRU position and evicting the LRU one 1567404SAli.Saidi@ARM.com 1577697SAli.Saidi@ARM.com for(int i = size-1; i > 0; i--) 1587697SAli.Saidi@ARM.com table[i] = table[i-1]; 1597697SAli.Saidi@ARM.com table[0] = entry; 1607734SAli.Saidi@ARM.com 1617734SAli.Saidi@ARM.com inserts++; 1626019Shines@cs.fsu.edu} 1636019Shines@cs.fsu.edu 1646019Shines@cs.fsu.eduvoid 1657404SAli.Saidi@ARM.comTLB::printTlb() 1667404SAli.Saidi@ARM.com{ 1677404SAli.Saidi@ARM.com int x = 0; 1687404SAli.Saidi@ARM.com TlbEntry *te; 1697404SAli.Saidi@ARM.com DPRINTF(TLB, "Current TLB contents:\n"); 1707404SAli.Saidi@ARM.com while (x < size) { 1717404SAli.Saidi@ARM.com te = &table[x]; 1727404SAli.Saidi@ARM.com if (te->valid) 1737404SAli.Saidi@ARM.com DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n", 1747404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1757404SAli.Saidi@ARM.com x++; 1767404SAli.Saidi@ARM.com } 1777404SAli.Saidi@ARM.com} 1787404SAli.Saidi@ARM.com 1797404SAli.Saidi@ARM.com 1807404SAli.Saidi@ARM.comvoid 1816019Shines@cs.fsu.eduTLB::flushAll() 1826019Shines@cs.fsu.edu{ 1837404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all TLB entries\n"); 1847404SAli.Saidi@ARM.com int x = 0; 1857404SAli.Saidi@ARM.com TlbEntry *te; 1867404SAli.Saidi@ARM.com while (x < size) { 1877404SAli.Saidi@ARM.com te = &table[x]; 1887734SAli.Saidi@ARM.com if (te->valid) { 1897404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 1907404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 1917734SAli.Saidi@ARM.com flushedEntries++; 1927734SAli.Saidi@ARM.com } 1937404SAli.Saidi@ARM.com x++; 1947404SAli.Saidi@ARM.com } 1957404SAli.Saidi@ARM.com 1968352SChander.Sudanthi@ARM.com memset(table, 0, sizeof(TlbEntry) * size); 1977734SAli.Saidi@ARM.com 1987734SAli.Saidi@ARM.com flushTlb++; 1996019Shines@cs.fsu.edu} 2006019Shines@cs.fsu.edu 2017404SAli.Saidi@ARM.com 2027404SAli.Saidi@ARM.comvoid 2037404SAli.Saidi@ARM.comTLB::flushMvaAsid(Addr mva, uint64_t asn) 2047404SAli.Saidi@ARM.com{ 2057404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn); 2067404SAli.Saidi@ARM.com TlbEntry *te; 2077404SAli.Saidi@ARM.com 2087404SAli.Saidi@ARM.com te = lookup(mva, asn); 2097404SAli.Saidi@ARM.com while (te != NULL) { 2107404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2117404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2127404SAli.Saidi@ARM.com te->valid = false; 2137734SAli.Saidi@ARM.com flushedEntries++; 2147404SAli.Saidi@ARM.com te = lookup(mva,asn); 2157404SAli.Saidi@ARM.com } 2167734SAli.Saidi@ARM.com flushTlbMvaAsid++; 2177404SAli.Saidi@ARM.com} 2187404SAli.Saidi@ARM.com 2197404SAli.Saidi@ARM.comvoid 2207404SAli.Saidi@ARM.comTLB::flushAsid(uint64_t asn) 2217404SAli.Saidi@ARM.com{ 2227404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn); 2237404SAli.Saidi@ARM.com 2247404SAli.Saidi@ARM.com int x = 0; 2257404SAli.Saidi@ARM.com TlbEntry *te; 2267404SAli.Saidi@ARM.com 2277404SAli.Saidi@ARM.com while (x < size) { 2287404SAli.Saidi@ARM.com te = &table[x]; 2297404SAli.Saidi@ARM.com if (te->asid == asn) { 2307404SAli.Saidi@ARM.com te->valid = false; 2317404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2327404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2337734SAli.Saidi@ARM.com flushedEntries++; 2347404SAli.Saidi@ARM.com } 2357404SAli.Saidi@ARM.com x++; 2367404SAli.Saidi@ARM.com } 2377734SAli.Saidi@ARM.com flushTlbAsid++; 2387404SAli.Saidi@ARM.com} 2397404SAli.Saidi@ARM.com 2407404SAli.Saidi@ARM.comvoid 2417404SAli.Saidi@ARM.comTLB::flushMva(Addr mva) 2427404SAli.Saidi@ARM.com{ 2437404SAli.Saidi@ARM.com DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva); 2447404SAli.Saidi@ARM.com 2457404SAli.Saidi@ARM.com int x = 0; 2467404SAli.Saidi@ARM.com TlbEntry *te; 2477404SAli.Saidi@ARM.com 2487404SAli.Saidi@ARM.com while (x < size) { 2497404SAli.Saidi@ARM.com te = &table[x]; 2507404SAli.Saidi@ARM.com Addr v = te->vpn << te->N; 2517404SAli.Saidi@ARM.com if (mva >= v && mva < v + te->size) { 2527404SAli.Saidi@ARM.com te->valid = false; 2537404SAli.Saidi@ARM.com DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n", 2547404SAli.Saidi@ARM.com te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap); 2557734SAli.Saidi@ARM.com flushedEntries++; 2567404SAli.Saidi@ARM.com } 2577404SAli.Saidi@ARM.com x++; 2587404SAli.Saidi@ARM.com } 2597734SAli.Saidi@ARM.com flushTlbMva++; 2607404SAli.Saidi@ARM.com} 2617404SAli.Saidi@ARM.com 2626019Shines@cs.fsu.eduvoid 2639439SAndreas.Sandberg@ARM.comTLB::drainResume() 2649439SAndreas.Sandberg@ARM.com{ 2659439SAndreas.Sandberg@ARM.com // We might have unserialized something or switched CPUs, so make 2669439SAndreas.Sandberg@ARM.com // sure to re-read the misc regs. 2679439SAndreas.Sandberg@ARM.com miscRegValid = false; 2689439SAndreas.Sandberg@ARM.com} 2699439SAndreas.Sandberg@ARM.com 2709439SAndreas.Sandberg@ARM.comvoid 2716019Shines@cs.fsu.eduTLB::serialize(ostream &os) 2726019Shines@cs.fsu.edu{ 2737733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm TLB\n"); 2747733SAli.Saidi@ARM.com 2757733SAli.Saidi@ARM.com SERIALIZE_SCALAR(_attr); 2768353SAli.Saidi@ARM.com 2778353SAli.Saidi@ARM.com int num_entries = size; 2788353SAli.Saidi@ARM.com SERIALIZE_SCALAR(num_entries); 2797733SAli.Saidi@ARM.com for(int i = 0; i < size; i++){ 2807733SAli.Saidi@ARM.com nameOut(os, csprintf("%s.TlbEntry%d", name(), i)); 2817733SAli.Saidi@ARM.com table[i].serialize(os); 2827733SAli.Saidi@ARM.com } 2836019Shines@cs.fsu.edu} 2846019Shines@cs.fsu.edu 2856019Shines@cs.fsu.eduvoid 2866019Shines@cs.fsu.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2876019Shines@cs.fsu.edu{ 2887733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm TLB\n"); 2896019Shines@cs.fsu.edu 2907733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_attr); 2918353SAli.Saidi@ARM.com int num_entries; 2928353SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(num_entries); 2938353SAli.Saidi@ARM.com for(int i = 0; i < min(size, num_entries); i++){ 2947733SAli.Saidi@ARM.com table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i)); 2957733SAli.Saidi@ARM.com } 2966019Shines@cs.fsu.edu} 2976019Shines@cs.fsu.edu 2986019Shines@cs.fsu.eduvoid 2996019Shines@cs.fsu.eduTLB::regStats() 3006019Shines@cs.fsu.edu{ 3017734SAli.Saidi@ARM.com instHits 3027734SAli.Saidi@ARM.com .name(name() + ".inst_hits") 3037734SAli.Saidi@ARM.com .desc("ITB inst hits") 3047734SAli.Saidi@ARM.com ; 3057734SAli.Saidi@ARM.com 3067734SAli.Saidi@ARM.com instMisses 3077734SAli.Saidi@ARM.com .name(name() + ".inst_misses") 3087734SAli.Saidi@ARM.com .desc("ITB inst misses") 3097734SAli.Saidi@ARM.com ; 3107734SAli.Saidi@ARM.com 3117734SAli.Saidi@ARM.com instAccesses 3127734SAli.Saidi@ARM.com .name(name() + ".inst_accesses") 3137734SAli.Saidi@ARM.com .desc("ITB inst accesses") 3147734SAli.Saidi@ARM.com ; 3157734SAli.Saidi@ARM.com 3167734SAli.Saidi@ARM.com readHits 3176019Shines@cs.fsu.edu .name(name() + ".read_hits") 3186019Shines@cs.fsu.edu .desc("DTB read hits") 3196019Shines@cs.fsu.edu ; 3206019Shines@cs.fsu.edu 3217734SAli.Saidi@ARM.com readMisses 3226019Shines@cs.fsu.edu .name(name() + ".read_misses") 3236019Shines@cs.fsu.edu .desc("DTB read misses") 3246019Shines@cs.fsu.edu ; 3256019Shines@cs.fsu.edu 3267734SAli.Saidi@ARM.com readAccesses 3276019Shines@cs.fsu.edu .name(name() + ".read_accesses") 3286019Shines@cs.fsu.edu .desc("DTB read accesses") 3296019Shines@cs.fsu.edu ; 3306019Shines@cs.fsu.edu 3317734SAli.Saidi@ARM.com writeHits 3326019Shines@cs.fsu.edu .name(name() + ".write_hits") 3336019Shines@cs.fsu.edu .desc("DTB write hits") 3346019Shines@cs.fsu.edu ; 3356019Shines@cs.fsu.edu 3367734SAli.Saidi@ARM.com writeMisses 3376019Shines@cs.fsu.edu .name(name() + ".write_misses") 3386019Shines@cs.fsu.edu .desc("DTB write misses") 3396019Shines@cs.fsu.edu ; 3406019Shines@cs.fsu.edu 3417734SAli.Saidi@ARM.com writeAccesses 3426019Shines@cs.fsu.edu .name(name() + ".write_accesses") 3436019Shines@cs.fsu.edu .desc("DTB write accesses") 3446019Shines@cs.fsu.edu ; 3456019Shines@cs.fsu.edu 3466019Shines@cs.fsu.edu hits 3476019Shines@cs.fsu.edu .name(name() + ".hits") 3486019Shines@cs.fsu.edu .desc("DTB hits") 3496019Shines@cs.fsu.edu ; 3506019Shines@cs.fsu.edu 3516019Shines@cs.fsu.edu misses 3526019Shines@cs.fsu.edu .name(name() + ".misses") 3536019Shines@cs.fsu.edu .desc("DTB misses") 3546019Shines@cs.fsu.edu ; 3556019Shines@cs.fsu.edu 3566019Shines@cs.fsu.edu accesses 3576019Shines@cs.fsu.edu .name(name() + ".accesses") 3586019Shines@cs.fsu.edu .desc("DTB accesses") 3596019Shines@cs.fsu.edu ; 3606019Shines@cs.fsu.edu 3617734SAli.Saidi@ARM.com flushTlb 3627734SAli.Saidi@ARM.com .name(name() + ".flush_tlb") 3637734SAli.Saidi@ARM.com .desc("Number of times complete TLB was flushed") 3647734SAli.Saidi@ARM.com ; 3657734SAli.Saidi@ARM.com 3667734SAli.Saidi@ARM.com flushTlbMva 3677734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva") 3687734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA") 3697734SAli.Saidi@ARM.com ; 3707734SAli.Saidi@ARM.com 3717734SAli.Saidi@ARM.com flushTlbMvaAsid 3727734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_mva_asid") 3737734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by MVA & ASID") 3747734SAli.Saidi@ARM.com ; 3757734SAli.Saidi@ARM.com 3767734SAli.Saidi@ARM.com flushTlbAsid 3777734SAli.Saidi@ARM.com .name(name() + ".flush_tlb_asid") 3787734SAli.Saidi@ARM.com .desc("Number of times TLB was flushed by ASID") 3797734SAli.Saidi@ARM.com ; 3807734SAli.Saidi@ARM.com 3817734SAli.Saidi@ARM.com flushedEntries 3827734SAli.Saidi@ARM.com .name(name() + ".flush_entries") 3837734SAli.Saidi@ARM.com .desc("Number of entries that have been flushed from TLB") 3847734SAli.Saidi@ARM.com ; 3857734SAli.Saidi@ARM.com 3867734SAli.Saidi@ARM.com alignFaults 3877734SAli.Saidi@ARM.com .name(name() + ".align_faults") 3887734SAli.Saidi@ARM.com .desc("Number of TLB faults due to alignment restrictions") 3897734SAli.Saidi@ARM.com ; 3907734SAli.Saidi@ARM.com 3917734SAli.Saidi@ARM.com prefetchFaults 3927734SAli.Saidi@ARM.com .name(name() + ".prefetch_faults") 3937734SAli.Saidi@ARM.com .desc("Number of TLB faults due to prefetch") 3947734SAli.Saidi@ARM.com ; 3957734SAli.Saidi@ARM.com 3967734SAli.Saidi@ARM.com domainFaults 3977734SAli.Saidi@ARM.com .name(name() + ".domain_faults") 3987734SAli.Saidi@ARM.com .desc("Number of TLB faults due to domain restrictions") 3997734SAli.Saidi@ARM.com ; 4007734SAli.Saidi@ARM.com 4017734SAli.Saidi@ARM.com permsFaults 4027734SAli.Saidi@ARM.com .name(name() + ".perms_faults") 4037734SAli.Saidi@ARM.com .desc("Number of TLB faults due to permissions restrictions") 4047734SAli.Saidi@ARM.com ; 4057734SAli.Saidi@ARM.com 4067734SAli.Saidi@ARM.com instAccesses = instHits + instMisses; 4077734SAli.Saidi@ARM.com readAccesses = readHits + readMisses; 4087734SAli.Saidi@ARM.com writeAccesses = writeHits + writeMisses; 4097734SAli.Saidi@ARM.com hits = readHits + writeHits + instHits; 4107734SAli.Saidi@ARM.com misses = readMisses + writeMisses + instMisses; 4117734SAli.Saidi@ARM.com accesses = readAccesses + writeAccesses + instAccesses; 4126019Shines@cs.fsu.edu} 4136019Shines@cs.fsu.edu 4147404SAli.Saidi@ARM.comFault 4157404SAli.Saidi@ARM.comTLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, 4167404SAli.Saidi@ARM.com Translation *translation, bool &delay, bool timing) 4177404SAli.Saidi@ARM.com{ 4187749SAli.Saidi@ARM.com if (!miscRegValid) 4197749SAli.Saidi@ARM.com updateMiscReg(tc); 4207720Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 4217294Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 4227294Sgblack@eecs.umich.edu 4237404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 4247404SAli.Saidi@ARM.com bool is_write = (mode == Write); 4257404SAli.Saidi@ARM.com 4267404SAli.Saidi@ARM.com if (!is_fetch) { 4277294Sgblack@eecs.umich.edu assert(flags & MustBeOne); 4287404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 4297404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 4307404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 4317294Sgblack@eecs.umich.edu } 4327294Sgblack@eecs.umich.edu } 4337294Sgblack@eecs.umich.edu } 4346019Shines@cs.fsu.edu 4357093Sgblack@eecs.umich.edu Addr paddr; 4367404SAli.Saidi@ARM.com Process *p = tc->getProcessPtr(); 4377404SAli.Saidi@ARM.com 4387093Sgblack@eecs.umich.edu if (!p->pTable->translate(vaddr, paddr)) 4397093Sgblack@eecs.umich.edu return Fault(new GenericPageTableFault(vaddr)); 4407093Sgblack@eecs.umich.edu req->setPaddr(paddr); 4416019Shines@cs.fsu.edu 4426019Shines@cs.fsu.edu return NoFault; 4437404SAli.Saidi@ARM.com} 4447404SAli.Saidi@ARM.com 4457404SAli.Saidi@ARM.comFault 4467406SAli.Saidi@ARM.comTLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) 4477406SAli.Saidi@ARM.com{ 4487406SAli.Saidi@ARM.com return NoFault; 4497406SAli.Saidi@ARM.com} 4507406SAli.Saidi@ARM.com 4517406SAli.Saidi@ARM.comFault 4527406SAli.Saidi@ARM.comTLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec, 4537406SAli.Saidi@ARM.com bool is_write, uint8_t domain, bool sNp) 4547406SAli.Saidi@ARM.com{ 4557406SAli.Saidi@ARM.com return NoFault; 4567406SAli.Saidi@ARM.com} 4577406SAli.Saidi@ARM.com 4587406SAli.Saidi@ARM.comFault 4597404SAli.Saidi@ARM.comTLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, 4608733Sgeoffrey.blake@arm.com Translation *translation, bool &delay, bool timing, bool functional) 4617404SAli.Saidi@ARM.com{ 4628733Sgeoffrey.blake@arm.com // No such thing as a functional timing access 4638733Sgeoffrey.blake@arm.com assert(!(timing && functional)); 4648733Sgeoffrey.blake@arm.com 4658202SAli.Saidi@ARM.com if (!miscRegValid) { 4667749SAli.Saidi@ARM.com updateMiscReg(tc); 4678202SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "TLB variables changed!\n"); 4688202SAli.Saidi@ARM.com } 4697749SAli.Saidi@ARM.com 4707720Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 4717404SAli.Saidi@ARM.com uint32_t flags = req->getFlags(); 4727404SAli.Saidi@ARM.com 4737404SAli.Saidi@ARM.com bool is_fetch = (mode == Execute); 4747404SAli.Saidi@ARM.com bool is_write = (mode == Write); 4757749SAli.Saidi@ARM.com bool is_priv = isPriv && !(flags & UserMode); 4767404SAli.Saidi@ARM.com 4778552Sdaniel.johnson@arm.com req->setAsid(contextId.asid); 4789950Sprakash.ramrakhyani@arm.com if (is_priv) 4799950Sprakash.ramrakhyani@arm.com req->setFlags(Request::PRIVILEGED); 4808552Sdaniel.johnson@arm.com 48110024Sdam.sunwoo@arm.com req->taskId(tc->getCpuPtr()->taskId()); 48210024Sdam.sunwoo@arm.com 4838202SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", 4847749SAli.Saidi@ARM.com isPriv, flags & UserMode); 4857603SGene.Wu@arm.com // If this is a clrex instruction, provide a PA of 0 with no fault 4867603SGene.Wu@arm.com // This will force the monitor to set the tracked address to 0 4877603SGene.Wu@arm.com // a bit of a hack but this effectively clrears this processors monitor 4887705Sgblack@eecs.umich.edu if (flags & Request::CLEAR_LL){ 4897603SGene.Wu@arm.com req->setPaddr(0); 4907606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 4917705Sgblack@eecs.umich.edu req->setFlags(Request::CLEAR_LL); 4927603SGene.Wu@arm.com return NoFault; 4937603SGene.Wu@arm.com } 4947608SGene.Wu@arm.com if ((req->isInstFetch() && (!sctlr.i)) || 4957608SGene.Wu@arm.com ((!req->isInstFetch()) && (!sctlr.c))){ 4967608SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 4977608SGene.Wu@arm.com } 4987404SAli.Saidi@ARM.com if (!is_fetch) { 4997404SAli.Saidi@ARM.com assert(flags & MustBeOne); 5007404SAli.Saidi@ARM.com if (sctlr.a || !(flags & AllowUnaligned)) { 5017404SAli.Saidi@ARM.com if (vaddr & flags & AlignmentMask) { 5027734SAli.Saidi@ARM.com alignFaults++; 5037404SAli.Saidi@ARM.com return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault); 5047404SAli.Saidi@ARM.com } 5057404SAli.Saidi@ARM.com } 5067404SAli.Saidi@ARM.com } 5077404SAli.Saidi@ARM.com 5087404SAli.Saidi@ARM.com Fault fault; 5097404SAli.Saidi@ARM.com 5106757SAli.Saidi@ARM.com if (!sctlr.m) { 5117093Sgblack@eecs.umich.edu req->setPaddr(vaddr); 5127404SAli.Saidi@ARM.com if (sctlr.tre == 0) { 5137404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 5147404SAli.Saidi@ARM.com } else { 5157404SAli.Saidi@ARM.com if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) 5167404SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 5177404SAli.Saidi@ARM.com } 5187436Sdam.sunwoo@arm.com 5197436Sdam.sunwoo@arm.com // Set memory attributes 5207436Sdam.sunwoo@arm.com TlbEntry temp_te; 5217439Sdam.sunwoo@arm.com tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); 5227436Sdam.sunwoo@arm.com temp_te.shareable = true; 5237436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ 5247436Sdam.sunwoo@arm.com %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, 5257436Sdam.sunwoo@arm.com temp_te.innerAttrs, temp_te.outerAttrs); 5267436Sdam.sunwoo@arm.com setAttr(temp_te.attributes); 5277436Sdam.sunwoo@arm.com 5287404SAli.Saidi@ARM.com return trickBoxCheck(req, mode, 0, false); 5297404SAli.Saidi@ARM.com } 5307404SAli.Saidi@ARM.com 5317749SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId); 5327404SAli.Saidi@ARM.com // Translation enabled 5337404SAli.Saidi@ARM.com 5347749SAli.Saidi@ARM.com TlbEntry *te = lookup(vaddr, contextId); 5357404SAli.Saidi@ARM.com if (te == NULL) { 5367611SGene.Wu@arm.com if (req->isPrefetch()){ 5377611SGene.Wu@arm.com //if the request is a prefetch don't attempt to fill the TLB 5387611SGene.Wu@arm.com //or go any further with the memory access 5397734SAli.Saidi@ARM.com prefetchFaults++; 5407611SGene.Wu@arm.com return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); 5417611SGene.Wu@arm.com } 5427734SAli.Saidi@ARM.com 5437734SAli.Saidi@ARM.com if (is_fetch) 5447734SAli.Saidi@ARM.com instMisses++; 5457734SAli.Saidi@ARM.com else if (is_write) 5467734SAli.Saidi@ARM.com writeMisses++; 5477734SAli.Saidi@ARM.com else 5487734SAli.Saidi@ARM.com readMisses++; 5497734SAli.Saidi@ARM.com 5507404SAli.Saidi@ARM.com // start translation table walk, pass variables rather than 5517404SAli.Saidi@ARM.com // re-retreaving in table walker for speed 5527404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", 5537749SAli.Saidi@ARM.com vaddr, contextId); 5547749SAli.Saidi@ARM.com fault = tableWalker->walk(req, tc, contextId, mode, translation, 5558733Sgeoffrey.blake@arm.com timing, functional); 5568067SAli.Saidi@ARM.com if (timing && fault == NoFault) { 5577404SAli.Saidi@ARM.com delay = true; 5587437Sdam.sunwoo@arm.com // for timing mode, return and wait for table walk 5597437Sdam.sunwoo@arm.com return fault; 5607437Sdam.sunwoo@arm.com } 5617404SAli.Saidi@ARM.com if (fault) 5627404SAli.Saidi@ARM.com return fault; 5637404SAli.Saidi@ARM.com 5647749SAli.Saidi@ARM.com te = lookup(vaddr, contextId); 5657404SAli.Saidi@ARM.com if (!te) 5667404SAli.Saidi@ARM.com printTlb(); 5677404SAli.Saidi@ARM.com assert(te); 5687734SAli.Saidi@ARM.com } else { 5697734SAli.Saidi@ARM.com if (is_fetch) 5707734SAli.Saidi@ARM.com instHits++; 5717734SAli.Saidi@ARM.com else if (is_write) 5727734SAli.Saidi@ARM.com writeHits++; 5737734SAli.Saidi@ARM.com else 5747734SAli.Saidi@ARM.com readHits++; 5757404SAli.Saidi@ARM.com } 5767404SAli.Saidi@ARM.com 5777436Sdam.sunwoo@arm.com // Set memory attributes 5787436Sdam.sunwoo@arm.com DPRINTF(TLBVerbose, 5797436Sdam.sunwoo@arm.com "Setting memory attributes: shareable: %d, innerAttrs: %d, \ 5807436Sdam.sunwoo@arm.com outerAttrs: %d\n", 5817436Sdam.sunwoo@arm.com te->shareable, te->innerAttrs, te->outerAttrs); 5827436Sdam.sunwoo@arm.com setAttr(te->attributes); 5837850SMatt.Horsnell@arm.com if (te->nonCacheable) { 5847606SGene.Wu@arm.com req->setFlags(Request::UNCACHEABLE); 5857749SAli.Saidi@ARM.com 5867850SMatt.Horsnell@arm.com // Prevent prefetching from I/O devices. 5877850SMatt.Horsnell@arm.com if (req->isPrefetch()) { 5887850SMatt.Horsnell@arm.com return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable); 5897850SMatt.Horsnell@arm.com } 5907850SMatt.Horsnell@arm.com } 5917850SMatt.Horsnell@arm.com 5928527SAli.Saidi@ARM.com if (!bootUncacheability && 5938527SAli.Saidi@ARM.com ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) 5948527SAli.Saidi@ARM.com req->setFlags(Request::UNCACHEABLE); 5958527SAli.Saidi@ARM.com 5967404SAli.Saidi@ARM.com switch ( (dacr >> (te->domain * 2)) & 0x3) { 5977404SAli.Saidi@ARM.com case 0: 5987734SAli.Saidi@ARM.com domainFaults++; 5997404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x" 6007404SAli.Saidi@ARM.com " write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp); 6017404SAli.Saidi@ARM.com if (is_fetch) 6027404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 6037404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 6047404SAli.Saidi@ARM.com else 6057404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 6067404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Domain0 : ArmFault::Domain1)); 6077404SAli.Saidi@ARM.com case 1: 6087404SAli.Saidi@ARM.com // Continue with permissions check 6097404SAli.Saidi@ARM.com break; 6107404SAli.Saidi@ARM.com case 2: 6117404SAli.Saidi@ARM.com panic("UNPRED domain\n"); 6127404SAli.Saidi@ARM.com case 3: 6137404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 6147404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 6157404SAli.Saidi@ARM.com if (fault) 6167404SAli.Saidi@ARM.com return fault; 6176757SAli.Saidi@ARM.com return NoFault; 6186757SAli.Saidi@ARM.com } 6197404SAli.Saidi@ARM.com 6207404SAli.Saidi@ARM.com uint8_t ap = te->ap; 6217404SAli.Saidi@ARM.com 6227404SAli.Saidi@ARM.com if (sctlr.afe == 1) 6237404SAli.Saidi@ARM.com ap |= 1; 6247404SAli.Saidi@ARM.com 6257404SAli.Saidi@ARM.com bool abt; 6267404SAli.Saidi@ARM.com 6277406SAli.Saidi@ARM.com /* if (!sctlr.xp) 6287406SAli.Saidi@ARM.com ap &= 0x3; 6297406SAli.Saidi@ARM.com*/ 6307404SAli.Saidi@ARM.com switch (ap) { 6317404SAli.Saidi@ARM.com case 0: 6327406SAli.Saidi@ARM.com DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs); 6337406SAli.Saidi@ARM.com if (!sctlr.xp) { 6347406SAli.Saidi@ARM.com switch ((int)sctlr.rs) { 6357406SAli.Saidi@ARM.com case 2: 6367406SAli.Saidi@ARM.com abt = is_write; 6377406SAli.Saidi@ARM.com break; 6387406SAli.Saidi@ARM.com case 1: 6397406SAli.Saidi@ARM.com abt = is_write || !is_priv; 6407406SAli.Saidi@ARM.com break; 6417406SAli.Saidi@ARM.com case 0: 6427406SAli.Saidi@ARM.com case 3: 6437406SAli.Saidi@ARM.com default: 6447406SAli.Saidi@ARM.com abt = true; 6457406SAli.Saidi@ARM.com break; 6467406SAli.Saidi@ARM.com } 6477406SAli.Saidi@ARM.com } else { 6487406SAli.Saidi@ARM.com abt = true; 6497406SAli.Saidi@ARM.com } 6507404SAli.Saidi@ARM.com break; 6517404SAli.Saidi@ARM.com case 1: 6527404SAli.Saidi@ARM.com abt = !is_priv; 6537404SAli.Saidi@ARM.com break; 6547404SAli.Saidi@ARM.com case 2: 6557404SAli.Saidi@ARM.com abt = !is_priv && is_write; 6567404SAli.Saidi@ARM.com break; 6577404SAli.Saidi@ARM.com case 3: 6587404SAli.Saidi@ARM.com abt = false; 6597404SAli.Saidi@ARM.com break; 6607404SAli.Saidi@ARM.com case 4: 6617404SAli.Saidi@ARM.com panic("UNPRED premissions\n"); 6627404SAli.Saidi@ARM.com case 5: 6637404SAli.Saidi@ARM.com abt = !is_priv || is_write; 6647404SAli.Saidi@ARM.com break; 6657404SAli.Saidi@ARM.com case 6: 6667404SAli.Saidi@ARM.com case 7: 6677404SAli.Saidi@ARM.com abt = is_write; 6687404SAli.Saidi@ARM.com break; 6697404SAli.Saidi@ARM.com default: 6707404SAli.Saidi@ARM.com panic("Unknown permissions\n"); 6717404SAli.Saidi@ARM.com } 6727404SAli.Saidi@ARM.com if ((is_fetch) && (abt || te->xn)) { 6737734SAli.Saidi@ARM.com permsFaults++; 6747404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d" 6757404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 6767404SAli.Saidi@ARM.com return new PrefetchAbort(vaddr, 6777404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 6787404SAli.Saidi@ARM.com ArmFault::Permission1)); 6797404SAli.Saidi@ARM.com } else if (abt) { 6807734SAli.Saidi@ARM.com permsFaults++; 6817404SAli.Saidi@ARM.com DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d" 6827404SAli.Saidi@ARM.com " write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp); 6837404SAli.Saidi@ARM.com return new DataAbort(vaddr, te->domain, is_write, 6847404SAli.Saidi@ARM.com (te->sNp ? ArmFault::Permission0 : 6857404SAli.Saidi@ARM.com ArmFault::Permission1)); 6867404SAli.Saidi@ARM.com } 6877404SAli.Saidi@ARM.com 6887404SAli.Saidi@ARM.com req->setPaddr(te->pAddr(vaddr)); 6897404SAli.Saidi@ARM.com // Check for a trickbox generated address fault 6907404SAli.Saidi@ARM.com fault = trickBoxCheck(req, mode, te->domain, te->sNp); 6917404SAli.Saidi@ARM.com if (fault) 6927404SAli.Saidi@ARM.com return fault; 6937404SAli.Saidi@ARM.com 6946757SAli.Saidi@ARM.com return NoFault; 6957404SAli.Saidi@ARM.com} 6966757SAli.Saidi@ARM.com 6977404SAli.Saidi@ARM.comFault 6987404SAli.Saidi@ARM.comTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 6997404SAli.Saidi@ARM.com{ 7007404SAli.Saidi@ARM.com bool delay = false; 7017404SAli.Saidi@ARM.com Fault fault; 7028756Sgblack@eecs.umich.edu if (FullSystem) 7038756Sgblack@eecs.umich.edu fault = translateFs(req, tc, mode, NULL, delay, false); 7048756Sgblack@eecs.umich.edu else 7058756Sgblack@eecs.umich.edu fault = translateSe(req, tc, mode, NULL, delay, false); 7067404SAli.Saidi@ARM.com assert(!delay); 7077404SAli.Saidi@ARM.com return fault; 7086019Shines@cs.fsu.edu} 7096019Shines@cs.fsu.edu 7107404SAli.Saidi@ARM.comFault 7118733Sgeoffrey.blake@arm.comTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 7128733Sgeoffrey.blake@arm.com{ 7138733Sgeoffrey.blake@arm.com bool delay = false; 7148733Sgeoffrey.blake@arm.com Fault fault; 7158809Sgblack@eecs.umich.edu if (FullSystem) 7168809Sgblack@eecs.umich.edu fault = translateFs(req, tc, mode, NULL, delay, false, true); 7178809Sgblack@eecs.umich.edu else 7188809Sgblack@eecs.umich.edu fault = translateSe(req, tc, mode, NULL, delay, false); 7198733Sgeoffrey.blake@arm.com assert(!delay); 7208733Sgeoffrey.blake@arm.com return fault; 7218733Sgeoffrey.blake@arm.com} 7228733Sgeoffrey.blake@arm.com 7238733Sgeoffrey.blake@arm.comFault 7246116Snate@binkert.orgTLB::translateTiming(RequestPtr req, ThreadContext *tc, 7256116Snate@binkert.org Translation *translation, Mode mode) 7266020Sgblack@eecs.umich.edu{ 7276020Sgblack@eecs.umich.edu assert(translation); 7287404SAli.Saidi@ARM.com bool delay = false; 7297404SAli.Saidi@ARM.com Fault fault; 7308756Sgblack@eecs.umich.edu if (FullSystem) 7318756Sgblack@eecs.umich.edu fault = translateFs(req, tc, mode, translation, delay, true); 7328756Sgblack@eecs.umich.edu else 7338756Sgblack@eecs.umich.edu fault = translateSe(req, tc, mode, translation, delay, true); 7348527SAli.Saidi@ARM.com DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != 7358067SAli.Saidi@ARM.com NoFault); 7367404SAli.Saidi@ARM.com if (!delay) 7377404SAli.Saidi@ARM.com translation->finish(fault, req, tc, mode); 7387944SGiacomo.Gabrielli@arm.com else 7397944SGiacomo.Gabrielli@arm.com translation->markDelayed(); 7407404SAli.Saidi@ARM.com return fault; 7416020Sgblack@eecs.umich.edu} 7426020Sgblack@eecs.umich.edu 7439294Sandreas.hansson@arm.comBaseMasterPort* 7448922Swilliam.wang@arm.comTLB::getMasterPort() 7457781SAli.Saidi@ARM.com{ 7468922Swilliam.wang@arm.com return &tableWalker->getMasterPort("port"); 7477781SAli.Saidi@ARM.com} 7487781SAli.Saidi@ARM.com 7497781SAli.Saidi@ARM.com 7507781SAli.Saidi@ARM.com 7516116Snate@binkert.orgArmISA::TLB * 7526116Snate@binkert.orgArmTLBParams::create() 7536019Shines@cs.fsu.edu{ 7546116Snate@binkert.org return new ArmISA::TLB(this); 7556019Shines@cs.fsu.edu} 756