table_walker.hh revision 7578:7ea651f34ae6
110859Sandreas.sandberg@arm.com/* 211461Sandreas.sandberg@arm.com * Copyright (c) 2010 ARM Limited 310859Sandreas.sandberg@arm.com * All rights reserved 410859Sandreas.sandberg@arm.com * 510859Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 610859Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 710859Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 810859Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 910859Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1010859Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1110859Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1210859Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1310859Sandreas.sandberg@arm.com * 1410859Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1510859Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 1610859Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 1710859Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 1810859Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1910859Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2010859Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 2110859Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2210859Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2310859Sandreas.sandberg@arm.com * this software without specific prior written permission. 2410859Sandreas.sandberg@arm.com * 2510859Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610859Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710859Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810859Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910859Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010859Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110859Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210859Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310859Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410859Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510859Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610859Sandreas.sandberg@arm.com * 3710859Sandreas.sandberg@arm.com * Authors: Ali Saidi 3810859Sandreas.sandberg@arm.com */ 3910859Sandreas.sandberg@arm.com 4010859Sandreas.sandberg@arm.com#ifndef __ARCH_ARM_TABLE_WALKER_HH__ 4110859Sandreas.sandberg@arm.com#define __ARCH_ARM_TABLE_WALKER_HH__ 4210859Sandreas.sandberg@arm.com 4310859Sandreas.sandberg@arm.com#include <list> 4410859Sandreas.sandberg@arm.com 4510859Sandreas.sandberg@arm.com#include "arch/arm/miscregs.hh" 4610859Sandreas.sandberg@arm.com#include "arch/arm/tlb.hh" 4710859Sandreas.sandberg@arm.com#include "mem/mem_object.hh" 4810859Sandreas.sandberg@arm.com#include "mem/request.hh" 4911461Sandreas.sandberg@arm.com#include "mem/request.hh" 5011461Sandreas.sandberg@arm.com#include "params/ArmTableWalker.hh" 5111461Sandreas.sandberg@arm.com#include "sim/faults.hh" 5211461Sandreas.sandberg@arm.com#include "sim/eventq.hh" 5311461Sandreas.sandberg@arm.com 5411461Sandreas.sandberg@arm.comclass DmaPort; 5511461Sandreas.sandberg@arm.comclass ThreadContext; 5611461Sandreas.sandberg@arm.com 5711461Sandreas.sandberg@arm.comnamespace ArmISA { 5811461Sandreas.sandberg@arm.comclass Translation; 5911461Sandreas.sandberg@arm.comclass TLB; 6011461Sandreas.sandberg@arm.com 6111461Sandreas.sandberg@arm.comclass TableWalker : public MemObject 6211461Sandreas.sandberg@arm.com{ 6311461Sandreas.sandberg@arm.com protected: 6411461Sandreas.sandberg@arm.com struct L1Descriptor { 6511461Sandreas.sandberg@arm.com /** Type of page table entry ARM DDI 0406B: B3-8*/ 6611461Sandreas.sandberg@arm.com enum EntryType { 6711461Sandreas.sandberg@arm.com Ignore, 6811838SCurtis.Dunham@arm.com PageTable, 6911461Sandreas.sandberg@arm.com Section, 7011462Sandreas.sandberg@arm.com Reserved 7111462Sandreas.sandberg@arm.com }; 7211461Sandreas.sandberg@arm.com 7311461Sandreas.sandberg@arm.com /** The raw bits of the entry */ 7411461Sandreas.sandberg@arm.com uint32_t data; 7511461Sandreas.sandberg@arm.com 7611461Sandreas.sandberg@arm.com /** This entry has been modified (access flag set) and needs to be 7711461Sandreas.sandberg@arm.com * written back to memory */ 7811461Sandreas.sandberg@arm.com bool _dirty; 7911461Sandreas.sandberg@arm.com 8011461Sandreas.sandberg@arm.com EntryType type() const 8111461Sandreas.sandberg@arm.com { 8211461Sandreas.sandberg@arm.com return (EntryType)(data & 0x3); 8311461Sandreas.sandberg@arm.com } 8411461Sandreas.sandberg@arm.com 8511461Sandreas.sandberg@arm.com /** Is the page a Supersection (16MB)?*/ 8611461Sandreas.sandberg@arm.com bool supersection() const 8711461Sandreas.sandberg@arm.com { 8811461Sandreas.sandberg@arm.com return bits(data, 18); 8911461Sandreas.sandberg@arm.com } 9011461Sandreas.sandberg@arm.com 9111461Sandreas.sandberg@arm.com /** Return the physcal address of the entry, bits in position*/ 9211461Sandreas.sandberg@arm.com Addr paddr() const 9311461Sandreas.sandberg@arm.com { 9411461Sandreas.sandberg@arm.com if (supersection()) 9511461Sandreas.sandberg@arm.com panic("Super sections not implemented\n"); 9611461Sandreas.sandberg@arm.com return mbits(data, 31,20); 9711461Sandreas.sandberg@arm.com } 9811461Sandreas.sandberg@arm.com 9911461Sandreas.sandberg@arm.com /** Return the physical frame, bits shifted right */ 10011461Sandreas.sandberg@arm.com Addr pfn() const 10111461Sandreas.sandberg@arm.com { 10211461Sandreas.sandberg@arm.com if (supersection()) 10311461Sandreas.sandberg@arm.com panic("Super sections not implemented\n"); 10411461Sandreas.sandberg@arm.com return bits(data, 31,20); 10511461Sandreas.sandberg@arm.com } 10611461Sandreas.sandberg@arm.com 10711461Sandreas.sandberg@arm.com /** Is the translation global (no asid used)? */ 10811461Sandreas.sandberg@arm.com bool global() const 10911461Sandreas.sandberg@arm.com { 11011461Sandreas.sandberg@arm.com return bits(data, 4); 11111461Sandreas.sandberg@arm.com } 11211461Sandreas.sandberg@arm.com 11311461Sandreas.sandberg@arm.com /** Is the translation not allow execution? */ 11411461Sandreas.sandberg@arm.com bool xn() const 11511461Sandreas.sandberg@arm.com { 11611461Sandreas.sandberg@arm.com return bits(data, 17); 11711461Sandreas.sandberg@arm.com } 11811461Sandreas.sandberg@arm.com 11911461Sandreas.sandberg@arm.com /** Three bit access protection flags */ 12011461Sandreas.sandberg@arm.com uint8_t ap() const 12111461Sandreas.sandberg@arm.com { 12211461Sandreas.sandberg@arm.com return (bits(data, 15) << 2) | bits(data,11,10); 12311461Sandreas.sandberg@arm.com } 12411461Sandreas.sandberg@arm.com 12511461Sandreas.sandberg@arm.com /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ 12611461Sandreas.sandberg@arm.com uint8_t domain() const 12711461Sandreas.sandberg@arm.com { 12811461Sandreas.sandberg@arm.com return bits(data,8,5); 12911461Sandreas.sandberg@arm.com } 13011461Sandreas.sandberg@arm.com 13111461Sandreas.sandberg@arm.com /** Address of L2 descriptor if it exists */ 13211461Sandreas.sandberg@arm.com Addr l2Addr() const 13311461Sandreas.sandberg@arm.com { 13411461Sandreas.sandberg@arm.com return mbits(data, 31,10); 13511461Sandreas.sandberg@arm.com } 13611461Sandreas.sandberg@arm.com 13711461Sandreas.sandberg@arm.com /** Memory region attributes: ARM DDI 0406B: B3-32. 13811461Sandreas.sandberg@arm.com * These bits are largly ignored by M5 and only used to 13911461Sandreas.sandberg@arm.com * provide the illusion that the memory system cares about 14010859Sandreas.sandberg@arm.com * anything but cachable vs. uncachable. 14110859Sandreas.sandberg@arm.com */ 14210859Sandreas.sandberg@arm.com uint8_t texcb() const 14310859Sandreas.sandberg@arm.com { 14410859Sandreas.sandberg@arm.com return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2; 14510859Sandreas.sandberg@arm.com } 14610859Sandreas.sandberg@arm.com 14710859Sandreas.sandberg@arm.com /** If the section is shareable. See texcb() comment. */ 14810859Sandreas.sandberg@arm.com bool shareable() const 14910859Sandreas.sandberg@arm.com { 15010859Sandreas.sandberg@arm.com return bits(data, 16); 15110859Sandreas.sandberg@arm.com } 15210859Sandreas.sandberg@arm.com 15310859Sandreas.sandberg@arm.com /** Set access flag that this entry has been touched. Mark 15410859Sandreas.sandberg@arm.com * the entry as requiring a writeback, in the future. 15510859Sandreas.sandberg@arm.com */ 15610859Sandreas.sandberg@arm.com void setAp0() 15710859Sandreas.sandberg@arm.com { 15810859Sandreas.sandberg@arm.com data |= 1 << 10; 15910859Sandreas.sandberg@arm.com _dirty = true; 16010859Sandreas.sandberg@arm.com } 16110859Sandreas.sandberg@arm.com 16210859Sandreas.sandberg@arm.com /** This entry needs to be written back to memory */ 16310859Sandreas.sandberg@arm.com bool dirty() const 16410859Sandreas.sandberg@arm.com { 16510859Sandreas.sandberg@arm.com return _dirty; 16610859Sandreas.sandberg@arm.com } 16710859Sandreas.sandberg@arm.com }; 16810859Sandreas.sandberg@arm.com 16911168Sandreas.hansson@arm.com /** Level 2 page table descriptor */ 17011168Sandreas.hansson@arm.com struct L2Descriptor { 17110859Sandreas.sandberg@arm.com 17211168Sandreas.hansson@arm.com /** The raw bits of the entry. */ 17311461Sandreas.sandberg@arm.com uint32_t data; 17410859Sandreas.sandberg@arm.com 17510859Sandreas.sandberg@arm.com /** This entry has been modified (access flag set) and needs to be 17610859Sandreas.sandberg@arm.com * written back to memory */ 17711168Sandreas.hansson@arm.com bool _dirty; 17811168Sandreas.hansson@arm.com 17910859Sandreas.sandberg@arm.com /** Is the entry invalid */ 18010859Sandreas.sandberg@arm.com bool invalid() const 18111168Sandreas.hansson@arm.com { 18211168Sandreas.hansson@arm.com return bits(data, 1,0) == 0;; 18310859Sandreas.sandberg@arm.com } 18411168Sandreas.hansson@arm.com 18511168Sandreas.hansson@arm.com /** What is the size of the mapping? */ 18610859Sandreas.sandberg@arm.com bool large() const 18710859Sandreas.sandberg@arm.com { 18810859Sandreas.sandberg@arm.com return bits(data, 1) == 0; 18910859Sandreas.sandberg@arm.com } 19010859Sandreas.sandberg@arm.com 19110859Sandreas.sandberg@arm.com /** Is execution allowed on this mapping? */ 19210859Sandreas.sandberg@arm.com bool xn() const 19310859Sandreas.sandberg@arm.com { 19410859Sandreas.sandberg@arm.com return large() ? bits(data, 15) : bits(data, 0); 19510859Sandreas.sandberg@arm.com } 19610859Sandreas.sandberg@arm.com 19710859Sandreas.sandberg@arm.com /** Is the translation global (no asid used)? */ 19810859Sandreas.sandberg@arm.com bool global() const 19910859Sandreas.sandberg@arm.com { 20010859Sandreas.sandberg@arm.com return !bits(data, 11); 20111461Sandreas.sandberg@arm.com } 20211461Sandreas.sandberg@arm.com 20311461Sandreas.sandberg@arm.com /** Three bit access protection flags */ 20410859Sandreas.sandberg@arm.com uint8_t ap() const 20510859Sandreas.sandberg@arm.com { 20610859Sandreas.sandberg@arm.com return bits(data, 5, 4) | (bits(data, 9) << 2); 20710859Sandreas.sandberg@arm.com } 20810859Sandreas.sandberg@arm.com 209 /** Memory region attributes: ARM DDI 0406B: B3-32 */ 210 uint8_t texcb() const 211 { 212 return large() ? 213 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 14, 12) << 2)) : 214 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 8, 6) << 2)); 215 } 216 217 /** Return the physical frame, bits shifted right */ 218 Addr pfn() const 219 { 220 return large() ? bits(data, 31, 16) : bits(data, 31, 12); 221 } 222 223 /** If the section is shareable. See texcb() comment. */ 224 bool shareable() const 225 { 226 return bits(data, 10); 227 } 228 229 /** Set access flag that this entry has been touched. Mark 230 * the entry as requiring a writeback, in the future. 231 */ 232 void setAp0() 233 { 234 data |= 1 << 4; 235 _dirty = true; 236 } 237 238 /** This entry needs to be written back to memory */ 239 bool dirty() const 240 { 241 return _dirty; 242 } 243 244 }; 245 246 struct WalkerState //: public SimObject 247 { 248 /** Thread context that we're doing the walk for */ 249 ThreadContext *tc; 250 251 /** Request that is currently being serviced */ 252 RequestPtr req; 253 254 /** Context ID that we're servicing the request under */ 255 uint8_t contextId; 256 257 /** Translation state for delayed requests */ 258 TLB::Translation *transState; 259 260 /** The fault that we are going to return */ 261 Fault fault; 262 263 /** The virtual address that is being translated */ 264 Addr vaddr; 265 266 /** Cached copy of the sctlr as it existed when translation began */ 267 SCTLR sctlr; 268 269 /** Cached copy of the cpsr as it existed when the translation began */ 270 CPSR cpsr; 271 272 /** Width of the base address held in TTRB0 */ 273 uint32_t N; 274 275 /** If the access is a write */ 276 bool isWrite; 277 278 /** If the access is not from user mode */ 279 bool isPriv; 280 281 /** If the access is a fetch (for execution, and no-exec) must be checked?*/ 282 bool isFetch; 283 284 /** If the mode is timing or atomic */ 285 bool timing; 286 287 /** Save mode for use in delayed response */ 288 BaseTLB::Mode mode; 289 290 L1Descriptor l1Desc; 291 L2Descriptor l2Desc; 292 293 /** Whether L1/L2 descriptor response is delayed in timing mode */ 294 bool delayed; 295 296 TableWalker *tableWalker; 297 298 void doL1Descriptor(); 299 void doL2Descriptor(); 300 301 std::string name() const {return tableWalker->name();} 302 }; 303 304 305 std::list<WalkerState *> stateQueue; 306 307 /** Port to issue translation requests from */ 308 DmaPort *port; 309 310 /** TLB that is initiating these table walks */ 311 TLB *tlb; 312 313 /** Cached copy of the sctlr as it existed when translation began */ 314 SCTLR sctlr; 315 316 WalkerState *currState; 317 318 public: 319 typedef ArmTableWalkerParams Params; 320 TableWalker(const Params *p); 321 virtual ~TableWalker(); 322 323 const Params * 324 params() const 325 { 326 return dynamic_cast<const Params *>(_params); 327 } 328 329 virtual unsigned int drain(Event *de) { panic("write me\n"); } 330 virtual Port *getPort(const std::string &if_name, int idx = -1); 331 332 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, 333 TLB::Translation *_trans, bool timing); 334 335 void setTlb(TLB *_tlb) { tlb = _tlb; } 336 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 337 uint8_t texcb, bool s); 338 339 private: 340 341 void doL1Descriptor(); 342 void doL1DescriptorWrapper(); 343 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent; 344 345 void doL2Descriptor(); 346 void doL2DescriptorWrapper(); 347 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent; 348 349 350}; 351 352 353} // namespace ArmISA 354 355#endif //__ARCH_ARM_TABLE_WALKER_HH__ 356 357