table_walker.hh revision 10873
1892SN/A/* 21762SN/A * Copyright (c) 2010-2015 ARM Limited 3892SN/A * All rights reserved 4892SN/A * 5892SN/A * The license below extends only to copyright in the software and shall 6892SN/A * not be construed as granting a license to any other intellectual 7892SN/A * property including but not limited to intellectual property relating 8892SN/A * to a hardware implementation of the functionality of the software 9892SN/A * licensed hereunder. You may use the software subject to the license 10892SN/A * terms below provided that you ensure that this notice is replicated 11892SN/A * unmodified and in its entirety in all distributions of the software, 12892SN/A * modified or unmodified, in source code or in binary form. 13892SN/A * 14892SN/A * Redistribution and use in source and binary forms, with or without 15892SN/A * modification, are permitted provided that the following conditions are 16892SN/A * met: redistributions of source code must retain the above copyright 17892SN/A * notice, this list of conditions and the following disclaimer; 18892SN/A * redistributions in binary form must reproduce the above copyright 19892SN/A * notice, this list of conditions and the following disclaimer in the 20892SN/A * documentation and/or other materials provided with the distribution; 21892SN/A * neither the name of the copyright holders nor the names of its 22892SN/A * contributors may be used to endorse or promote products derived from 23892SN/A * this software without specific prior written permission. 24892SN/A * 25892SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26892SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30892SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31768SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 321730SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33768SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34768SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3511244Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36768SN/A * 37768SN/A * Authors: Ali Saidi 38768SN/A * Giacomo Gabrielli 39768SN/A */ 40768SN/A 41768SN/A#ifndef __ARCH_ARM_TABLE_WALKER_HH__ 426658Snate@binkert.org#define __ARCH_ARM_TABLE_WALKER_HH__ 438232Snate@binkert.org 448229Snate@binkert.org#include <list> 4511244Sandreas.sandberg@arm.com 463540Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 4711260Sandreas.sandberg@arm.com#include "arch/arm/system.hh" 482542SN/A#include "arch/arm/tlb.hh" 493348SN/A#include "mem/request.hh" 50768SN/A#include "params/ArmTableWalker.hh" 51768SN/A#include "sim/eventq.hh" 52768SN/A 532107SN/Aclass ThreadContext; 542107SN/A 55768SN/Aclass DmaPort; 564762Snate@binkert.org 5711244Sandreas.sandberg@arm.comnamespace ArmISA { 5811244Sandreas.sandberg@arm.comclass Translation; 5911244Sandreas.sandberg@arm.comclass TLB; 60768SN/Aclass Stage2MMU; 61835SN/A 62835SN/Aclass TableWalker : public MemObject 63835SN/A{ 64835SN/A public: 65835SN/A class WalkerState; 66768SN/A 67896SN/A class DescriptorBase { 68896SN/A public: 69896SN/A /** Current lookup level for this descriptor */ 70775SN/A LookupLevel lookupLevel; 712539SN/A 722539SN/A virtual Addr pfn() const = 0; 732539SN/A virtual TlbEntry::DomainType domain() const = 0; 742539SN/A virtual bool xn() const = 0; 753349SN/A virtual uint8_t ap() const = 0; 762539SN/A virtual bool global(WalkerState *currState) const = 0; 7711244Sandreas.sandberg@arm.com virtual uint8_t offsetBits() const = 0; 7811244Sandreas.sandberg@arm.com virtual bool secure(bool have_security, WalkerState *currState) const = 0; 7911244Sandreas.sandberg@arm.com virtual std::string dbgHeader() const = 0; 8011244Sandreas.sandberg@arm.com virtual uint64_t getRawData() const = 0; 812539SN/A virtual uint8_t texcb() const 8211244Sandreas.sandberg@arm.com { 832641SN/A panic("texcb() not implemented for this class\n"); 842539SN/A } 852539SN/A virtual bool shareable() const 862641SN/A { 872539SN/A panic("shareable() not implemented for this class\n"); 882539SN/A } 892539SN/A }; 9013232Sgabeblack@google.com 912539SN/A class L1Descriptor : public DescriptorBase { 922539SN/A public: 9313232Sgabeblack@google.com /** Type of page table entry ARM DDI 0406B: B3-8*/ 942539SN/A enum EntryType { 952539SN/A Ignore, 9613232Sgabeblack@google.com PageTable, 972539SN/A Section, 982539SN/A Reserved 9913232Sgabeblack@google.com }; 1002539SN/A 1012539SN/A /** The raw bits of the entry */ 10213232Sgabeblack@google.com uint32_t data; 1032539SN/A 1042539SN/A /** This entry has been modified (access flag set) and needs to be 10513232Sgabeblack@google.com * written back to memory */ 1062539SN/A bool _dirty; 1072539SN/A 10813232Sgabeblack@google.com /** Default ctor */ 1092539SN/A L1Descriptor() : data(0), _dirty(false) 1102539SN/A { 11113232Sgabeblack@google.com lookupLevel = L1; 1122539SN/A } 1132539SN/A 11413232Sgabeblack@google.com virtual uint64_t getRawData() const 1152539SN/A { 1162539SN/A return (data); 11713232Sgabeblack@google.com } 1182539SN/A 1192539SN/A virtual std::string dbgHeader() const 12013232Sgabeblack@google.com { 1212539SN/A return "Inserting Section Descriptor into TLB\n"; 1222542SN/A } 12313232Sgabeblack@google.com 1242539SN/A virtual uint8_t offsetBits() const 1252539SN/A { 12613232Sgabeblack@google.com return 20; 1272539SN/A } 1282539SN/A 1292539SN/A EntryType type() const 1302539SN/A { 1312539SN/A return (EntryType)(data & 0x3); 1322539SN/A } 13313232Sgabeblack@google.com 1342539SN/A /** Is the page a Supersection (16MB)?*/ 1352539SN/A bool supersection() const 13613232Sgabeblack@google.com { 1372539SN/A return bits(data, 18); 1382539SN/A } 1392539SN/A 1402539SN/A /** Return the physcal address of the entry, bits in position*/ 1412539SN/A Addr paddr() const 1422539SN/A { 14313232Sgabeblack@google.com if (supersection()) 1442539SN/A panic("Super sections not implemented\n"); 1452539SN/A return mbits(data, 31, 20); 1462539SN/A } 1472539SN/A /** Return the physcal address of the entry, bits in position*/ 1482539SN/A Addr paddr(Addr va) const 1492539SN/A { 1502539SN/A if (supersection()) 1512539SN/A panic("Super sections not implemented\n"); 15211244Sandreas.sandberg@arm.com return mbits(data, 31, 20) | mbits(va, 19, 0); 1534870Sstever@eecs.umich.edu } 1542539SN/A 1552539SN/A 156768SN/A /** Return the physical frame, bits shifted right */ 157768SN/A Addr pfn() const 1582542SN/A { 1593349SN/A if (supersection()) 160768SN/A panic("Super sections not implemented\n"); 16111244Sandreas.sandberg@arm.com return bits(data, 31, 20); 16211244Sandreas.sandberg@arm.com } 16311244Sandreas.sandberg@arm.com 16411244Sandreas.sandberg@arm.com /** Is the translation global (no asid used)? */ 16511244Sandreas.sandberg@arm.com bool global(WalkerState *currState) const 16611244Sandreas.sandberg@arm.com { 167768SN/A return !bits(data, 17); 1682641SN/A } 169768SN/A 1702641SN/A /** Is the translation not allow execution? */ 171768SN/A bool xn() const 1722539SN/A { 1732539SN/A return bits(data, 4); 17413232Sgabeblack@google.com } 1752539SN/A 1762539SN/A /** Three bit access protection flags */ 17713232Sgabeblack@google.com uint8_t ap() const 1782539SN/A { 1792539SN/A return (bits(data, 15) << 2) | bits(data, 11, 10); 18013232Sgabeblack@google.com } 1812539SN/A 1822539SN/A /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ 18313232Sgabeblack@google.com TlbEntry::DomainType domain() const 1842539SN/A { 1852539SN/A return static_cast<TlbEntry::DomainType>(bits(data, 8, 5)); 18613232Sgabeblack@google.com } 1872539SN/A 1882539SN/A /** Address of L2 descriptor if it exists */ 18913232Sgabeblack@google.com Addr l2Addr() const 1902539SN/A { 1912539SN/A return mbits(data, 31, 10); 19213232Sgabeblack@google.com } 1932539SN/A 1942539SN/A /** Memory region attributes: ARM DDI 0406B: B3-32. 19513232Sgabeblack@google.com * These bits are largly ignored by M5 and only used to 1962539SN/A * provide the illusion that the memory system cares about 1972539SN/A * anything but cachable vs. uncachable. 19813232Sgabeblack@google.com */ 1992539SN/A uint8_t texcb() const 2002539SN/A { 20113232Sgabeblack@google.com return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2; 2022539SN/A } 2032539SN/A 20413232Sgabeblack@google.com /** If the section is shareable. See texcb() comment. */ 2052539SN/A bool shareable() const 2062539SN/A { 20713232Sgabeblack@google.com return bits(data, 16); 2082539SN/A } 2092539SN/A 21013232Sgabeblack@google.com /** Set access flag that this entry has been touched. Mark 2112539SN/A * the entry as requiring a writeback, in the future. 2122539SN/A */ 2132539SN/A void setAp0() 2142539SN/A { 2152539SN/A data |= 1 << 10; 2162539SN/A _dirty = true; 2172539SN/A } 2182539SN/A 2192539SN/A /** This entry needs to be written back to memory */ 2202539SN/A bool dirty() const 2212539SN/A { 2222539SN/A return _dirty; 2232539SN/A } 2242539SN/A 2252539SN/A /** 2262539SN/A * Returns true if this entry targets the secure physical address 2272539SN/A * map. 2282539SN/A */ 2292539SN/A bool secure(bool have_security, WalkerState *currState) const 2302539SN/A { 2312549SN/A if (have_security) { 232768SN/A if (type() == PageTable) 2332539SN/A return !bits(data, 3); 234768SN/A else 2354870Sstever@eecs.umich.edu return !bits(data, 19); 2362539SN/A } 237768SN/A return false; 238768SN/A } 23911244Sandreas.sandberg@arm.com }; 24011244Sandreas.sandberg@arm.com 24111244Sandreas.sandberg@arm.com /** Level 2 page table descriptor */ 24211244Sandreas.sandberg@arm.com class L2Descriptor : public DescriptorBase { 24311244Sandreas.sandberg@arm.com public: 24411244Sandreas.sandberg@arm.com /** The raw bits of the entry. */ 24511244Sandreas.sandberg@arm.com uint32_t data; 24611244Sandreas.sandberg@arm.com L1Descriptor *l1Parent; 24711244Sandreas.sandberg@arm.com 24811244Sandreas.sandberg@arm.com /** This entry has been modified (access flag set) and needs to be 24911244Sandreas.sandberg@arm.com * written back to memory */ 250857SN/A bool _dirty; 251857SN/A 252835SN/A /** Default ctor */ 25311244Sandreas.sandberg@arm.com L2Descriptor() : data(0), l1Parent(nullptr), _dirty(false) 254835SN/A { 255835SN/A lookupLevel = L2; 256857SN/A } 257857SN/A 258857SN/A L2Descriptor(L1Descriptor &parent) : data(0), l1Parent(&parent), 259835SN/A _dirty(false) 260835SN/A { 261857SN/A lookupLevel = L2; 262857SN/A } 263857SN/A 264857SN/A virtual uint64_t getRawData() const 265835SN/A { 266835SN/A return (data); 267896SN/A } 268896SN/A 269896SN/A virtual std::string dbgHeader() const 270896SN/A { 271896SN/A return "Inserting L2 Descriptor into TLB\n"; 272896SN/A } 273835SN/A 274835SN/A virtual TlbEntry::DomainType domain() const 275857SN/A { 276857SN/A return l1Parent->domain(); 277857SN/A } 278857SN/A 279857SN/A bool secure(bool have_security, WalkerState *currState) const 280857SN/A { 281857SN/A return l1Parent->secure(have_security, currState); 282857SN/A } 283857SN/A 284857SN/A virtual uint8_t offsetBits() const 285835SN/A { 28614010Sgabeblack@google.com return large() ? 16 : 12; 28714010Sgabeblack@google.com } 288896SN/A 289857SN/A /** Is the entry invalid */ 290857SN/A bool invalid() const 29114010Sgabeblack@google.com { 2928853Sandreas.hansson@arm.com return bits(data, 1, 0) == 0; 293857SN/A } 29414010Sgabeblack@google.com 29514010Sgabeblack@google.com /** What is the size of the mapping? */ 296857SN/A bool large() const 297857SN/A { 298896SN/A return bits(data, 1) == 0; 299857SN/A } 300857SN/A 301857SN/A /** Is execution allowed on this mapping? */ 302857SN/A bool xn() const 303857SN/A { 304835SN/A return large() ? bits(data, 15) : bits(data, 0); 305835SN/A } 306835SN/A 307835SN/A /** Is the translation global (no asid used)? */ 308896SN/A bool global(WalkerState *currState) const 309896SN/A { 310835SN/A return !bits(data, 11); 3115834Sgblack@eecs.umich.edu } 312768SN/A 31310905Sandreas.sandberg@arm.com /** Three bit access protection flags */ 314768SN/A uint8_t ap() const 315896SN/A { 316835SN/A return bits(data, 5, 4) | (bits(data, 9) << 2); 317835SN/A } 318835SN/A 319768SN/A /** Memory region attributes: ARM DDI 0406B: B3-32 */ 320768SN/A uint8_t texcb() const 321768SN/A { 32210905Sandreas.sandberg@arm.com return large() ? 323768SN/A (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) : 324896SN/A (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2)); 325835SN/A } 326835SN/A 327835SN/A /** Return the physical frame, bits shifted right */ 328768SN/A Addr pfn() const 329768SN/A { 330909SN/A return large() ? bits(data, 31, 16) : bits(data, 31, 12); 3314762Snate@binkert.org } 3324762Snate@binkert.org 333768SN/A /** Return complete physical address given a VA */ 3344762Snate@binkert.org Addr paddr(Addr va) const 335768SN/A { 336 if (large()) 337 return mbits(data, 31, 16) | mbits(va, 15, 0); 338 else 339 return mbits(data, 31, 12) | mbits(va, 11, 0); 340 } 341 342 /** If the section is shareable. See texcb() comment. */ 343 bool shareable() const 344 { 345 return bits(data, 10); 346 } 347 348 /** Set access flag that this entry has been touched. Mark 349 * the entry as requiring a writeback, in the future. 350 */ 351 void setAp0() 352 { 353 data |= 1 << 4; 354 _dirty = true; 355 } 356 357 /** This entry needs to be written back to memory */ 358 bool dirty() const 359 { 360 return _dirty; 361 } 362 363 }; 364 365 // Granule sizes for AArch64 long descriptors 366 enum GrainSize { 367 Grain4KB = 12, 368 Grain16KB = 14, 369 Grain64KB = 16, 370 ReservedGrain = 0 371 }; 372 373 /** Long-descriptor format (LPAE) */ 374 class LongDescriptor : public DescriptorBase { 375 public: 376 /** Descriptor type */ 377 enum EntryType { 378 Invalid, 379 Table, 380 Block, 381 Page 382 }; 383 384 /** The raw bits of the entry */ 385 uint64_t data; 386 387 /** This entry has been modified (access flag set) and needs to be 388 * written back to memory */ 389 bool _dirty; 390 391 virtual uint64_t getRawData() const 392 { 393 return (data); 394 } 395 396 virtual std::string dbgHeader() const 397 { 398 if (type() == LongDescriptor::Page) { 399 assert(lookupLevel == L3); 400 return "Inserting Page descriptor into TLB\n"; 401 } else { 402 assert(lookupLevel < L3); 403 return "Inserting Block descriptor into TLB\n"; 404 } 405 } 406 407 /** 408 * Returns true if this entry targets the secure physical address 409 * map. 410 */ 411 bool secure(bool have_security, WalkerState *currState) const 412 { 413 assert(type() == Block || type() == Page); 414 return have_security && (currState->secureLookup && !bits(data, 5)); 415 } 416 417 /** True if the current lookup is performed in AArch64 state */ 418 bool aarch64; 419 420 /** Width of the granule size in bits */ 421 GrainSize grainSize; 422 423 /** Return the descriptor type */ 424 EntryType type() const 425 { 426 switch (bits(data, 1, 0)) { 427 case 0x1: 428 // In AArch64 blocks are not allowed at L0 for the 4 KB granule 429 // and at L1 for 16/64 KB granules 430 if (grainSize > Grain4KB) 431 return lookupLevel == L2 ? Block : Invalid; 432 return lookupLevel == L0 || lookupLevel == L3 ? Invalid : Block; 433 case 0x3: 434 return lookupLevel == L3 ? Page : Table; 435 default: 436 return Invalid; 437 } 438 } 439 440 /** Return the bit width of the page/block offset */ 441 uint8_t offsetBits() const 442 { 443 if (type() == Block) { 444 switch (grainSize) { 445 case Grain4KB: 446 return lookupLevel == L1 ? 30 /* 1 GB */ 447 : 21 /* 2 MB */; 448 case Grain16KB: 449 return 25 /* 32 MB */; 450 case Grain64KB: 451 return 29 /* 512 MB */; 452 default: 453 panic("Invalid AArch64 VM granule size\n"); 454 } 455 } else if (type() == Page) { 456 switch (grainSize) { 457 case Grain4KB: 458 case Grain16KB: 459 case Grain64KB: 460 return grainSize; /* enum -> uint okay */ 461 default: 462 panic("Invalid AArch64 VM granule size\n"); 463 } 464 } else { 465 panic("AArch64 page table entry must be block or page\n"); 466 } 467 } 468 469 /** Return the physical frame, bits shifted right */ 470 Addr pfn() const 471 { 472 if (aarch64) 473 return bits(data, 47, offsetBits()); 474 return bits(data, 39, offsetBits()); 475 } 476 477 /** Return the complete physical address given a VA */ 478 Addr paddr(Addr va) const 479 { 480 int n = offsetBits(); 481 if (aarch64) 482 return mbits(data, 47, n) | mbits(va, n - 1, 0); 483 return mbits(data, 39, n) | mbits(va, n - 1, 0); 484 } 485 486 /** Return the physical address of the entry */ 487 Addr paddr() const 488 { 489 if (aarch64) 490 return mbits(data, 47, offsetBits()); 491 return mbits(data, 39, offsetBits()); 492 } 493 494 /** Return the address of the next page table */ 495 Addr nextTableAddr() const 496 { 497 assert(type() == Table); 498 if (aarch64) 499 return mbits(data, 47, grainSize); 500 else 501 return mbits(data, 39, 12); 502 } 503 504 /** Return the address of the next descriptor */ 505 Addr nextDescAddr(Addr va) const 506 { 507 assert(type() == Table); 508 Addr pa = 0; 509 if (aarch64) { 510 int stride = grainSize - 3; 511 int va_lo = stride * (3 - (lookupLevel + 1)) + grainSize; 512 int va_hi = va_lo + stride - 1; 513 pa = nextTableAddr() | (bits(va, va_hi, va_lo) << 3); 514 } else { 515 if (lookupLevel == L1) 516 pa = nextTableAddr() | (bits(va, 29, 21) << 3); 517 else // lookupLevel == L2 518 pa = nextTableAddr() | (bits(va, 20, 12) << 3); 519 } 520 return pa; 521 } 522 523 /** Is execution allowed on this mapping? */ 524 bool xn() const 525 { 526 assert(type() == Block || type() == Page); 527 return bits(data, 54); 528 } 529 530 /** Is privileged execution allowed on this mapping? (LPAE only) */ 531 bool pxn() const 532 { 533 assert(type() == Block || type() == Page); 534 return bits(data, 53); 535 } 536 537 /** Contiguous hint bit. */ 538 bool contiguousHint() const 539 { 540 assert(type() == Block || type() == Page); 541 return bits(data, 52); 542 } 543 544 /** Is the translation global (no asid used)? */ 545 bool global(WalkerState *currState) const 546 { 547 assert(currState && (type() == Block || type() == Page)); 548 if (!currState->aarch64 && (currState->isSecure && 549 !currState->secureLookup)) { 550 return false; // ARM ARM issue C B3.6.3 551 } else if (currState->aarch64) { 552 if (currState->el == EL2 || currState->el == EL3) { 553 return true; // By default translations are treated as global 554 // in AArch64 EL2 and EL3 555 } else if (currState->isSecure && !currState->secureLookup) { 556 return false; 557 } 558 } 559 return !bits(data, 11); 560 } 561 562 /** Returns true if the access flag (AF) is set. */ 563 bool af() const 564 { 565 assert(type() == Block || type() == Page); 566 return bits(data, 10); 567 } 568 569 /** 2-bit shareability field */ 570 uint8_t sh() const 571 { 572 assert(type() == Block || type() == Page); 573 return bits(data, 9, 8); 574 } 575 576 /** 2-bit access protection flags */ 577 uint8_t ap() const 578 { 579 assert(type() == Block || type() == Page); 580 // Long descriptors only support the AP[2:1] scheme 581 return bits(data, 7, 6); 582 } 583 584 /** Read/write access protection flag */ 585 bool rw() const 586 { 587 assert(type() == Block || type() == Page); 588 return !bits(data, 7); 589 } 590 591 /** User/privileged level access protection flag */ 592 bool user() const 593 { 594 assert(type() == Block || type() == Page); 595 return bits(data, 6); 596 } 597 598 /** Return the AP bits as compatible with the AP[2:0] format. Utility 599 * function used to simplify the code in the TLB for performing 600 * permission checks. */ 601 static uint8_t ap(bool rw, bool user) 602 { 603 return ((!rw) << 2) | (user << 1); 604 } 605 606 TlbEntry::DomainType domain() const 607 { 608 // Long-desc. format only supports Client domain 609 assert(type() == Block || type() == Page); 610 return TlbEntry::DomainType::Client; 611 } 612 613 /** Attribute index */ 614 uint8_t attrIndx() const 615 { 616 assert(type() == Block || type() == Page); 617 return bits(data, 4, 2); 618 } 619 620 /** Memory attributes, only used by stage 2 translations */ 621 uint8_t memAttr() const 622 { 623 assert(type() == Block || type() == Page); 624 return bits(data, 5, 2); 625 } 626 627 /** Set access flag that this entry has been touched. Mark the entry as 628 * requiring a writeback, in the future. */ 629 void setAf() 630 { 631 data |= 1 << 10; 632 _dirty = true; 633 } 634 635 /** This entry needs to be written back to memory */ 636 bool dirty() const 637 { 638 return _dirty; 639 } 640 641 /** Whether the subsequent levels of lookup are secure */ 642 bool secureTable() const 643 { 644 assert(type() == Table); 645 return !bits(data, 63); 646 } 647 648 /** Two bit access protection flags for subsequent levels of lookup */ 649 uint8_t apTable() const 650 { 651 assert(type() == Table); 652 return bits(data, 62, 61); 653 } 654 655 /** R/W protection flag for subsequent levels of lookup */ 656 uint8_t rwTable() const 657 { 658 assert(type() == Table); 659 return !bits(data, 62); 660 } 661 662 /** User/privileged mode protection flag for subsequent levels of 663 * lookup */ 664 uint8_t userTable() const 665 { 666 assert(type() == Table); 667 return !bits(data, 61); 668 } 669 670 /** Is execution allowed on subsequent lookup levels? */ 671 bool xnTable() const 672 { 673 assert(type() == Table); 674 return bits(data, 60); 675 } 676 677 /** Is privileged execution allowed on subsequent lookup levels? */ 678 bool pxnTable() const 679 { 680 assert(type() == Table); 681 return bits(data, 59); 682 } 683 }; 684 685 class WalkerState 686 { 687 public: 688 /** Thread context that we're doing the walk for */ 689 ThreadContext *tc; 690 691 /** If the access is performed in AArch64 state */ 692 bool aarch64; 693 694 /** Current exception level */ 695 ExceptionLevel el; 696 697 /** Current physical address range in bits */ 698 int physAddrRange; 699 700 /** Request that is currently being serviced */ 701 RequestPtr req; 702 703 /** ASID that we're servicing the request under */ 704 uint16_t asid; 705 uint8_t vmid; 706 bool isHyp; 707 708 /** Translation state for delayed requests */ 709 TLB::Translation *transState; 710 711 /** The fault that we are going to return */ 712 Fault fault; 713 714 /** The virtual address that is being translated with tagging removed.*/ 715 Addr vaddr; 716 717 /** The virtual address that is being translated */ 718 Addr vaddr_tainted; 719 720 /** Cached copy of the sctlr as it existed when translation began */ 721 SCTLR sctlr; 722 723 /** Cached copy of the scr as it existed when translation began */ 724 SCR scr; 725 726 /** Cached copy of the cpsr as it existed when translation began */ 727 CPSR cpsr; 728 729 /** Cached copy of ttbcr/tcr as it existed when translation began */ 730 union { 731 TTBCR ttbcr; // AArch32 translations 732 TCR tcr; // AArch64 translations 733 }; 734 735 /** Cached copy of the htcr as it existed when translation began. */ 736 HTCR htcr; 737 738 /** Cached copy of the htcr as it existed when translation began. */ 739 HCR hcr; 740 741 /** Cached copy of the vtcr as it existed when translation began. */ 742 VTCR_t vtcr; 743 744 /** If the access is a write */ 745 bool isWrite; 746 747 /** If the access is a fetch (for execution, and no-exec) must be checked?*/ 748 bool isFetch; 749 750 /** If the access comes from the secure state. */ 751 bool isSecure; 752 753 /** Helper variables used to implement hierarchical access permissions 754 * when the long-desc. format is used (LPAE only) */ 755 bool secureLookup; 756 bool rwTable; 757 bool userTable; 758 bool xnTable; 759 bool pxnTable; 760 761 /** Flag indicating if a second stage of lookup is required */ 762 bool stage2Req; 763 764 /** Indicates whether the translation has been passed onto the second 765 * stage mmu, and no more work is required from the first stage. 766 */ 767 bool doingStage2; 768 769 /** A pointer to the stage 2 translation that's in progress */ 770 TLB::Translation *stage2Tran; 771 772 /** If the mode is timing or atomic */ 773 bool timing; 774 775 /** If the atomic mode should be functional */ 776 bool functional; 777 778 /** Save mode for use in delayed response */ 779 BaseTLB::Mode mode; 780 781 /** The translation type that has been requested */ 782 TLB::ArmTranslationType tranType; 783 784 /** Short-format descriptors */ 785 L1Descriptor l1Desc; 786 L2Descriptor l2Desc; 787 788 /** Long-format descriptor (LPAE and AArch64) */ 789 LongDescriptor longDesc; 790 791 /** Whether the response is delayed in timing mode due to additional 792 * lookups */ 793 bool delayed; 794 795 TableWalker *tableWalker; 796 797 /** Timestamp for calculating elapsed time in service (for stats) */ 798 Tick startTime; 799 800 /** Page entries walked during service (for stats) */ 801 unsigned levels; 802 803 void doL1Descriptor(); 804 void doL2Descriptor(); 805 806 void doLongDescriptor(); 807 808 WalkerState(); 809 810 std::string name() const { return tableWalker->name(); } 811 }; 812 813 protected: 814 815 /** Queues of requests for all the different lookup levels */ 816 std::list<WalkerState *> stateQueues[MAX_LOOKUP_LEVELS]; 817 818 /** Queue of requests that have passed are waiting because the walker is 819 * currently busy. */ 820 std::list<WalkerState *> pendingQueue; 821 822 /** If we're draining keep the drain event around until we're drained */ 823 DrainManager *drainManager; 824 825 /** The MMU to forward second stage look upts to */ 826 Stage2MMU *stage2Mmu; 827 828 /** Port shared by the two table walkers. */ 829 DmaPort* port; 830 831 /** Master id assigned by the MMU. */ 832 MasterID masterId; 833 834 /** Indicates whether this table walker is part of the stage 2 mmu */ 835 const bool isStage2; 836 837 /** TLB that is initiating these table walks */ 838 TLB *tlb; 839 840 /** Cached copy of the sctlr as it existed when translation began */ 841 SCTLR sctlr; 842 843 WalkerState *currState; 844 845 /** If a timing translation is currently in progress */ 846 bool pending; 847 848 /** The number of walks belonging to squashed instructions that can be 849 * removed from the pendingQueue per cycle. */ 850 unsigned numSquashable; 851 852 /** Cached copies of system-level properties */ 853 bool haveSecurity; 854 bool _haveLPAE; 855 bool _haveVirtualization; 856 uint8_t physAddrRange; 857 bool _haveLargeAsid64; 858 859 /** Statistics */ 860 Stats::Scalar statWalks; 861 Stats::Scalar statWalksShortDescriptor; 862 Stats::Scalar statWalksLongDescriptor; 863 Stats::Vector statWalksShortTerminatedAtLevel; 864 Stats::Vector statWalksLongTerminatedAtLevel; 865 Stats::Scalar statSquashedBefore; 866 Stats::Scalar statSquashedAfter; 867 Stats::Histogram statWalkWaitTime; 868 Stats::Histogram statWalkServiceTime; 869 Stats::Histogram statPendingWalks; // essentially "L" of queueing theory 870 Stats::Vector statPageSizes; 871 Stats::Vector2d statRequestOrigin; 872 873 mutable unsigned pendingReqs; 874 mutable Tick pendingChangeTick; 875 876 static const unsigned REQUESTED = 0; 877 static const unsigned COMPLETED = 1; 878 879 public: 880 typedef ArmTableWalkerParams Params; 881 TableWalker(const Params *p); 882 virtual ~TableWalker(); 883 884 const Params * 885 params() const 886 { 887 return dynamic_cast<const Params *>(_params); 888 } 889 890 virtual void init(); 891 892 bool haveLPAE() const { return _haveLPAE; } 893 bool haveVirtualization() const { return _haveVirtualization; } 894 bool haveLargeAsid64() const { return _haveLargeAsid64; } 895 /** Checks if all state is cleared and if so, completes drain */ 896 void completeDrain(); 897 unsigned int drain(DrainManager *dm); 898 virtual void drainResume(); 899 900 virtual BaseMasterPort& getMasterPort(const std::string &if_name, 901 PortID idx = InvalidPortID); 902 903 void regStats(); 904 905 Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid, 906 bool _isHyp, TLB::Mode mode, TLB::Translation *_trans, 907 bool timing, bool functional, bool secure, 908 TLB::ArmTranslationType tranType); 909 910 void setTlb(TLB *_tlb) { tlb = _tlb; } 911 TLB* getTlb() { return tlb; } 912 void setMMU(Stage2MMU *m, MasterID master_id); 913 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 914 uint8_t texcb, bool s); 915 void memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 916 LongDescriptor &lDescriptor); 917 void memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx, 918 uint8_t sh); 919 920 static LookupLevel toLookupLevel(uint8_t lookup_level_as_int); 921 922 private: 923 924 void doL1Descriptor(); 925 void doL1DescriptorWrapper(); 926 EventWrapper<TableWalker, 927 &TableWalker::doL1DescriptorWrapper> doL1DescEvent; 928 929 void doL2Descriptor(); 930 void doL2DescriptorWrapper(); 931 EventWrapper<TableWalker, 932 &TableWalker::doL2DescriptorWrapper> doL2DescEvent; 933 934 void doLongDescriptor(); 935 936 void doL0LongDescriptorWrapper(); 937 EventWrapper<TableWalker, 938 &TableWalker::doL0LongDescriptorWrapper> doL0LongDescEvent; 939 void doL1LongDescriptorWrapper(); 940 EventWrapper<TableWalker, 941 &TableWalker::doL1LongDescriptorWrapper> doL1LongDescEvent; 942 void doL2LongDescriptorWrapper(); 943 EventWrapper<TableWalker, 944 &TableWalker::doL2LongDescriptorWrapper> doL2LongDescEvent; 945 void doL3LongDescriptorWrapper(); 946 EventWrapper<TableWalker, 947 &TableWalker::doL3LongDescriptorWrapper> doL3LongDescEvent; 948 949 void doLongDescriptorWrapper(LookupLevel curr_lookup_level); 950 951 bool fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 952 Request::Flags flags, int queueIndex, Event *event, 953 void (TableWalker::*doDescriptor)()); 954 955 void insertTableEntry(DescriptorBase &descriptor, bool longDescriptor); 956 957 Fault processWalk(); 958 Fault processWalkLPAE(); 959 static unsigned adjustTableSizeAArch64(unsigned tsz); 960 /// Returns true if the address exceeds the range permitted by the 961 /// system-wide setting or by the TCR_ELx IPS/PS setting 962 static bool checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange); 963 Fault processWalkAArch64(); 964 void processWalkWrapper(); 965 EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent; 966 967 void nextWalk(ThreadContext *tc); 968 969 void pendingChange(); 970 971 static uint8_t pageSizeNtoStatBin(uint8_t N); 972}; 973 974} // namespace ArmISA 975 976#endif //__ARCH_ARM_TABLE_WALKER_HH__ 977 978