table_walker.hh revision 11169
17404SAli.Saidi@ARM.com/* 27404SAli.Saidi@ARM.com * Copyright (c) 2010-2015 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 387404SAli.Saidi@ARM.com * Giacomo Gabrielli 397404SAli.Saidi@ARM.com */ 407404SAli.Saidi@ARM.com 417404SAli.Saidi@ARM.com#ifndef __ARCH_ARM_TABLE_WALKER_HH__ 427404SAli.Saidi@ARM.com#define __ARCH_ARM_TABLE_WALKER_HH__ 437404SAli.Saidi@ARM.com 447404SAli.Saidi@ARM.com#include <list> 457404SAli.Saidi@ARM.com 467404SAli.Saidi@ARM.com#include "arch/arm/miscregs.hh" 477404SAli.Saidi@ARM.com#include "arch/arm/system.hh" 487404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 497404SAli.Saidi@ARM.com#include "mem/request.hh" 507404SAli.Saidi@ARM.com#include "params/ArmTableWalker.hh" 517439Sdam.sunwoo@arm.com#include "sim/eventq.hh" 527404SAli.Saidi@ARM.com 537404SAli.Saidi@ARM.comclass ThreadContext; 547404SAli.Saidi@ARM.com 557404SAli.Saidi@ARM.comclass DmaPort; 567404SAli.Saidi@ARM.com 577404SAli.Saidi@ARM.comnamespace ArmISA { 587404SAli.Saidi@ARM.comclass Translation; 597404SAli.Saidi@ARM.comclass TLB; 607404SAli.Saidi@ARM.comclass Stage2MMU; 617404SAli.Saidi@ARM.com 627404SAli.Saidi@ARM.comclass TableWalker : public MemObject 637404SAli.Saidi@ARM.com{ 647404SAli.Saidi@ARM.com public: 657404SAli.Saidi@ARM.com class WalkerState; 667404SAli.Saidi@ARM.com 677404SAli.Saidi@ARM.com class DescriptorBase { 687404SAli.Saidi@ARM.com public: 697404SAli.Saidi@ARM.com /** Current lookup level for this descriptor */ 707404SAli.Saidi@ARM.com LookupLevel lookupLevel; 717404SAli.Saidi@ARM.com 727436Sdam.sunwoo@arm.com virtual Addr pfn() const = 0; 737404SAli.Saidi@ARM.com virtual TlbEntry::DomainType domain() const = 0; 747404SAli.Saidi@ARM.com virtual bool xn() const = 0; 757436Sdam.sunwoo@arm.com virtual uint8_t ap() const = 0; 767436Sdam.sunwoo@arm.com virtual bool global(WalkerState *currState) const = 0; 777436Sdam.sunwoo@arm.com virtual uint8_t offsetBits() const = 0; 787436Sdam.sunwoo@arm.com virtual bool secure(bool have_security, WalkerState *currState) const = 0; 797404SAli.Saidi@ARM.com virtual std::string dbgHeader() const = 0; 807404SAli.Saidi@ARM.com virtual uint64_t getRawData() const = 0; 817404SAli.Saidi@ARM.com virtual uint8_t texcb() const 827404SAli.Saidi@ARM.com { 837404SAli.Saidi@ARM.com panic("texcb() not implemented for this class\n"); 847404SAli.Saidi@ARM.com } 857404SAli.Saidi@ARM.com virtual bool shareable() const 867404SAli.Saidi@ARM.com { 877404SAli.Saidi@ARM.com panic("shareable() not implemented for this class\n"); 887404SAli.Saidi@ARM.com } 897404SAli.Saidi@ARM.com }; 907404SAli.Saidi@ARM.com 917404SAli.Saidi@ARM.com class L1Descriptor : public DescriptorBase { 927404SAli.Saidi@ARM.com public: 937404SAli.Saidi@ARM.com /** Type of page table entry ARM DDI 0406B: B3-8*/ 947404SAli.Saidi@ARM.com enum EntryType { 957404SAli.Saidi@ARM.com Ignore, 967404SAli.Saidi@ARM.com PageTable, 977404SAli.Saidi@ARM.com Section, 987404SAli.Saidi@ARM.com Reserved 997404SAli.Saidi@ARM.com }; 1007404SAli.Saidi@ARM.com 1017404SAli.Saidi@ARM.com /** The raw bits of the entry */ 1027404SAli.Saidi@ARM.com uint32_t data; 1037404SAli.Saidi@ARM.com 1047404SAli.Saidi@ARM.com /** This entry has been modified (access flag set) and needs to be 1057404SAli.Saidi@ARM.com * written back to memory */ 1067404SAli.Saidi@ARM.com bool _dirty; 1077404SAli.Saidi@ARM.com 1087404SAli.Saidi@ARM.com /** Default ctor */ 1097406SAli.Saidi@ARM.com L1Descriptor() : data(0), _dirty(false) 1107404SAli.Saidi@ARM.com { 1117404SAli.Saidi@ARM.com lookupLevel = L1; 1127404SAli.Saidi@ARM.com } 1137404SAli.Saidi@ARM.com 1147404SAli.Saidi@ARM.com virtual uint64_t getRawData() const 1157404SAli.Saidi@ARM.com { 1167404SAli.Saidi@ARM.com return (data); 1177404SAli.Saidi@ARM.com } 1187404SAli.Saidi@ARM.com 1197404SAli.Saidi@ARM.com virtual std::string dbgHeader() const 1207404SAli.Saidi@ARM.com { 1217404SAli.Saidi@ARM.com return "Inserting Section Descriptor into TLB\n"; 1227404SAli.Saidi@ARM.com } 1237404SAli.Saidi@ARM.com 1247404SAli.Saidi@ARM.com virtual uint8_t offsetBits() const 1257404SAli.Saidi@ARM.com { 1267404SAli.Saidi@ARM.com return 20; 1277404SAli.Saidi@ARM.com } 1287404SAli.Saidi@ARM.com 1297404SAli.Saidi@ARM.com EntryType type() const 1307404SAli.Saidi@ARM.com { 1317404SAli.Saidi@ARM.com return (EntryType)(data & 0x3); 1327404SAli.Saidi@ARM.com } 1337404SAli.Saidi@ARM.com 1347404SAli.Saidi@ARM.com /** Is the page a Supersection (16MB)?*/ 1357404SAli.Saidi@ARM.com bool supersection() const 1367436Sdam.sunwoo@arm.com { 1377436Sdam.sunwoo@arm.com return bits(data, 18); 1387436Sdam.sunwoo@arm.com } 1397436Sdam.sunwoo@arm.com 1407436Sdam.sunwoo@arm.com /** Return the physcal address of the entry, bits in position*/ 1417404SAli.Saidi@ARM.com Addr paddr() const 1427404SAli.Saidi@ARM.com { 1437406SAli.Saidi@ARM.com if (supersection()) 1447404SAli.Saidi@ARM.com panic("Super sections not implemented\n"); 1457404SAli.Saidi@ARM.com return mbits(data, 31, 20); 1467436Sdam.sunwoo@arm.com } 1477436Sdam.sunwoo@arm.com /** Return the physcal address of the entry, bits in position*/ 1487436Sdam.sunwoo@arm.com Addr paddr(Addr va) const 1497436Sdam.sunwoo@arm.com { 1507436Sdam.sunwoo@arm.com if (supersection()) 1517436Sdam.sunwoo@arm.com panic("Super sections not implemented\n"); 1527436Sdam.sunwoo@arm.com return mbits(data, 31, 20) | mbits(va, 19, 0); 1537436Sdam.sunwoo@arm.com } 1547436Sdam.sunwoo@arm.com 1557436Sdam.sunwoo@arm.com 1567436Sdam.sunwoo@arm.com /** Return the physical frame, bits shifted right */ 1577436Sdam.sunwoo@arm.com Addr pfn() const 1587436Sdam.sunwoo@arm.com { 1597436Sdam.sunwoo@arm.com if (supersection()) 1607436Sdam.sunwoo@arm.com panic("Super sections not implemented\n"); 1617436Sdam.sunwoo@arm.com return bits(data, 31, 20); 1627436Sdam.sunwoo@arm.com } 1637436Sdam.sunwoo@arm.com 1647436Sdam.sunwoo@arm.com /** Is the translation global (no asid used)? */ 1657436Sdam.sunwoo@arm.com bool global(WalkerState *currState) const 1667404SAli.Saidi@ARM.com { 1677404SAli.Saidi@ARM.com return !bits(data, 17); 1687404SAli.Saidi@ARM.com } 1697404SAli.Saidi@ARM.com 1707404SAli.Saidi@ARM.com /** Is the translation not allow execution? */ 1717436Sdam.sunwoo@arm.com bool xn() const 1727404SAli.Saidi@ARM.com { 1737404SAli.Saidi@ARM.com return bits(data, 4); 1747436Sdam.sunwoo@arm.com } 1757436Sdam.sunwoo@arm.com 1767436Sdam.sunwoo@arm.com /** Three bit access protection flags */ 1777436Sdam.sunwoo@arm.com uint8_t ap() const 1787404SAli.Saidi@ARM.com { 1797404SAli.Saidi@ARM.com return (bits(data, 15) << 2) | bits(data, 11, 10); 1807404SAli.Saidi@ARM.com } 1817404SAli.Saidi@ARM.com 1827404SAli.Saidi@ARM.com /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ 1837404SAli.Saidi@ARM.com TlbEntry::DomainType domain() const 1847404SAli.Saidi@ARM.com { 1857404SAli.Saidi@ARM.com return static_cast<TlbEntry::DomainType>(bits(data, 8, 5)); 1867404SAli.Saidi@ARM.com } 1877404SAli.Saidi@ARM.com 1887404SAli.Saidi@ARM.com /** Address of L2 descriptor if it exists */ 1897404SAli.Saidi@ARM.com Addr l2Addr() const 1907404SAli.Saidi@ARM.com { 1917404SAli.Saidi@ARM.com return mbits(data, 31, 10); 1927404SAli.Saidi@ARM.com } 1937404SAli.Saidi@ARM.com 1947404SAli.Saidi@ARM.com /** Memory region attributes: ARM DDI 0406B: B3-32. 1957404SAli.Saidi@ARM.com * These bits are largly ignored by M5 and only used to 1967404SAli.Saidi@ARM.com * provide the illusion that the memory system cares about 1977404SAli.Saidi@ARM.com * anything but cachable vs. uncachable. 1987404SAli.Saidi@ARM.com */ 1997404SAli.Saidi@ARM.com uint8_t texcb() const 2007404SAli.Saidi@ARM.com { 2017404SAli.Saidi@ARM.com return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2; 2027404SAli.Saidi@ARM.com } 2037404SAli.Saidi@ARM.com 2047404SAli.Saidi@ARM.com /** If the section is shareable. See texcb() comment. */ 2057404SAli.Saidi@ARM.com bool shareable() const 2067404SAli.Saidi@ARM.com { 2077404SAli.Saidi@ARM.com return bits(data, 16); 2087404SAli.Saidi@ARM.com } 2097404SAli.Saidi@ARM.com 2107404SAli.Saidi@ARM.com /** Set access flag that this entry has been touched. Mark 2117404SAli.Saidi@ARM.com * the entry as requiring a writeback, in the future. 2127406SAli.Saidi@ARM.com */ 2137406SAli.Saidi@ARM.com void setAp0() 2147404SAli.Saidi@ARM.com { 2157404SAli.Saidi@ARM.com data |= 1 << 10; 2167404SAli.Saidi@ARM.com _dirty = true; 2177404SAli.Saidi@ARM.com } 2187404SAli.Saidi@ARM.com 2197404SAli.Saidi@ARM.com /** This entry needs to be written back to memory */ 2207404SAli.Saidi@ARM.com bool dirty() const 2217404SAli.Saidi@ARM.com { 2227436Sdam.sunwoo@arm.com return _dirty; 2237436Sdam.sunwoo@arm.com } 2247436Sdam.sunwoo@arm.com 2257436Sdam.sunwoo@arm.com /** 2267436Sdam.sunwoo@arm.com * Returns true if this entry targets the secure physical address 2277436Sdam.sunwoo@arm.com * map. 2287436Sdam.sunwoo@arm.com */ 2297436Sdam.sunwoo@arm.com bool secure(bool have_security, WalkerState *currState) const 2307436Sdam.sunwoo@arm.com { 2317436Sdam.sunwoo@arm.com if (have_security) { 2327436Sdam.sunwoo@arm.com if (type() == PageTable) 2337436Sdam.sunwoo@arm.com return !bits(data, 3); 2347436Sdam.sunwoo@arm.com else 2357436Sdam.sunwoo@arm.com return !bits(data, 19); 2367436Sdam.sunwoo@arm.com } 2377436Sdam.sunwoo@arm.com return false; 2387436Sdam.sunwoo@arm.com } 2397436Sdam.sunwoo@arm.com }; 2407436Sdam.sunwoo@arm.com 2417436Sdam.sunwoo@arm.com /** Level 2 page table descriptor */ 2427436Sdam.sunwoo@arm.com class L2Descriptor : public DescriptorBase { 2437404SAli.Saidi@ARM.com public: 2447404SAli.Saidi@ARM.com /** The raw bits of the entry. */ 2457439Sdam.sunwoo@arm.com uint32_t data; 2467439Sdam.sunwoo@arm.com L1Descriptor *l1Parent; 2477439Sdam.sunwoo@arm.com 2487439Sdam.sunwoo@arm.com /** This entry has been modified (access flag set) and needs to be 2497439Sdam.sunwoo@arm.com * written back to memory */ 2507439Sdam.sunwoo@arm.com bool _dirty; 2517439Sdam.sunwoo@arm.com 2527439Sdam.sunwoo@arm.com /** Default ctor */ 2537439Sdam.sunwoo@arm.com L2Descriptor() : data(0), l1Parent(nullptr), _dirty(false) 2547439Sdam.sunwoo@arm.com { 2557439Sdam.sunwoo@arm.com lookupLevel = L2; 2567439Sdam.sunwoo@arm.com } 2577439Sdam.sunwoo@arm.com 2587439Sdam.sunwoo@arm.com L2Descriptor(L1Descriptor &parent) : data(0), l1Parent(&parent), 2597439Sdam.sunwoo@arm.com _dirty(false) 2607439Sdam.sunwoo@arm.com { 2617439Sdam.sunwoo@arm.com lookupLevel = L2; 2627439Sdam.sunwoo@arm.com } 2637439Sdam.sunwoo@arm.com 2647439Sdam.sunwoo@arm.com virtual uint64_t getRawData() const 2657439Sdam.sunwoo@arm.com { 2667439Sdam.sunwoo@arm.com return (data); 2677439Sdam.sunwoo@arm.com } 2687439Sdam.sunwoo@arm.com 2697439Sdam.sunwoo@arm.com virtual std::string dbgHeader() const 2707439Sdam.sunwoo@arm.com { 2717439Sdam.sunwoo@arm.com return "Inserting L2 Descriptor into TLB\n"; 2727439Sdam.sunwoo@arm.com } 2737439Sdam.sunwoo@arm.com 2747439Sdam.sunwoo@arm.com virtual TlbEntry::DomainType domain() const 2757439Sdam.sunwoo@arm.com { 2767439Sdam.sunwoo@arm.com return l1Parent->domain(); 2777439Sdam.sunwoo@arm.com } 2787439Sdam.sunwoo@arm.com 2797439Sdam.sunwoo@arm.com bool secure(bool have_security, WalkerState *currState) const 2807439Sdam.sunwoo@arm.com { 2817439Sdam.sunwoo@arm.com return l1Parent->secure(have_security, currState); 2827439Sdam.sunwoo@arm.com } 2837439Sdam.sunwoo@arm.com 2847439Sdam.sunwoo@arm.com virtual uint8_t offsetBits() const 2857439Sdam.sunwoo@arm.com { 2867439Sdam.sunwoo@arm.com return large() ? 16 : 12; 2877439Sdam.sunwoo@arm.com } 2887439Sdam.sunwoo@arm.com 2897439Sdam.sunwoo@arm.com /** Is the entry invalid */ 2907439Sdam.sunwoo@arm.com bool invalid() const 2917439Sdam.sunwoo@arm.com { 2927439Sdam.sunwoo@arm.com return bits(data, 1, 0) == 0; 2937439Sdam.sunwoo@arm.com } 2947439Sdam.sunwoo@arm.com 2957439Sdam.sunwoo@arm.com /** What is the size of the mapping? */ 2967439Sdam.sunwoo@arm.com bool large() const 2977439Sdam.sunwoo@arm.com { 2987439Sdam.sunwoo@arm.com return bits(data, 1) == 0; 2997439Sdam.sunwoo@arm.com } 3007439Sdam.sunwoo@arm.com 3017439Sdam.sunwoo@arm.com /** Is execution allowed on this mapping? */ 3027439Sdam.sunwoo@arm.com bool xn() const 3037439Sdam.sunwoo@arm.com { 3047439Sdam.sunwoo@arm.com return large() ? bits(data, 15) : bits(data, 0); 3057439Sdam.sunwoo@arm.com } 3067404SAli.Saidi@ARM.com 3077404SAli.Saidi@ARM.com /** Is the translation global (no asid used)? */ 3087404SAli.Saidi@ARM.com bool global(WalkerState *currState) const 3097404SAli.Saidi@ARM.com { 3107404SAli.Saidi@ARM.com return !bits(data, 11); 3117404SAli.Saidi@ARM.com } 3127404SAli.Saidi@ARM.com 3137404SAli.Saidi@ARM.com /** Three bit access protection flags */ 3147404SAli.Saidi@ARM.com uint8_t ap() const 3157439Sdam.sunwoo@arm.com { 3167437Sdam.sunwoo@arm.com return bits(data, 5, 4) | (bits(data, 9) << 2); 3177404SAli.Saidi@ARM.com } 3187404SAli.Saidi@ARM.com 3197404SAli.Saidi@ARM.com /** Memory region attributes: ARM DDI 0406B: B3-32 */ 3207404SAli.Saidi@ARM.com uint8_t texcb() const 3217404SAli.Saidi@ARM.com { 3227404SAli.Saidi@ARM.com return large() ? 3237404SAli.Saidi@ARM.com (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) : 3247404SAli.Saidi@ARM.com (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2)); 3257404SAli.Saidi@ARM.com } 3267404SAli.Saidi@ARM.com 3277404SAli.Saidi@ARM.com /** Return the physical frame, bits shifted right */ 3287404SAli.Saidi@ARM.com Addr pfn() const 3297404SAli.Saidi@ARM.com { 3307404SAli.Saidi@ARM.com return large() ? bits(data, 31, 16) : bits(data, 31, 12); 3317404SAli.Saidi@ARM.com } 3327404SAli.Saidi@ARM.com 3337404SAli.Saidi@ARM.com /** Return complete physical address given a VA */ 3347404SAli.Saidi@ARM.com Addr paddr(Addr va) const 3357439Sdam.sunwoo@arm.com { 3367439Sdam.sunwoo@arm.com if (large()) 3377404SAli.Saidi@ARM.com return mbits(data, 31, 16) | mbits(va, 15, 0); 3387404SAli.Saidi@ARM.com else 3397404SAli.Saidi@ARM.com return mbits(data, 31, 12) | mbits(va, 11, 0); 3407404SAli.Saidi@ARM.com } 3417437Sdam.sunwoo@arm.com 3427437Sdam.sunwoo@arm.com /** If the section is shareable. See texcb() comment. */ 3437404SAli.Saidi@ARM.com bool shareable() const 3447404SAli.Saidi@ARM.com { 3457437Sdam.sunwoo@arm.com return bits(data, 10); 3467437Sdam.sunwoo@arm.com } 3477404SAli.Saidi@ARM.com 3487404SAli.Saidi@ARM.com /** Set access flag that this entry has been touched. Mark 3497404SAli.Saidi@ARM.com * the entry as requiring a writeback, in the future. 3507404SAli.Saidi@ARM.com */ 3517404SAli.Saidi@ARM.com void setAp0() 3527404SAli.Saidi@ARM.com { 3537404SAli.Saidi@ARM.com data |= 1 << 4; 3547404SAli.Saidi@ARM.com _dirty = true; 3557404SAli.Saidi@ARM.com } 356 357 /** This entry needs to be written back to memory */ 358 bool dirty() const 359 { 360 return _dirty; 361 } 362 363 }; 364 365 // Granule sizes for AArch64 long descriptors 366 enum GrainSize { 367 Grain4KB = 12, 368 Grain16KB = 14, 369 Grain64KB = 16, 370 ReservedGrain = 0 371 }; 372 373 /** Long-descriptor format (LPAE) */ 374 class LongDescriptor : public DescriptorBase { 375 public: 376 /** Descriptor type */ 377 enum EntryType { 378 Invalid, 379 Table, 380 Block, 381 Page 382 }; 383 384 /** The raw bits of the entry */ 385 uint64_t data; 386 387 /** This entry has been modified (access flag set) and needs to be 388 * written back to memory */ 389 bool _dirty; 390 391 virtual uint64_t getRawData() const 392 { 393 return (data); 394 } 395 396 virtual std::string dbgHeader() const 397 { 398 if (type() == LongDescriptor::Page) { 399 assert(lookupLevel == L3); 400 return "Inserting Page descriptor into TLB\n"; 401 } else { 402 assert(lookupLevel < L3); 403 return "Inserting Block descriptor into TLB\n"; 404 } 405 } 406 407 /** 408 * Returns true if this entry targets the secure physical address 409 * map. 410 */ 411 bool secure(bool have_security, WalkerState *currState) const 412 { 413 assert(type() == Block || type() == Page); 414 return have_security && (currState->secureLookup && !bits(data, 5)); 415 } 416 417 /** True if the current lookup is performed in AArch64 state */ 418 bool aarch64; 419 420 /** Width of the granule size in bits */ 421 GrainSize grainSize; 422 423 /** Return the descriptor type */ 424 EntryType type() const 425 { 426 switch (bits(data, 1, 0)) { 427 case 0x1: 428 // In AArch64 blocks are not allowed at L0 for the 4 KB granule 429 // and at L1 for 16/64 KB granules 430 if (grainSize > Grain4KB) 431 return lookupLevel == L2 ? Block : Invalid; 432 return lookupLevel == L0 || lookupLevel == L3 ? Invalid : Block; 433 case 0x3: 434 return lookupLevel == L3 ? Page : Table; 435 default: 436 return Invalid; 437 } 438 } 439 440 /** Return the bit width of the page/block offset */ 441 uint8_t offsetBits() const 442 { 443 if (type() == Block) { 444 switch (grainSize) { 445 case Grain4KB: 446 return lookupLevel == L1 ? 30 /* 1 GB */ 447 : 21 /* 2 MB */; 448 case Grain16KB: 449 return 25 /* 32 MB */; 450 case Grain64KB: 451 return 29 /* 512 MB */; 452 default: 453 panic("Invalid AArch64 VM granule size\n"); 454 } 455 } else if (type() == Page) { 456 switch (grainSize) { 457 case Grain4KB: 458 case Grain16KB: 459 case Grain64KB: 460 return grainSize; /* enum -> uint okay */ 461 default: 462 panic("Invalid AArch64 VM granule size\n"); 463 } 464 } else { 465 panic("AArch64 page table entry must be block or page\n"); 466 } 467 } 468 469 /** Return the physical frame, bits shifted right */ 470 Addr pfn() const 471 { 472 if (aarch64) 473 return bits(data, 47, offsetBits()); 474 return bits(data, 39, offsetBits()); 475 } 476 477 /** Return the complete physical address given a VA */ 478 Addr paddr(Addr va) const 479 { 480 int n = offsetBits(); 481 if (aarch64) 482 return mbits(data, 47, n) | mbits(va, n - 1, 0); 483 return mbits(data, 39, n) | mbits(va, n - 1, 0); 484 } 485 486 /** Return the physical address of the entry */ 487 Addr paddr() const 488 { 489 if (aarch64) 490 return mbits(data, 47, offsetBits()); 491 return mbits(data, 39, offsetBits()); 492 } 493 494 /** Return the address of the next page table */ 495 Addr nextTableAddr() const 496 { 497 assert(type() == Table); 498 if (aarch64) 499 return mbits(data, 47, grainSize); 500 else 501 return mbits(data, 39, 12); 502 } 503 504 /** Return the address of the next descriptor */ 505 Addr nextDescAddr(Addr va) const 506 { 507 assert(type() == Table); 508 Addr pa = 0; 509 if (aarch64) { 510 int stride = grainSize - 3; 511 int va_lo = stride * (3 - (lookupLevel + 1)) + grainSize; 512 int va_hi = va_lo + stride - 1; 513 pa = nextTableAddr() | (bits(va, va_hi, va_lo) << 3); 514 } else { 515 if (lookupLevel == L1) 516 pa = nextTableAddr() | (bits(va, 29, 21) << 3); 517 else // lookupLevel == L2 518 pa = nextTableAddr() | (bits(va, 20, 12) << 3); 519 } 520 return pa; 521 } 522 523 /** Is execution allowed on this mapping? */ 524 bool xn() const 525 { 526 assert(type() == Block || type() == Page); 527 return bits(data, 54); 528 } 529 530 /** Is privileged execution allowed on this mapping? (LPAE only) */ 531 bool pxn() const 532 { 533 assert(type() == Block || type() == Page); 534 return bits(data, 53); 535 } 536 537 /** Contiguous hint bit. */ 538 bool contiguousHint() const 539 { 540 assert(type() == Block || type() == Page); 541 return bits(data, 52); 542 } 543 544 /** Is the translation global (no asid used)? */ 545 bool global(WalkerState *currState) const 546 { 547 assert(currState && (type() == Block || type() == Page)); 548 if (!currState->aarch64 && (currState->isSecure && 549 !currState->secureLookup)) { 550 return false; // ARM ARM issue C B3.6.3 551 } else if (currState->aarch64) { 552 if (currState->el == EL2 || currState->el == EL3) { 553 return true; // By default translations are treated as global 554 // in AArch64 EL2 and EL3 555 } else if (currState->isSecure && !currState->secureLookup) { 556 return false; 557 } 558 } 559 return !bits(data, 11); 560 } 561 562 /** Returns true if the access flag (AF) is set. */ 563 bool af() const 564 { 565 assert(type() == Block || type() == Page); 566 return bits(data, 10); 567 } 568 569 /** 2-bit shareability field */ 570 uint8_t sh() const 571 { 572 assert(type() == Block || type() == Page); 573 return bits(data, 9, 8); 574 } 575 576 /** 2-bit access protection flags */ 577 uint8_t ap() const 578 { 579 assert(type() == Block || type() == Page); 580 // Long descriptors only support the AP[2:1] scheme 581 return bits(data, 7, 6); 582 } 583 584 /** Read/write access protection flag */ 585 bool rw() const 586 { 587 assert(type() == Block || type() == Page); 588 return !bits(data, 7); 589 } 590 591 /** User/privileged level access protection flag */ 592 bool user() const 593 { 594 assert(type() == Block || type() == Page); 595 return bits(data, 6); 596 } 597 598 /** Return the AP bits as compatible with the AP[2:0] format. Utility 599 * function used to simplify the code in the TLB for performing 600 * permission checks. */ 601 static uint8_t ap(bool rw, bool user) 602 { 603 return ((!rw) << 2) | (user << 1); 604 } 605 606 TlbEntry::DomainType domain() const 607 { 608 // Long-desc. format only supports Client domain 609 assert(type() == Block || type() == Page); 610 return TlbEntry::DomainType::Client; 611 } 612 613 /** Attribute index */ 614 uint8_t attrIndx() const 615 { 616 assert(type() == Block || type() == Page); 617 return bits(data, 4, 2); 618 } 619 620 /** Memory attributes, only used by stage 2 translations */ 621 uint8_t memAttr() const 622 { 623 assert(type() == Block || type() == Page); 624 return bits(data, 5, 2); 625 } 626 627 /** Set access flag that this entry has been touched. Mark the entry as 628 * requiring a writeback, in the future. */ 629 void setAf() 630 { 631 data |= 1 << 10; 632 _dirty = true; 633 } 634 635 /** This entry needs to be written back to memory */ 636 bool dirty() const 637 { 638 return _dirty; 639 } 640 641 /** Whether the subsequent levels of lookup are secure */ 642 bool secureTable() const 643 { 644 assert(type() == Table); 645 return !bits(data, 63); 646 } 647 648 /** Two bit access protection flags for subsequent levels of lookup */ 649 uint8_t apTable() const 650 { 651 assert(type() == Table); 652 return bits(data, 62, 61); 653 } 654 655 /** R/W protection flag for subsequent levels of lookup */ 656 uint8_t rwTable() const 657 { 658 assert(type() == Table); 659 return !bits(data, 62); 660 } 661 662 /** User/privileged mode protection flag for subsequent levels of 663 * lookup */ 664 uint8_t userTable() const 665 { 666 assert(type() == Table); 667 return !bits(data, 61); 668 } 669 670 /** Is execution allowed on subsequent lookup levels? */ 671 bool xnTable() const 672 { 673 assert(type() == Table); 674 return bits(data, 60); 675 } 676 677 /** Is privileged execution allowed on subsequent lookup levels? */ 678 bool pxnTable() const 679 { 680 assert(type() == Table); 681 return bits(data, 59); 682 } 683 }; 684 685 class WalkerState 686 { 687 public: 688 /** Thread context that we're doing the walk for */ 689 ThreadContext *tc; 690 691 /** If the access is performed in AArch64 state */ 692 bool aarch64; 693 694 /** Current exception level */ 695 ExceptionLevel el; 696 697 /** Current physical address range in bits */ 698 int physAddrRange; 699 700 /** Request that is currently being serviced */ 701 RequestPtr req; 702 703 /** ASID that we're servicing the request under */ 704 uint16_t asid; 705 uint8_t vmid; 706 bool isHyp; 707 708 /** Translation state for delayed requests */ 709 TLB::Translation *transState; 710 711 /** The fault that we are going to return */ 712 Fault fault; 713 714 /** The virtual address that is being translated with tagging removed.*/ 715 Addr vaddr; 716 717 /** The virtual address that is being translated */ 718 Addr vaddr_tainted; 719 720 /** Cached copy of the sctlr as it existed when translation began */ 721 SCTLR sctlr; 722 723 /** Cached copy of the scr as it existed when translation began */ 724 SCR scr; 725 726 /** Cached copy of the cpsr as it existed when translation began */ 727 CPSR cpsr; 728 729 /** Cached copy of ttbcr/tcr as it existed when translation began */ 730 union { 731 TTBCR ttbcr; // AArch32 translations 732 TCR tcr; // AArch64 translations 733 }; 734 735 /** Cached copy of the htcr as it existed when translation began. */ 736 HTCR htcr; 737 738 /** Cached copy of the htcr as it existed when translation began. */ 739 HCR hcr; 740 741 /** Cached copy of the vtcr as it existed when translation began. */ 742 VTCR_t vtcr; 743 744 /** If the access is a write */ 745 bool isWrite; 746 747 /** If the access is a fetch (for execution, and no-exec) must be checked?*/ 748 bool isFetch; 749 750 /** If the access comes from the secure state. */ 751 bool isSecure; 752 753 /** Helper variables used to implement hierarchical access permissions 754 * when the long-desc. format is used (LPAE only) */ 755 bool secureLookup; 756 bool rwTable; 757 bool userTable; 758 bool xnTable; 759 bool pxnTable; 760 761 /** Flag indicating if a second stage of lookup is required */ 762 bool stage2Req; 763 764 /** Indicates whether the translation has been passed onto the second 765 * stage mmu, and no more work is required from the first stage. 766 */ 767 bool doingStage2; 768 769 /** A pointer to the stage 2 translation that's in progress */ 770 TLB::Translation *stage2Tran; 771 772 /** If the mode is timing or atomic */ 773 bool timing; 774 775 /** If the atomic mode should be functional */ 776 bool functional; 777 778 /** Save mode for use in delayed response */ 779 BaseTLB::Mode mode; 780 781 /** The translation type that has been requested */ 782 TLB::ArmTranslationType tranType; 783 784 /** Short-format descriptors */ 785 L1Descriptor l1Desc; 786 L2Descriptor l2Desc; 787 788 /** Long-format descriptor (LPAE and AArch64) */ 789 LongDescriptor longDesc; 790 791 /** Whether the response is delayed in timing mode due to additional 792 * lookups */ 793 bool delayed; 794 795 TableWalker *tableWalker; 796 797 /** Timestamp for calculating elapsed time in service (for stats) */ 798 Tick startTime; 799 800 /** Page entries walked during service (for stats) */ 801 unsigned levels; 802 803 void doL1Descriptor(); 804 void doL2Descriptor(); 805 806 void doLongDescriptor(); 807 808 WalkerState(); 809 810 std::string name() const { return tableWalker->name(); } 811 }; 812 813 protected: 814 815 /** Queues of requests for all the different lookup levels */ 816 std::list<WalkerState *> stateQueues[MAX_LOOKUP_LEVELS]; 817 818 /** Queue of requests that have passed are waiting because the walker is 819 * currently busy. */ 820 std::list<WalkerState *> pendingQueue; 821 822 /** The MMU to forward second stage look upts to */ 823 Stage2MMU *stage2Mmu; 824 825 /** Port shared by the two table walkers. */ 826 DmaPort* port; 827 828 /** Master id assigned by the MMU. */ 829 MasterID masterId; 830 831 /** Indicates whether this table walker is part of the stage 2 mmu */ 832 const bool isStage2; 833 834 /** TLB that is initiating these table walks */ 835 TLB *tlb; 836 837 /** Cached copy of the sctlr as it existed when translation began */ 838 SCTLR sctlr; 839 840 WalkerState *currState; 841 842 /** If a timing translation is currently in progress */ 843 bool pending; 844 845 /** The number of walks belonging to squashed instructions that can be 846 * removed from the pendingQueue per cycle. */ 847 unsigned numSquashable; 848 849 /** Cached copies of system-level properties */ 850 bool haveSecurity; 851 bool _haveLPAE; 852 bool _haveVirtualization; 853 uint8_t physAddrRange; 854 bool _haveLargeAsid64; 855 856 /** Statistics */ 857 Stats::Scalar statWalks; 858 Stats::Scalar statWalksShortDescriptor; 859 Stats::Scalar statWalksLongDescriptor; 860 Stats::Vector statWalksShortTerminatedAtLevel; 861 Stats::Vector statWalksLongTerminatedAtLevel; 862 Stats::Scalar statSquashedBefore; 863 Stats::Scalar statSquashedAfter; 864 Stats::Histogram statWalkWaitTime; 865 Stats::Histogram statWalkServiceTime; 866 Stats::Histogram statPendingWalks; // essentially "L" of queueing theory 867 Stats::Vector statPageSizes; 868 Stats::Vector2d statRequestOrigin; 869 870 mutable unsigned pendingReqs; 871 mutable Tick pendingChangeTick; 872 873 static const unsigned REQUESTED = 0; 874 static const unsigned COMPLETED = 1; 875 876 public: 877 typedef ArmTableWalkerParams Params; 878 TableWalker(const Params *p); 879 virtual ~TableWalker(); 880 881 const Params * 882 params() const 883 { 884 return dynamic_cast<const Params *>(_params); 885 } 886 887 void init() override; 888 889 bool haveLPAE() const { return _haveLPAE; } 890 bool haveVirtualization() const { return _haveVirtualization; } 891 bool haveLargeAsid64() const { return _haveLargeAsid64; } 892 /** Checks if all state is cleared and if so, completes drain */ 893 void completeDrain(); 894 DrainState drain() override; 895 void drainResume() override; 896 897 BaseMasterPort& getMasterPort(const std::string &if_name, 898 PortID idx = InvalidPortID) override; 899 900 void regStats() override; 901 902 Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid, 903 bool _isHyp, TLB::Mode mode, TLB::Translation *_trans, 904 bool timing, bool functional, bool secure, 905 TLB::ArmTranslationType tranType); 906 907 void setTlb(TLB *_tlb) { tlb = _tlb; } 908 TLB* getTlb() { return tlb; } 909 void setMMU(Stage2MMU *m, MasterID master_id); 910 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 911 uint8_t texcb, bool s); 912 void memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 913 LongDescriptor &lDescriptor); 914 void memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx, 915 uint8_t sh); 916 917 static LookupLevel toLookupLevel(uint8_t lookup_level_as_int); 918 919 private: 920 921 void doL1Descriptor(); 922 void doL1DescriptorWrapper(); 923 EventWrapper<TableWalker, 924 &TableWalker::doL1DescriptorWrapper> doL1DescEvent; 925 926 void doL2Descriptor(); 927 void doL2DescriptorWrapper(); 928 EventWrapper<TableWalker, 929 &TableWalker::doL2DescriptorWrapper> doL2DescEvent; 930 931 void doLongDescriptor(); 932 933 void doL0LongDescriptorWrapper(); 934 EventWrapper<TableWalker, 935 &TableWalker::doL0LongDescriptorWrapper> doL0LongDescEvent; 936 void doL1LongDescriptorWrapper(); 937 EventWrapper<TableWalker, 938 &TableWalker::doL1LongDescriptorWrapper> doL1LongDescEvent; 939 void doL2LongDescriptorWrapper(); 940 EventWrapper<TableWalker, 941 &TableWalker::doL2LongDescriptorWrapper> doL2LongDescEvent; 942 void doL3LongDescriptorWrapper(); 943 EventWrapper<TableWalker, 944 &TableWalker::doL3LongDescriptorWrapper> doL3LongDescEvent; 945 946 void doLongDescriptorWrapper(LookupLevel curr_lookup_level); 947 948 bool fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 949 Request::Flags flags, int queueIndex, Event *event, 950 void (TableWalker::*doDescriptor)()); 951 952 void insertTableEntry(DescriptorBase &descriptor, bool longDescriptor); 953 954 Fault processWalk(); 955 Fault processWalkLPAE(); 956 static unsigned adjustTableSizeAArch64(unsigned tsz); 957 /// Returns true if the address exceeds the range permitted by the 958 /// system-wide setting or by the TCR_ELx IPS/PS setting 959 static bool checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange); 960 Fault processWalkAArch64(); 961 void processWalkWrapper(); 962 EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent; 963 964 void nextWalk(ThreadContext *tc); 965 966 void pendingChange(); 967 968 static uint8_t pageSizeNtoStatBin(uint8_t N); 969}; 970 971} // namespace ArmISA 972 973#endif //__ARCH_ARM_TABLE_WALKER_HH__ 974 975