table_walker.hh revision 10717
17404SAli.Saidi@ARM.com/* 210717Sandreas.hansson@arm.com * Copyright (c) 2010-2015 ARM Limited 37404SAli.Saidi@ARM.com * All rights reserved 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67404SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77404SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87404SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97404SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107404SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117404SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127404SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137404SAli.Saidi@ARM.com * 147404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237404SAli.Saidi@ARM.com * this software without specific prior written permission. 247404SAli.Saidi@ARM.com * 257404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367404SAli.Saidi@ARM.com * 377404SAli.Saidi@ARM.com * Authors: Ali Saidi 3810037SARM gem5 Developers * Giacomo Gabrielli 397404SAli.Saidi@ARM.com */ 407404SAli.Saidi@ARM.com 417404SAli.Saidi@ARM.com#ifndef __ARCH_ARM_TABLE_WALKER_HH__ 427404SAli.Saidi@ARM.com#define __ARCH_ARM_TABLE_WALKER_HH__ 437404SAli.Saidi@ARM.com 447578Sdam.sunwoo@arm.com#include <list> 457578Sdam.sunwoo@arm.com 467404SAli.Saidi@ARM.com#include "arch/arm/miscregs.hh" 4710037SARM gem5 Developers#include "arch/arm/system.hh" 487404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 499016Sandreas.hansson@arm.com#include "dev/dma_device.hh" 507404SAli.Saidi@ARM.com#include "mem/request.hh" 517404SAli.Saidi@ARM.com#include "params/ArmTableWalker.hh" 527404SAli.Saidi@ARM.com#include "sim/eventq.hh" 537404SAli.Saidi@ARM.com 547404SAli.Saidi@ARM.comclass ThreadContext; 557404SAli.Saidi@ARM.com 567404SAli.Saidi@ARM.comnamespace ArmISA { 577404SAli.Saidi@ARM.comclass Translation; 587404SAli.Saidi@ARM.comclass TLB; 5910037SARM gem5 Developersclass Stage2MMU; 607404SAli.Saidi@ARM.com 617404SAli.Saidi@ARM.comclass TableWalker : public MemObject 627404SAli.Saidi@ARM.com{ 637694SAli.Saidi@ARM.com public: 6410037SARM gem5 Developers class WalkerState; 6510037SARM gem5 Developers 6610037SARM gem5 Developers class DescriptorBase { 6710037SARM gem5 Developers public: 6810037SARM gem5 Developers /** Current lookup level for this descriptor */ 6910037SARM gem5 Developers LookupLevel lookupLevel; 7010037SARM gem5 Developers 7110037SARM gem5 Developers virtual Addr pfn() const = 0; 7210037SARM gem5 Developers virtual TlbEntry::DomainType domain() const = 0; 7310037SARM gem5 Developers virtual bool xn() const = 0; 7410037SARM gem5 Developers virtual uint8_t ap() const = 0; 7510037SARM gem5 Developers virtual bool global(WalkerState *currState) const = 0; 7610037SARM gem5 Developers virtual uint8_t offsetBits() const = 0; 7710037SARM gem5 Developers virtual bool secure(bool have_security, WalkerState *currState) const = 0; 7810037SARM gem5 Developers virtual std::string dbgHeader() const = 0; 7910037SARM gem5 Developers virtual uint64_t getRawData() const = 0; 8010037SARM gem5 Developers virtual uint8_t texcb() const 8110037SARM gem5 Developers { 8210037SARM gem5 Developers panic("texcb() not implemented for this class\n"); 8310037SARM gem5 Developers } 8410037SARM gem5 Developers virtual bool shareable() const 8510037SARM gem5 Developers { 8610037SARM gem5 Developers panic("shareable() not implemented for this class\n"); 8710037SARM gem5 Developers } 8810037SARM gem5 Developers }; 8910037SARM gem5 Developers 9010037SARM gem5 Developers class L1Descriptor : public DescriptorBase { 9110037SARM gem5 Developers public: 927404SAli.Saidi@ARM.com /** Type of page table entry ARM DDI 0406B: B3-8*/ 937404SAli.Saidi@ARM.com enum EntryType { 947404SAli.Saidi@ARM.com Ignore, 957404SAli.Saidi@ARM.com PageTable, 967404SAli.Saidi@ARM.com Section, 977404SAli.Saidi@ARM.com Reserved 987404SAli.Saidi@ARM.com }; 997404SAli.Saidi@ARM.com 1007436Sdam.sunwoo@arm.com /** The raw bits of the entry */ 1017404SAli.Saidi@ARM.com uint32_t data; 1027404SAli.Saidi@ARM.com 1037436Sdam.sunwoo@arm.com /** This entry has been modified (access flag set) and needs to be 1047436Sdam.sunwoo@arm.com * written back to memory */ 1057436Sdam.sunwoo@arm.com bool _dirty; 1067436Sdam.sunwoo@arm.com 10710037SARM gem5 Developers /** Default ctor */ 10810537Sandreas.hansson@arm.com L1Descriptor() : data(0), _dirty(false) 10910037SARM gem5 Developers { 11010037SARM gem5 Developers lookupLevel = L1; 11110037SARM gem5 Developers } 11210037SARM gem5 Developers 11310037SARM gem5 Developers virtual uint64_t getRawData() const 11410037SARM gem5 Developers { 11510037SARM gem5 Developers return (data); 11610037SARM gem5 Developers } 11710037SARM gem5 Developers 11810037SARM gem5 Developers virtual std::string dbgHeader() const 11910037SARM gem5 Developers { 12010037SARM gem5 Developers return "Inserting Section Descriptor into TLB\n"; 12110037SARM gem5 Developers } 12210037SARM gem5 Developers 12310037SARM gem5 Developers virtual uint8_t offsetBits() const 12410037SARM gem5 Developers { 12510037SARM gem5 Developers return 20; 12610037SARM gem5 Developers } 12710037SARM gem5 Developers 1287404SAli.Saidi@ARM.com EntryType type() const 1297404SAli.Saidi@ARM.com { 1307404SAli.Saidi@ARM.com return (EntryType)(data & 0x3); 1317404SAli.Saidi@ARM.com } 1327404SAli.Saidi@ARM.com 1337404SAli.Saidi@ARM.com /** Is the page a Supersection (16MB)?*/ 1347404SAli.Saidi@ARM.com bool supersection() const 1357404SAli.Saidi@ARM.com { 1367404SAli.Saidi@ARM.com return bits(data, 18); 1377404SAli.Saidi@ARM.com } 1387404SAli.Saidi@ARM.com 1397404SAli.Saidi@ARM.com /** Return the physcal address of the entry, bits in position*/ 1407404SAli.Saidi@ARM.com Addr paddr() const 1417404SAli.Saidi@ARM.com { 1427404SAli.Saidi@ARM.com if (supersection()) 1437404SAli.Saidi@ARM.com panic("Super sections not implemented\n"); 1447946SGiacomo.Gabrielli@arm.com return mbits(data, 31, 20); 1457404SAli.Saidi@ARM.com } 1467694SAli.Saidi@ARM.com /** Return the physcal address of the entry, bits in position*/ 1477694SAli.Saidi@ARM.com Addr paddr(Addr va) const 1487694SAli.Saidi@ARM.com { 1497694SAli.Saidi@ARM.com if (supersection()) 1507694SAli.Saidi@ARM.com panic("Super sections not implemented\n"); 1517946SGiacomo.Gabrielli@arm.com return mbits(data, 31, 20) | mbits(va, 19, 0); 1527694SAli.Saidi@ARM.com } 1537694SAli.Saidi@ARM.com 1547404SAli.Saidi@ARM.com 1557404SAli.Saidi@ARM.com /** Return the physical frame, bits shifted right */ 1567404SAli.Saidi@ARM.com Addr pfn() const 1577404SAli.Saidi@ARM.com { 1587404SAli.Saidi@ARM.com if (supersection()) 1597404SAli.Saidi@ARM.com panic("Super sections not implemented\n"); 1607946SGiacomo.Gabrielli@arm.com return bits(data, 31, 20); 1617404SAli.Saidi@ARM.com } 1627404SAli.Saidi@ARM.com 1637404SAli.Saidi@ARM.com /** Is the translation global (no asid used)? */ 16410037SARM gem5 Developers bool global(WalkerState *currState) const 1657404SAli.Saidi@ARM.com { 16610037SARM gem5 Developers return !bits(data, 17); 1677404SAli.Saidi@ARM.com } 1687404SAli.Saidi@ARM.com 1697404SAli.Saidi@ARM.com /** Is the translation not allow execution? */ 1707404SAli.Saidi@ARM.com bool xn() const 1717404SAli.Saidi@ARM.com { 1727608SGene.Wu@arm.com return bits(data, 4); 1737404SAli.Saidi@ARM.com } 1747404SAli.Saidi@ARM.com 1757404SAli.Saidi@ARM.com /** Three bit access protection flags */ 1767404SAli.Saidi@ARM.com uint8_t ap() const 1777404SAli.Saidi@ARM.com { 1787946SGiacomo.Gabrielli@arm.com return (bits(data, 15) << 2) | bits(data, 11, 10); 1797404SAli.Saidi@ARM.com } 1807404SAli.Saidi@ARM.com 1817404SAli.Saidi@ARM.com /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ 18210037SARM gem5 Developers TlbEntry::DomainType domain() const 1837404SAli.Saidi@ARM.com { 18410037SARM gem5 Developers return static_cast<TlbEntry::DomainType>(bits(data, 8, 5)); 1857404SAli.Saidi@ARM.com } 1867404SAli.Saidi@ARM.com 1877404SAli.Saidi@ARM.com /** Address of L2 descriptor if it exists */ 1887404SAli.Saidi@ARM.com Addr l2Addr() const 1897404SAli.Saidi@ARM.com { 1907946SGiacomo.Gabrielli@arm.com return mbits(data, 31, 10); 1917404SAli.Saidi@ARM.com } 1927404SAli.Saidi@ARM.com 1937436Sdam.sunwoo@arm.com /** Memory region attributes: ARM DDI 0406B: B3-32. 1947436Sdam.sunwoo@arm.com * These bits are largly ignored by M5 and only used to 1957436Sdam.sunwoo@arm.com * provide the illusion that the memory system cares about 1967436Sdam.sunwoo@arm.com * anything but cachable vs. uncachable. 1977436Sdam.sunwoo@arm.com */ 1987404SAli.Saidi@ARM.com uint8_t texcb() const 1997404SAli.Saidi@ARM.com { 2007946SGiacomo.Gabrielli@arm.com return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2; 2017404SAli.Saidi@ARM.com } 2027404SAli.Saidi@ARM.com 2037436Sdam.sunwoo@arm.com /** If the section is shareable. See texcb() comment. */ 2047436Sdam.sunwoo@arm.com bool shareable() const 2057436Sdam.sunwoo@arm.com { 2067436Sdam.sunwoo@arm.com return bits(data, 16); 2077436Sdam.sunwoo@arm.com } 2087436Sdam.sunwoo@arm.com 2097436Sdam.sunwoo@arm.com /** Set access flag that this entry has been touched. Mark 2107436Sdam.sunwoo@arm.com * the entry as requiring a writeback, in the future. 2117436Sdam.sunwoo@arm.com */ 2127436Sdam.sunwoo@arm.com void setAp0() 2137436Sdam.sunwoo@arm.com { 2147436Sdam.sunwoo@arm.com data |= 1 << 10; 2157436Sdam.sunwoo@arm.com _dirty = true; 2167436Sdam.sunwoo@arm.com } 2177436Sdam.sunwoo@arm.com 2187436Sdam.sunwoo@arm.com /** This entry needs to be written back to memory */ 2197436Sdam.sunwoo@arm.com bool dirty() const 2207436Sdam.sunwoo@arm.com { 2217436Sdam.sunwoo@arm.com return _dirty; 2227436Sdam.sunwoo@arm.com } 22310037SARM gem5 Developers 22410037SARM gem5 Developers /** 22510037SARM gem5 Developers * Returns true if this entry targets the secure physical address 22610037SARM gem5 Developers * map. 22710037SARM gem5 Developers */ 22810037SARM gem5 Developers bool secure(bool have_security, WalkerState *currState) const 22910037SARM gem5 Developers { 23010037SARM gem5 Developers if (have_security) { 23110037SARM gem5 Developers if (type() == PageTable) 23210037SARM gem5 Developers return !bits(data, 3); 23310037SARM gem5 Developers else 23410037SARM gem5 Developers return !bits(data, 19); 23510037SARM gem5 Developers } 23610037SARM gem5 Developers return false; 23710037SARM gem5 Developers } 2387404SAli.Saidi@ARM.com }; 2397404SAli.Saidi@ARM.com 2407404SAli.Saidi@ARM.com /** Level 2 page table descriptor */ 24110037SARM gem5 Developers class L2Descriptor : public DescriptorBase { 24210037SARM gem5 Developers public: 2437436Sdam.sunwoo@arm.com /** The raw bits of the entry. */ 24410037SARM gem5 Developers uint32_t data; 24510037SARM gem5 Developers L1Descriptor *l1Parent; 2467404SAli.Saidi@ARM.com 2477436Sdam.sunwoo@arm.com /** This entry has been modified (access flag set) and needs to be 2487436Sdam.sunwoo@arm.com * written back to memory */ 2497436Sdam.sunwoo@arm.com bool _dirty; 2507436Sdam.sunwoo@arm.com 25110037SARM gem5 Developers /** Default ctor */ 25210537Sandreas.hansson@arm.com L2Descriptor() : data(0), l1Parent(nullptr), _dirty(false) 25310037SARM gem5 Developers { 25410037SARM gem5 Developers lookupLevel = L2; 25510037SARM gem5 Developers } 25610037SARM gem5 Developers 25710537Sandreas.hansson@arm.com L2Descriptor(L1Descriptor &parent) : data(0), l1Parent(&parent), 25810537Sandreas.hansson@arm.com _dirty(false) 25910037SARM gem5 Developers { 26010037SARM gem5 Developers lookupLevel = L2; 26110037SARM gem5 Developers } 26210037SARM gem5 Developers 26310037SARM gem5 Developers virtual uint64_t getRawData() const 26410037SARM gem5 Developers { 26510037SARM gem5 Developers return (data); 26610037SARM gem5 Developers } 26710037SARM gem5 Developers 26810037SARM gem5 Developers virtual std::string dbgHeader() const 26910037SARM gem5 Developers { 27010037SARM gem5 Developers return "Inserting L2 Descriptor into TLB\n"; 27110037SARM gem5 Developers } 27210037SARM gem5 Developers 27310037SARM gem5 Developers virtual TlbEntry::DomainType domain() const 27410037SARM gem5 Developers { 27510037SARM gem5 Developers return l1Parent->domain(); 27610037SARM gem5 Developers } 27710037SARM gem5 Developers 27810037SARM gem5 Developers bool secure(bool have_security, WalkerState *currState) const 27910037SARM gem5 Developers { 28010037SARM gem5 Developers return l1Parent->secure(have_security, currState); 28110037SARM gem5 Developers } 28210037SARM gem5 Developers 28310037SARM gem5 Developers virtual uint8_t offsetBits() const 28410037SARM gem5 Developers { 28510037SARM gem5 Developers return large() ? 16 : 12; 28610037SARM gem5 Developers } 28710037SARM gem5 Developers 2887404SAli.Saidi@ARM.com /** Is the entry invalid */ 2897404SAli.Saidi@ARM.com bool invalid() const 2907404SAli.Saidi@ARM.com { 2917946SGiacomo.Gabrielli@arm.com return bits(data, 1, 0) == 0; 2927404SAli.Saidi@ARM.com } 2937404SAli.Saidi@ARM.com 2947404SAli.Saidi@ARM.com /** What is the size of the mapping? */ 2957404SAli.Saidi@ARM.com bool large() const 2967404SAli.Saidi@ARM.com { 2977404SAli.Saidi@ARM.com return bits(data, 1) == 0; 2987404SAli.Saidi@ARM.com } 2997404SAli.Saidi@ARM.com 3007404SAli.Saidi@ARM.com /** Is execution allowed on this mapping? */ 3017404SAli.Saidi@ARM.com bool xn() const 3027404SAli.Saidi@ARM.com { 3037404SAli.Saidi@ARM.com return large() ? bits(data, 15) : bits(data, 0); 3047404SAli.Saidi@ARM.com } 3057404SAli.Saidi@ARM.com 3067404SAli.Saidi@ARM.com /** Is the translation global (no asid used)? */ 30710037SARM gem5 Developers bool global(WalkerState *currState) const 3087404SAli.Saidi@ARM.com { 3097404SAli.Saidi@ARM.com return !bits(data, 11); 3107404SAli.Saidi@ARM.com } 3117404SAli.Saidi@ARM.com 3127404SAli.Saidi@ARM.com /** Three bit access protection flags */ 3137404SAli.Saidi@ARM.com uint8_t ap() const 3147404SAli.Saidi@ARM.com { 3157404SAli.Saidi@ARM.com return bits(data, 5, 4) | (bits(data, 9) << 2); 3167404SAli.Saidi@ARM.com } 3177404SAli.Saidi@ARM.com 3187404SAli.Saidi@ARM.com /** Memory region attributes: ARM DDI 0406B: B3-32 */ 3197404SAli.Saidi@ARM.com uint8_t texcb() const 3207404SAli.Saidi@ARM.com { 3217404SAli.Saidi@ARM.com return large() ? 3227946SGiacomo.Gabrielli@arm.com (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) : 3237946SGiacomo.Gabrielli@arm.com (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2)); 3247404SAli.Saidi@ARM.com } 3257404SAli.Saidi@ARM.com 3267404SAli.Saidi@ARM.com /** Return the physical frame, bits shifted right */ 3277404SAli.Saidi@ARM.com Addr pfn() const 3287404SAli.Saidi@ARM.com { 3297404SAli.Saidi@ARM.com return large() ? bits(data, 31, 16) : bits(data, 31, 12); 3307404SAli.Saidi@ARM.com } 3317404SAli.Saidi@ARM.com 3327694SAli.Saidi@ARM.com /** Return complete physical address given a VA */ 3337694SAli.Saidi@ARM.com Addr paddr(Addr va) const 3347694SAli.Saidi@ARM.com { 3357694SAli.Saidi@ARM.com if (large()) 3367694SAli.Saidi@ARM.com return mbits(data, 31, 16) | mbits(va, 15, 0); 3377694SAli.Saidi@ARM.com else 3387694SAli.Saidi@ARM.com return mbits(data, 31, 12) | mbits(va, 11, 0); 3397694SAli.Saidi@ARM.com } 3407694SAli.Saidi@ARM.com 3417436Sdam.sunwoo@arm.com /** If the section is shareable. See texcb() comment. */ 3427436Sdam.sunwoo@arm.com bool shareable() const 3437436Sdam.sunwoo@arm.com { 3447436Sdam.sunwoo@arm.com return bits(data, 10); 3457436Sdam.sunwoo@arm.com } 3467436Sdam.sunwoo@arm.com 3477436Sdam.sunwoo@arm.com /** Set access flag that this entry has been touched. Mark 3487436Sdam.sunwoo@arm.com * the entry as requiring a writeback, in the future. 3497436Sdam.sunwoo@arm.com */ 3507436Sdam.sunwoo@arm.com void setAp0() 3517436Sdam.sunwoo@arm.com { 3527436Sdam.sunwoo@arm.com data |= 1 << 4; 3537436Sdam.sunwoo@arm.com _dirty = true; 3547436Sdam.sunwoo@arm.com } 3557436Sdam.sunwoo@arm.com 3567436Sdam.sunwoo@arm.com /** This entry needs to be written back to memory */ 3577436Sdam.sunwoo@arm.com bool dirty() const 3587436Sdam.sunwoo@arm.com { 3597436Sdam.sunwoo@arm.com return _dirty; 3607436Sdam.sunwoo@arm.com } 3617436Sdam.sunwoo@arm.com 3627404SAli.Saidi@ARM.com }; 3637404SAli.Saidi@ARM.com 36410324SCurtis.Dunham@arm.com // Granule sizes for AArch64 long descriptors 36510324SCurtis.Dunham@arm.com enum GrainSize { 36610324SCurtis.Dunham@arm.com Grain4KB = 12, 36710324SCurtis.Dunham@arm.com Grain16KB = 14, 36810324SCurtis.Dunham@arm.com Grain64KB = 16, 36910324SCurtis.Dunham@arm.com ReservedGrain = 0 37010324SCurtis.Dunham@arm.com }; 37110324SCurtis.Dunham@arm.com 37210037SARM gem5 Developers /** Long-descriptor format (LPAE) */ 37310037SARM gem5 Developers class LongDescriptor : public DescriptorBase { 37410037SARM gem5 Developers public: 37510037SARM gem5 Developers /** Descriptor type */ 37610037SARM gem5 Developers enum EntryType { 37710037SARM gem5 Developers Invalid, 37810037SARM gem5 Developers Table, 37910037SARM gem5 Developers Block, 38010037SARM gem5 Developers Page 38110037SARM gem5 Developers }; 38210037SARM gem5 Developers 38310037SARM gem5 Developers /** The raw bits of the entry */ 38410037SARM gem5 Developers uint64_t data; 38510037SARM gem5 Developers 38610037SARM gem5 Developers /** This entry has been modified (access flag set) and needs to be 38710037SARM gem5 Developers * written back to memory */ 38810037SARM gem5 Developers bool _dirty; 38910037SARM gem5 Developers 39010037SARM gem5 Developers virtual uint64_t getRawData() const 39110037SARM gem5 Developers { 39210037SARM gem5 Developers return (data); 39310037SARM gem5 Developers } 39410037SARM gem5 Developers 39510037SARM gem5 Developers virtual std::string dbgHeader() const 39610037SARM gem5 Developers { 39710037SARM gem5 Developers if (type() == LongDescriptor::Page) { 39810037SARM gem5 Developers assert(lookupLevel == L3); 39910037SARM gem5 Developers return "Inserting Page descriptor into TLB\n"; 40010037SARM gem5 Developers } else { 40110037SARM gem5 Developers assert(lookupLevel < L3); 40210037SARM gem5 Developers return "Inserting Block descriptor into TLB\n"; 40310037SARM gem5 Developers } 40410037SARM gem5 Developers } 40510037SARM gem5 Developers 40610037SARM gem5 Developers /** 40710037SARM gem5 Developers * Returns true if this entry targets the secure physical address 40810037SARM gem5 Developers * map. 40910037SARM gem5 Developers */ 41010037SARM gem5 Developers bool secure(bool have_security, WalkerState *currState) const 41110037SARM gem5 Developers { 41210037SARM gem5 Developers assert(type() == Block || type() == Page); 41310037SARM gem5 Developers return have_security && (currState->secureLookup && !bits(data, 5)); 41410037SARM gem5 Developers } 41510037SARM gem5 Developers 41610037SARM gem5 Developers /** True if the current lookup is performed in AArch64 state */ 41710037SARM gem5 Developers bool aarch64; 41810037SARM gem5 Developers 41910037SARM gem5 Developers /** Width of the granule size in bits */ 42010324SCurtis.Dunham@arm.com GrainSize grainSize; 42110037SARM gem5 Developers 42210037SARM gem5 Developers /** Return the descriptor type */ 42310037SARM gem5 Developers EntryType type() const 42410037SARM gem5 Developers { 42510037SARM gem5 Developers switch (bits(data, 1, 0)) { 42610037SARM gem5 Developers case 0x1: 42710037SARM gem5 Developers // In AArch64 blocks are not allowed at L0 for the 4 KB granule 42810324SCurtis.Dunham@arm.com // and at L1 for 16/64 KB granules 42910324SCurtis.Dunham@arm.com if (grainSize > Grain4KB) 43010037SARM gem5 Developers return lookupLevel == L2 ? Block : Invalid; 43110037SARM gem5 Developers return lookupLevel == L0 || lookupLevel == L3 ? Invalid : Block; 43210037SARM gem5 Developers case 0x3: 43310037SARM gem5 Developers return lookupLevel == L3 ? Page : Table; 43410037SARM gem5 Developers default: 43510037SARM gem5 Developers return Invalid; 43610037SARM gem5 Developers } 43710037SARM gem5 Developers } 43810037SARM gem5 Developers 43910037SARM gem5 Developers /** Return the bit width of the page/block offset */ 44010037SARM gem5 Developers uint8_t offsetBits() const 44110037SARM gem5 Developers { 44210324SCurtis.Dunham@arm.com if (type() == Block) { 44310324SCurtis.Dunham@arm.com switch (grainSize) { 44410324SCurtis.Dunham@arm.com case Grain4KB: 44510324SCurtis.Dunham@arm.com return lookupLevel == L1 ? 30 /* 1 GB */ 44610324SCurtis.Dunham@arm.com : 21 /* 2 MB */; 44710324SCurtis.Dunham@arm.com case Grain16KB: 44810324SCurtis.Dunham@arm.com return 25 /* 32 MB */; 44910324SCurtis.Dunham@arm.com case Grain64KB: 45010324SCurtis.Dunham@arm.com return 29 /* 512 MB */; 45110324SCurtis.Dunham@arm.com default: 45210324SCurtis.Dunham@arm.com panic("Invalid AArch64 VM granule size\n"); 45310324SCurtis.Dunham@arm.com } 45410324SCurtis.Dunham@arm.com } else if (type() == Page) { 45510324SCurtis.Dunham@arm.com switch (grainSize) { 45610324SCurtis.Dunham@arm.com case Grain4KB: 45710324SCurtis.Dunham@arm.com case Grain16KB: 45810324SCurtis.Dunham@arm.com case Grain64KB: 45910324SCurtis.Dunham@arm.com return grainSize; /* enum -> uint okay */ 46010324SCurtis.Dunham@arm.com default: 46110324SCurtis.Dunham@arm.com panic("Invalid AArch64 VM granule size\n"); 46210324SCurtis.Dunham@arm.com } 46310037SARM gem5 Developers } else { 46410324SCurtis.Dunham@arm.com panic("AArch64 page table entry must be block or page\n"); 46510037SARM gem5 Developers } 46610037SARM gem5 Developers } 46710037SARM gem5 Developers 46810037SARM gem5 Developers /** Return the physical frame, bits shifted right */ 46910037SARM gem5 Developers Addr pfn() const 47010037SARM gem5 Developers { 47110037SARM gem5 Developers if (aarch64) 47210037SARM gem5 Developers return bits(data, 47, offsetBits()); 47310037SARM gem5 Developers return bits(data, 39, offsetBits()); 47410037SARM gem5 Developers } 47510037SARM gem5 Developers 47610037SARM gem5 Developers /** Return the complete physical address given a VA */ 47710037SARM gem5 Developers Addr paddr(Addr va) const 47810037SARM gem5 Developers { 47910037SARM gem5 Developers int n = offsetBits(); 48010037SARM gem5 Developers if (aarch64) 48110037SARM gem5 Developers return mbits(data, 47, n) | mbits(va, n - 1, 0); 48210037SARM gem5 Developers return mbits(data, 39, n) | mbits(va, n - 1, 0); 48310037SARM gem5 Developers } 48410037SARM gem5 Developers 48510037SARM gem5 Developers /** Return the physical address of the entry */ 48610037SARM gem5 Developers Addr paddr() const 48710037SARM gem5 Developers { 48810037SARM gem5 Developers if (aarch64) 48910037SARM gem5 Developers return mbits(data, 47, offsetBits()); 49010037SARM gem5 Developers return mbits(data, 39, offsetBits()); 49110037SARM gem5 Developers } 49210037SARM gem5 Developers 49310037SARM gem5 Developers /** Return the address of the next page table */ 49410037SARM gem5 Developers Addr nextTableAddr() const 49510037SARM gem5 Developers { 49610037SARM gem5 Developers assert(type() == Table); 49710037SARM gem5 Developers if (aarch64) 49810037SARM gem5 Developers return mbits(data, 47, grainSize); 49910037SARM gem5 Developers else 50010037SARM gem5 Developers return mbits(data, 39, 12); 50110037SARM gem5 Developers } 50210037SARM gem5 Developers 50310037SARM gem5 Developers /** Return the address of the next descriptor */ 50410037SARM gem5 Developers Addr nextDescAddr(Addr va) const 50510037SARM gem5 Developers { 50610037SARM gem5 Developers assert(type() == Table); 50710037SARM gem5 Developers Addr pa = 0; 50810037SARM gem5 Developers if (aarch64) { 50910037SARM gem5 Developers int stride = grainSize - 3; 51010037SARM gem5 Developers int va_lo = stride * (3 - (lookupLevel + 1)) + grainSize; 51110037SARM gem5 Developers int va_hi = va_lo + stride - 1; 51210037SARM gem5 Developers pa = nextTableAddr() | (bits(va, va_hi, va_lo) << 3); 51310037SARM gem5 Developers } else { 51410037SARM gem5 Developers if (lookupLevel == L1) 51510037SARM gem5 Developers pa = nextTableAddr() | (bits(va, 29, 21) << 3); 51610037SARM gem5 Developers else // lookupLevel == L2 51710037SARM gem5 Developers pa = nextTableAddr() | (bits(va, 20, 12) << 3); 51810037SARM gem5 Developers } 51910037SARM gem5 Developers return pa; 52010037SARM gem5 Developers } 52110037SARM gem5 Developers 52210037SARM gem5 Developers /** Is execution allowed on this mapping? */ 52310037SARM gem5 Developers bool xn() const 52410037SARM gem5 Developers { 52510037SARM gem5 Developers assert(type() == Block || type() == Page); 52610037SARM gem5 Developers return bits(data, 54); 52710037SARM gem5 Developers } 52810037SARM gem5 Developers 52910037SARM gem5 Developers /** Is privileged execution allowed on this mapping? (LPAE only) */ 53010037SARM gem5 Developers bool pxn() const 53110037SARM gem5 Developers { 53210037SARM gem5 Developers assert(type() == Block || type() == Page); 53310037SARM gem5 Developers return bits(data, 53); 53410037SARM gem5 Developers } 53510037SARM gem5 Developers 53610037SARM gem5 Developers /** Contiguous hint bit. */ 53710037SARM gem5 Developers bool contiguousHint() const 53810037SARM gem5 Developers { 53910037SARM gem5 Developers assert(type() == Block || type() == Page); 54010037SARM gem5 Developers return bits(data, 52); 54110037SARM gem5 Developers } 54210037SARM gem5 Developers 54310037SARM gem5 Developers /** Is the translation global (no asid used)? */ 54410037SARM gem5 Developers bool global(WalkerState *currState) const 54510037SARM gem5 Developers { 54610037SARM gem5 Developers assert(currState && (type() == Block || type() == Page)); 54710037SARM gem5 Developers if (!currState->aarch64 && (currState->isSecure && 54810037SARM gem5 Developers !currState->secureLookup)) { 54910037SARM gem5 Developers return false; // ARM ARM issue C B3.6.3 55010037SARM gem5 Developers } else if (currState->aarch64) { 55110037SARM gem5 Developers if (currState->el == EL2 || currState->el == EL3) { 55210037SARM gem5 Developers return true; // By default translations are treated as global 55310037SARM gem5 Developers // in AArch64 EL2 and EL3 55410037SARM gem5 Developers } else if (currState->isSecure && !currState->secureLookup) { 55510037SARM gem5 Developers return false; 55610037SARM gem5 Developers } 55710037SARM gem5 Developers } 55810037SARM gem5 Developers return !bits(data, 11); 55910037SARM gem5 Developers } 56010037SARM gem5 Developers 56110037SARM gem5 Developers /** Returns true if the access flag (AF) is set. */ 56210037SARM gem5 Developers bool af() const 56310037SARM gem5 Developers { 56410037SARM gem5 Developers assert(type() == Block || type() == Page); 56510037SARM gem5 Developers return bits(data, 10); 56610037SARM gem5 Developers } 56710037SARM gem5 Developers 56810037SARM gem5 Developers /** 2-bit shareability field */ 56910037SARM gem5 Developers uint8_t sh() const 57010037SARM gem5 Developers { 57110037SARM gem5 Developers assert(type() == Block || type() == Page); 57210037SARM gem5 Developers return bits(data, 9, 8); 57310037SARM gem5 Developers } 57410037SARM gem5 Developers 57510037SARM gem5 Developers /** 2-bit access protection flags */ 57610037SARM gem5 Developers uint8_t ap() const 57710037SARM gem5 Developers { 57810037SARM gem5 Developers assert(type() == Block || type() == Page); 57910037SARM gem5 Developers // Long descriptors only support the AP[2:1] scheme 58010037SARM gem5 Developers return bits(data, 7, 6); 58110037SARM gem5 Developers } 58210037SARM gem5 Developers 58310037SARM gem5 Developers /** Read/write access protection flag */ 58410037SARM gem5 Developers bool rw() const 58510037SARM gem5 Developers { 58610037SARM gem5 Developers assert(type() == Block || type() == Page); 58710037SARM gem5 Developers return !bits(data, 7); 58810037SARM gem5 Developers } 58910037SARM gem5 Developers 59010037SARM gem5 Developers /** User/privileged level access protection flag */ 59110037SARM gem5 Developers bool user() const 59210037SARM gem5 Developers { 59310037SARM gem5 Developers assert(type() == Block || type() == Page); 59410037SARM gem5 Developers return bits(data, 6); 59510037SARM gem5 Developers } 59610037SARM gem5 Developers 59710037SARM gem5 Developers /** Return the AP bits as compatible with the AP[2:0] format. Utility 59810037SARM gem5 Developers * function used to simplify the code in the TLB for performing 59910037SARM gem5 Developers * permission checks. */ 60010037SARM gem5 Developers static uint8_t ap(bool rw, bool user) 60110037SARM gem5 Developers { 60210037SARM gem5 Developers return ((!rw) << 2) | (user << 1); 60310037SARM gem5 Developers } 60410037SARM gem5 Developers 60510037SARM gem5 Developers TlbEntry::DomainType domain() const 60610037SARM gem5 Developers { 60710037SARM gem5 Developers // Long-desc. format only supports Client domain 60810037SARM gem5 Developers assert(type() == Block || type() == Page); 60910037SARM gem5 Developers return TlbEntry::DomainType::Client; 61010037SARM gem5 Developers } 61110037SARM gem5 Developers 61210037SARM gem5 Developers /** Attribute index */ 61310037SARM gem5 Developers uint8_t attrIndx() const 61410037SARM gem5 Developers { 61510037SARM gem5 Developers assert(type() == Block || type() == Page); 61610037SARM gem5 Developers return bits(data, 4, 2); 61710037SARM gem5 Developers } 61810037SARM gem5 Developers 61910037SARM gem5 Developers /** Memory attributes, only used by stage 2 translations */ 62010037SARM gem5 Developers uint8_t memAttr() const 62110037SARM gem5 Developers { 62210037SARM gem5 Developers assert(type() == Block || type() == Page); 62310037SARM gem5 Developers return bits(data, 5, 2); 62410037SARM gem5 Developers } 62510037SARM gem5 Developers 62610037SARM gem5 Developers /** Set access flag that this entry has been touched. Mark the entry as 62710037SARM gem5 Developers * requiring a writeback, in the future. */ 62810037SARM gem5 Developers void setAf() 62910037SARM gem5 Developers { 63010037SARM gem5 Developers data |= 1 << 10; 63110037SARM gem5 Developers _dirty = true; 63210037SARM gem5 Developers } 63310037SARM gem5 Developers 63410037SARM gem5 Developers /** This entry needs to be written back to memory */ 63510037SARM gem5 Developers bool dirty() const 63610037SARM gem5 Developers { 63710037SARM gem5 Developers return _dirty; 63810037SARM gem5 Developers } 63910037SARM gem5 Developers 64010037SARM gem5 Developers /** Whether the subsequent levels of lookup are secure */ 64110037SARM gem5 Developers bool secureTable() const 64210037SARM gem5 Developers { 64310037SARM gem5 Developers assert(type() == Table); 64410037SARM gem5 Developers return !bits(data, 63); 64510037SARM gem5 Developers } 64610037SARM gem5 Developers 64710037SARM gem5 Developers /** Two bit access protection flags for subsequent levels of lookup */ 64810037SARM gem5 Developers uint8_t apTable() const 64910037SARM gem5 Developers { 65010037SARM gem5 Developers assert(type() == Table); 65110037SARM gem5 Developers return bits(data, 62, 61); 65210037SARM gem5 Developers } 65310037SARM gem5 Developers 65410037SARM gem5 Developers /** R/W protection flag for subsequent levels of lookup */ 65510037SARM gem5 Developers uint8_t rwTable() const 65610037SARM gem5 Developers { 65710037SARM gem5 Developers assert(type() == Table); 65810037SARM gem5 Developers return !bits(data, 62); 65910037SARM gem5 Developers } 66010037SARM gem5 Developers 66110037SARM gem5 Developers /** User/privileged mode protection flag for subsequent levels of 66210037SARM gem5 Developers * lookup */ 66310037SARM gem5 Developers uint8_t userTable() const 66410037SARM gem5 Developers { 66510037SARM gem5 Developers assert(type() == Table); 66610037SARM gem5 Developers return !bits(data, 61); 66710037SARM gem5 Developers } 66810037SARM gem5 Developers 66910037SARM gem5 Developers /** Is execution allowed on subsequent lookup levels? */ 67010037SARM gem5 Developers bool xnTable() const 67110037SARM gem5 Developers { 67210037SARM gem5 Developers assert(type() == Table); 67310037SARM gem5 Developers return bits(data, 60); 67410037SARM gem5 Developers } 67510037SARM gem5 Developers 67610037SARM gem5 Developers /** Is privileged execution allowed on subsequent lookup levels? */ 67710037SARM gem5 Developers bool pxnTable() const 67810037SARM gem5 Developers { 67910037SARM gem5 Developers assert(type() == Table); 68010037SARM gem5 Developers return bits(data, 59); 68110037SARM gem5 Developers } 68210037SARM gem5 Developers }; 68310037SARM gem5 Developers 68410037SARM gem5 Developers class WalkerState 68510037SARM gem5 Developers { 68610037SARM gem5 Developers public: 68710037SARM gem5 Developers /** Thread context that we're doing the walk for */ 68810037SARM gem5 Developers ThreadContext *tc; 68910037SARM gem5 Developers 69010037SARM gem5 Developers /** If the access is performed in AArch64 state */ 69110037SARM gem5 Developers bool aarch64; 69210037SARM gem5 Developers 69310037SARM gem5 Developers /** Current exception level */ 69410037SARM gem5 Developers ExceptionLevel el; 69510037SARM gem5 Developers 69610037SARM gem5 Developers /** Current physical address range in bits */ 69710037SARM gem5 Developers int physAddrRange; 69810037SARM gem5 Developers 69910037SARM gem5 Developers /** Request that is currently being serviced */ 70010037SARM gem5 Developers RequestPtr req; 70110037SARM gem5 Developers 70210037SARM gem5 Developers /** ASID that we're servicing the request under */ 70310037SARM gem5 Developers uint16_t asid; 70410037SARM gem5 Developers uint8_t vmid; 70510037SARM gem5 Developers bool isHyp; 70610037SARM gem5 Developers 70710037SARM gem5 Developers /** Translation state for delayed requests */ 70810037SARM gem5 Developers TLB::Translation *transState; 70910037SARM gem5 Developers 71010037SARM gem5 Developers /** The fault that we are going to return */ 71110037SARM gem5 Developers Fault fault; 71210037SARM gem5 Developers 71310037SARM gem5 Developers /** The virtual address that is being translated with tagging removed.*/ 71410037SARM gem5 Developers Addr vaddr; 71510037SARM gem5 Developers 71610037SARM gem5 Developers /** The virtual address that is being translated */ 71710037SARM gem5 Developers Addr vaddr_tainted; 71810037SARM gem5 Developers 71910037SARM gem5 Developers /** Cached copy of the sctlr as it existed when translation began */ 72010037SARM gem5 Developers SCTLR sctlr; 72110037SARM gem5 Developers 72210037SARM gem5 Developers /** Cached copy of the scr as it existed when translation began */ 72310037SARM gem5 Developers SCR scr; 72410037SARM gem5 Developers 72510037SARM gem5 Developers /** Cached copy of the cpsr as it existed when translation began */ 72610037SARM gem5 Developers CPSR cpsr; 72710037SARM gem5 Developers 72810324SCurtis.Dunham@arm.com /** Cached copy of ttbcr/tcr as it existed when translation began */ 72910324SCurtis.Dunham@arm.com union { 73010324SCurtis.Dunham@arm.com TTBCR ttbcr; // AArch32 translations 73110324SCurtis.Dunham@arm.com TCR tcr; // AArch64 translations 73210324SCurtis.Dunham@arm.com }; 73310037SARM gem5 Developers 73410037SARM gem5 Developers /** Cached copy of the htcr as it existed when translation began. */ 73510037SARM gem5 Developers HTCR htcr; 73610037SARM gem5 Developers 73710037SARM gem5 Developers /** Cached copy of the htcr as it existed when translation began. */ 73810037SARM gem5 Developers HCR hcr; 73910037SARM gem5 Developers 74010037SARM gem5 Developers /** Cached copy of the vtcr as it existed when translation began. */ 74110037SARM gem5 Developers VTCR_t vtcr; 74210037SARM gem5 Developers 74310037SARM gem5 Developers /** If the access is a write */ 74410037SARM gem5 Developers bool isWrite; 74510037SARM gem5 Developers 74610037SARM gem5 Developers /** If the access is a fetch (for execution, and no-exec) must be checked?*/ 74710037SARM gem5 Developers bool isFetch; 74810037SARM gem5 Developers 74910037SARM gem5 Developers /** If the access comes from the secure state. */ 75010037SARM gem5 Developers bool isSecure; 75110037SARM gem5 Developers 75210037SARM gem5 Developers /** Helper variables used to implement hierarchical access permissions 75310037SARM gem5 Developers * when the long-desc. format is used (LPAE only) */ 75410037SARM gem5 Developers bool secureLookup; 75510037SARM gem5 Developers bool rwTable; 75610037SARM gem5 Developers bool userTable; 75710037SARM gem5 Developers bool xnTable; 75810037SARM gem5 Developers bool pxnTable; 75910037SARM gem5 Developers 76010037SARM gem5 Developers /** Flag indicating if a second stage of lookup is required */ 76110037SARM gem5 Developers bool stage2Req; 76210037SARM gem5 Developers 76310037SARM gem5 Developers /** Indicates whether the translation has been passed onto the second 76410037SARM gem5 Developers * stage mmu, and no more work is required from the first stage. 76510037SARM gem5 Developers */ 76610037SARM gem5 Developers bool doingStage2; 76710037SARM gem5 Developers 76810037SARM gem5 Developers /** A pointer to the stage 2 translation that's in progress */ 76910037SARM gem5 Developers TLB::Translation *stage2Tran; 77010037SARM gem5 Developers 77110037SARM gem5 Developers /** If the mode is timing or atomic */ 77210037SARM gem5 Developers bool timing; 77310037SARM gem5 Developers 77410037SARM gem5 Developers /** If the atomic mode should be functional */ 77510037SARM gem5 Developers bool functional; 77610037SARM gem5 Developers 77710037SARM gem5 Developers /** Save mode for use in delayed response */ 77810037SARM gem5 Developers BaseTLB::Mode mode; 77910037SARM gem5 Developers 78010037SARM gem5 Developers /** The translation type that has been requested */ 78110037SARM gem5 Developers TLB::ArmTranslationType tranType; 78210037SARM gem5 Developers 78310037SARM gem5 Developers /** Short-format descriptors */ 78410037SARM gem5 Developers L1Descriptor l1Desc; 78510037SARM gem5 Developers L2Descriptor l2Desc; 78610037SARM gem5 Developers 78710037SARM gem5 Developers /** Long-format descriptor (LPAE and AArch64) */ 78810037SARM gem5 Developers LongDescriptor longDesc; 78910037SARM gem5 Developers 79010037SARM gem5 Developers /** Whether the response is delayed in timing mode due to additional 79110037SARM gem5 Developers * lookups */ 79210037SARM gem5 Developers bool delayed; 79310037SARM gem5 Developers 79410037SARM gem5 Developers TableWalker *tableWalker; 79510037SARM gem5 Developers 79610621SCurtis.Dunham@arm.com /** Timestamp for calculating elapsed time in service (for stats) */ 79710621SCurtis.Dunham@arm.com Tick startTime; 79810621SCurtis.Dunham@arm.com 79910621SCurtis.Dunham@arm.com /** Page entries walked during service (for stats) */ 80010621SCurtis.Dunham@arm.com unsigned levels; 80110621SCurtis.Dunham@arm.com 80210037SARM gem5 Developers void doL1Descriptor(); 80310037SARM gem5 Developers void doL2Descriptor(); 80410037SARM gem5 Developers 80510037SARM gem5 Developers void doLongDescriptor(); 80610037SARM gem5 Developers 80710037SARM gem5 Developers WalkerState(); 80810037SARM gem5 Developers 80910037SARM gem5 Developers std::string name() const { return tableWalker->name(); } 81010037SARM gem5 Developers }; 81110037SARM gem5 Developers 8129015Sandreas.hansson@arm.com protected: 8139015Sandreas.hansson@arm.com 81410037SARM gem5 Developers /** Queues of requests for all the different lookup levels */ 81510037SARM gem5 Developers std::list<WalkerState *> stateQueues[MAX_LOOKUP_LEVELS]; 8167439Sdam.sunwoo@arm.com 8177728SAli.Saidi@ARM.com /** Queue of requests that have passed are waiting because the walker is 8187728SAli.Saidi@ARM.com * currently busy. */ 8198902Sandreas.hansson@arm.com std::list<WalkerState *> pendingQueue; 8207728SAli.Saidi@ARM.com 8219152Satgutier@umich.edu /** If we're draining keep the drain event around until we're drained */ 8229342SAndreas.Sandberg@arm.com DrainManager *drainManager; 8239152Satgutier@umich.edu 82410037SARM gem5 Developers /** The MMU to forward second stage look upts to */ 82510037SARM gem5 Developers Stage2MMU *stage2Mmu; 82610037SARM gem5 Developers 82710717Sandreas.hansson@arm.com /** Port shared by the two table walkers. */ 82810717Sandreas.hansson@arm.com DmaPort* port; 82910717Sandreas.hansson@arm.com 83010717Sandreas.hansson@arm.com /** Master id assigned by the MMU. */ 83110717Sandreas.hansson@arm.com MasterID masterId; 83210717Sandreas.hansson@arm.com 83310037SARM gem5 Developers /** Indicates whether this table walker is part of the stage 2 mmu */ 83410037SARM gem5 Developers const bool isStage2; 83510037SARM gem5 Developers 8367404SAli.Saidi@ARM.com /** TLB that is initiating these table walks */ 8377404SAli.Saidi@ARM.com TLB *tlb; 8387404SAli.Saidi@ARM.com 8397404SAli.Saidi@ARM.com /** Cached copy of the sctlr as it existed when translation began */ 8407404SAli.Saidi@ARM.com SCTLR sctlr; 8417404SAli.Saidi@ARM.com 8427439Sdam.sunwoo@arm.com WalkerState *currState; 8437437Sdam.sunwoo@arm.com 8447728SAli.Saidi@ARM.com /** If a timing translation is currently in progress */ 8457728SAli.Saidi@ARM.com bool pending; 8467728SAli.Saidi@ARM.com 8479258SAli.Saidi@ARM.com /** The number of walks belonging to squashed instructions that can be 8489258SAli.Saidi@ARM.com * removed from the pendingQueue per cycle. */ 8499258SAli.Saidi@ARM.com unsigned numSquashable; 8509258SAli.Saidi@ARM.com 85110037SARM gem5 Developers /** Cached copies of system-level properties */ 85210037SARM gem5 Developers bool haveSecurity; 85310037SARM gem5 Developers bool _haveLPAE; 85410037SARM gem5 Developers bool _haveVirtualization; 85510037SARM gem5 Developers uint8_t physAddrRange; 85610037SARM gem5 Developers bool _haveLargeAsid64; 85710037SARM gem5 Developers 85810621SCurtis.Dunham@arm.com /** Statistics */ 85910621SCurtis.Dunham@arm.com Stats::Scalar statWalks; 86010621SCurtis.Dunham@arm.com Stats::Scalar statWalksShortDescriptor; 86110621SCurtis.Dunham@arm.com Stats::Scalar statWalksLongDescriptor; 86210621SCurtis.Dunham@arm.com Stats::Vector statWalksShortTerminatedAtLevel; 86310621SCurtis.Dunham@arm.com Stats::Vector statWalksLongTerminatedAtLevel; 86410621SCurtis.Dunham@arm.com Stats::Scalar statSquashedBefore; 86510621SCurtis.Dunham@arm.com Stats::Scalar statSquashedAfter; 86610621SCurtis.Dunham@arm.com Stats::Histogram statWalkWaitTime; 86710621SCurtis.Dunham@arm.com Stats::Histogram statWalkServiceTime; 86810621SCurtis.Dunham@arm.com Stats::Histogram statPendingWalks; // essentially "L" of queueing theory 86910621SCurtis.Dunham@arm.com Stats::Vector statPageSizes; 87010621SCurtis.Dunham@arm.com Stats::Vector2d statRequestOrigin; 87110621SCurtis.Dunham@arm.com 87210621SCurtis.Dunham@arm.com mutable unsigned pendingReqs; 87310621SCurtis.Dunham@arm.com mutable Tick pendingChangeTick; 87410621SCurtis.Dunham@arm.com 87510621SCurtis.Dunham@arm.com static const unsigned REQUESTED = 0; 87610621SCurtis.Dunham@arm.com static const unsigned COMPLETED = 1; 87710621SCurtis.Dunham@arm.com 8787404SAli.Saidi@ARM.com public: 87910037SARM gem5 Developers typedef ArmTableWalkerParams Params; 8807404SAli.Saidi@ARM.com TableWalker(const Params *p); 8817404SAli.Saidi@ARM.com virtual ~TableWalker(); 8827404SAli.Saidi@ARM.com 8837404SAli.Saidi@ARM.com const Params * 8847404SAli.Saidi@ARM.com params() const 8857404SAli.Saidi@ARM.com { 8867404SAli.Saidi@ARM.com return dynamic_cast<const Params *>(_params); 8877404SAli.Saidi@ARM.com } 8887404SAli.Saidi@ARM.com 88910717Sandreas.hansson@arm.com virtual void init(); 89010717Sandreas.hansson@arm.com 89110037SARM gem5 Developers bool haveLPAE() const { return _haveLPAE; } 89210037SARM gem5 Developers bool haveVirtualization() const { return _haveVirtualization; } 89310037SARM gem5 Developers bool haveLargeAsid64() const { return _haveLargeAsid64; } 8949152Satgutier@umich.edu /** Checks if all state is cleared and if so, completes drain */ 8959152Satgutier@umich.edu void completeDrain(); 8969342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *dm); 89710037SARM gem5 Developers virtual void drainResume(); 89810717Sandreas.hansson@arm.com 8999294Sandreas.hansson@arm.com virtual BaseMasterPort& getMasterPort(const std::string &if_name, 9009294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 90110717Sandreas.hansson@arm.com 90210621SCurtis.Dunham@arm.com void regStats(); 9037404SAli.Saidi@ARM.com 90410037SARM gem5 Developers Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid, 90510037SARM gem5 Developers bool _isHyp, TLB::Mode mode, TLB::Translation *_trans, 90610037SARM gem5 Developers bool timing, bool functional, bool secure, 90710037SARM gem5 Developers TLB::ArmTranslationType tranType); 9087404SAli.Saidi@ARM.com 9097404SAli.Saidi@ARM.com void setTlb(TLB *_tlb) { tlb = _tlb; } 91010037SARM gem5 Developers TLB* getTlb() { return tlb; } 91110717Sandreas.hansson@arm.com void setMMU(Stage2MMU *m, MasterID master_id); 9127439Sdam.sunwoo@arm.com void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, 9137439Sdam.sunwoo@arm.com uint8_t texcb, bool s); 91410037SARM gem5 Developers void memAttrsLPAE(ThreadContext *tc, TlbEntry &te, 91510037SARM gem5 Developers LongDescriptor &lDescriptor); 91610037SARM gem5 Developers void memAttrsAArch64(ThreadContext *tc, TlbEntry &te, uint8_t attrIndx, 91710037SARM gem5 Developers uint8_t sh); 91810037SARM gem5 Developers 91910037SARM gem5 Developers static LookupLevel toLookupLevel(uint8_t lookup_level_as_int); 9207404SAli.Saidi@ARM.com 9217404SAli.Saidi@ARM.com private: 9227404SAli.Saidi@ARM.com 9237404SAli.Saidi@ARM.com void doL1Descriptor(); 9247437Sdam.sunwoo@arm.com void doL1DescriptorWrapper(); 92510037SARM gem5 Developers EventWrapper<TableWalker, 92610037SARM gem5 Developers &TableWalker::doL1DescriptorWrapper> doL1DescEvent; 9277404SAli.Saidi@ARM.com 9287404SAli.Saidi@ARM.com void doL2Descriptor(); 9297437Sdam.sunwoo@arm.com void doL2DescriptorWrapper(); 93010037SARM gem5 Developers EventWrapper<TableWalker, 93110037SARM gem5 Developers &TableWalker::doL2DescriptorWrapper> doL2DescEvent; 93210037SARM gem5 Developers 93310037SARM gem5 Developers void doLongDescriptor(); 93410037SARM gem5 Developers 93510037SARM gem5 Developers void doL0LongDescriptorWrapper(); 93610037SARM gem5 Developers EventWrapper<TableWalker, 93710037SARM gem5 Developers &TableWalker::doL0LongDescriptorWrapper> doL0LongDescEvent; 93810037SARM gem5 Developers void doL1LongDescriptorWrapper(); 93910037SARM gem5 Developers EventWrapper<TableWalker, 94010037SARM gem5 Developers &TableWalker::doL1LongDescriptorWrapper> doL1LongDescEvent; 94110037SARM gem5 Developers void doL2LongDescriptorWrapper(); 94210037SARM gem5 Developers EventWrapper<TableWalker, 94310037SARM gem5 Developers &TableWalker::doL2LongDescriptorWrapper> doL2LongDescEvent; 94410037SARM gem5 Developers void doL3LongDescriptorWrapper(); 94510037SARM gem5 Developers EventWrapper<TableWalker, 94610037SARM gem5 Developers &TableWalker::doL3LongDescriptorWrapper> doL3LongDescEvent; 94710037SARM gem5 Developers 94810037SARM gem5 Developers void doLongDescriptorWrapper(LookupLevel curr_lookup_level); 94910037SARM gem5 Developers 95010037SARM gem5 Developers bool fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, 95110037SARM gem5 Developers Request::Flags flags, int queueIndex, Event *event, 95210037SARM gem5 Developers void (TableWalker::*doDescriptor)()); 95310037SARM gem5 Developers 95410037SARM gem5 Developers void insertTableEntry(DescriptorBase &descriptor, bool longDescriptor); 9557404SAli.Saidi@ARM.com 9567728SAli.Saidi@ARM.com Fault processWalk(); 95710037SARM gem5 Developers Fault processWalkLPAE(); 95810037SARM gem5 Developers static unsigned adjustTableSizeAArch64(unsigned tsz); 95910037SARM gem5 Developers /// Returns true if the address exceeds the range permitted by the 96010037SARM gem5 Developers /// system-wide setting or by the TCR_ELx IPS/PS setting 96110037SARM gem5 Developers static bool checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange); 96210037SARM gem5 Developers Fault processWalkAArch64(); 9637728SAli.Saidi@ARM.com void processWalkWrapper(); 9647728SAli.Saidi@ARM.com EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent; 9657404SAli.Saidi@ARM.com 9667728SAli.Saidi@ARM.com void nextWalk(ThreadContext *tc); 96710621SCurtis.Dunham@arm.com 96810621SCurtis.Dunham@arm.com void pendingChange(); 96910621SCurtis.Dunham@arm.com 97010621SCurtis.Dunham@arm.com static uint8_t pageSizeNtoStatBin(uint8_t N); 9717404SAli.Saidi@ARM.com}; 9727404SAli.Saidi@ARM.com 9737404SAli.Saidi@ARM.com} // namespace ArmISA 9747404SAli.Saidi@ARM.com 9757404SAli.Saidi@ARM.com#endif //__ARCH_ARM_TABLE_WALKER_HH__ 9767404SAli.Saidi@ARM.com 977