system.hh revision 14133:f3e7e7c3803d 
1/*
2 * Copyright (c) 2010, 2012-2013, 2015-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <memory>
47#include <string>
48#include <vector>
49
50#include "kern/linux/events.hh"
51#include "params/ArmSystem.hh"
52#include "params/GenericArmSystem.hh"
53#include "sim/sim_object.hh"
54#include "sim/system.hh"
55
56class GenericTimer;
57class BaseGic;
58class ThreadContext;
59
60class ArmSystem : public System
61{
62  protected:
63    /**
64     * PC based event to skip the dprink() call and emulate its
65     * functionality
66     */
67    Linux::DebugPrintkEvent *debugPrintkEvent;
68
69    /** Bootloaders */
70    std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
71
72    /**
73     * Pointer to the bootloader object
74     */
75    ObjectFile *bootldr;
76
77    /**
78     * True if this system implements the Security Extensions
79     */
80    const bool _haveSecurity;
81
82    /**
83     * True if this system implements the Large Physical Address Extension
84     */
85    const bool _haveLPAE;
86
87    /**
88     * True if this system implements the virtualization Extensions
89     */
90    const bool _haveVirtualization;
91
92    /**
93     * True if this system implements the Crypto Extension
94     */
95    const bool _haveCrypto;
96
97    /**
98     * Pointer to the Generic Timer wrapper.
99     */
100    GenericTimer *_genericTimer;
101    BaseGic *_gic;
102
103    /**
104     * Reset address (ARMv8)
105     */
106    const Addr _resetAddr;
107
108    /**
109     * True if the register width of the highest implemented exception level is
110     * 64 bits (ARMv8)
111     */
112    bool _highestELIs64;
113
114    /**
115     * Supported physical address range in bits if the highest implemented
116     * exception level is 64 bits (ARMv8)
117     */
118    const uint8_t _physAddrRange64;
119
120    /**
121     * True if ASID is 16 bits in AArch64 (ARMv8)
122     */
123    const bool _haveLargeAsid64;
124
125    /**
126     * True if SVE is implemented (ARMv8)
127     */
128    const bool _haveSVE;
129
130    /** SVE vector length at reset, in quadwords */
131    const unsigned _sveVL;
132
133    /**
134     * True if LSE is implemented (ARMv8.1)
135     */
136    const bool _haveLSE;
137
138    /** True if Priviledge Access Never is implemented */
139    const unsigned _havePAN;
140
141    /**
142     * Range for memory-mapped m5 pseudo ops. The range will be
143     * invalid/empty if disabled.
144     */
145    const AddrRange _m5opRange;
146
147    /**
148     * True if the Semihosting interface is enabled.
149     */
150    ArmSemihosting *const semihosting;
151
152  protected:
153    /**
154     * Get a boot loader that matches the kernel.
155     *
156     * @param obj Kernel binary
157     * @return Pointer to boot loader ObjectFile or nullptr if there
158     *         is no matching boot loader.
159     */
160    ObjectFile *getBootLoader(ObjectFile *const obj);
161
162  public:
163    typedef ArmSystemParams Params;
164    const Params *
165    params() const
166    {
167        return dynamic_cast<const Params *>(_params);
168    }
169
170    ArmSystem(Params *p);
171    ~ArmSystem();
172
173    /**
174     * Initialise the system
175     */
176    virtual void initState();
177
178    virtual Addr fixFuncEventAddr(Addr addr)
179    {
180        // Remove the low bit that thumb symbols have set
181        // but that aren't actually odd aligned
182        if (addr & 0x1)
183            return addr & ~1;
184        return addr;
185    }
186
187    /** true if this a multiprocessor system */
188    bool multiProc;
189
190    /** Returns true if this system implements the Security Extensions */
191    bool haveSecurity() const { return _haveSecurity; }
192
193    /** Returns true if this system implements the Large Physical Address
194     * Extension */
195    bool haveLPAE() const { return _haveLPAE; }
196
197    /** Returns true if this system implements the virtualization
198      * Extensions
199      */
200    bool haveVirtualization() const { return _haveVirtualization; }
201
202    /** Returns true if this system implements the Crypto
203      * Extension
204      */
205    bool haveCrypto() const { return _haveCrypto; }
206
207    /** Sets the pointer to the Generic Timer. */
208    void setGenericTimer(GenericTimer *generic_timer)
209    {
210        _genericTimer = generic_timer;
211    }
212
213    /** Sets the pointer to the GIC. */
214    void setGIC(BaseGic *gic)
215    {
216        _gic = gic;
217    }
218
219    /** Get a pointer to the system's generic timer model */
220    GenericTimer *getGenericTimer() const { return _genericTimer; }
221
222    /** Get a pointer to the system's GIC */
223    BaseGic *getGIC() const { return _gic; }
224
225    /** Returns true if the register width of the highest implemented exception
226     * level is 64 bits (ARMv8) */
227    bool highestELIs64() const { return _highestELIs64; }
228
229    /** Returns the highest implemented exception level */
230    ExceptionLevel highestEL() const
231    {
232        if (_haveSecurity)
233            return EL3;
234        if (_haveVirtualization)
235            return EL2;
236        return EL1;
237    }
238
239    /** Returns the reset address if the highest implemented exception level is
240     * 64 bits (ARMv8) */
241    Addr resetAddr() const { return _resetAddr; }
242
243    /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
244    bool haveLargeAsid64() const { return _haveLargeAsid64; }
245
246    /** Returns true if SVE is implemented (ARMv8) */
247    bool haveSVE() const { return _haveSVE; }
248
249    /** Returns the SVE vector length at reset, in quadwords */
250    unsigned sveVL() const { return _sveVL; }
251
252    /** Returns true if LSE is implemented (ARMv8.1) */
253    bool haveLSE() const { return _haveLSE; }
254
255    /** Returns true if Priviledge Access Never is implemented */
256    bool havePAN() const { return _havePAN; }
257
258    /** Returns the supported physical address range in bits if the highest
259     * implemented exception level is 64 bits (ARMv8) */
260    uint8_t physAddrRange64() const { return _physAddrRange64; }
261
262    /** Returns the supported physical address range in bits */
263    uint8_t physAddrRange() const
264    {
265        if (_highestELIs64)
266            return _physAddrRange64;
267        if (_haveLPAE)
268            return 40;
269        return 32;
270    }
271
272    /** Returns the physical address mask */
273    Addr physAddrMask() const
274    {
275        return mask(physAddrRange());
276    }
277
278    /**
279     * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
280     * an invalid/empty range if disabled.
281     */
282    const AddrRange &m5opRange() const { return _m5opRange; }
283
284    /** Is Arm Semihosting support enabled? */
285    bool haveSemihosting() const { return semihosting != nullptr; }
286
287    /**
288     * Returns a valid ArmSystem pointer if using ARM ISA, it fails
289     * otherwise.
290     */
291    static ArmSystem* getArmSystem(ThreadContext *tc);
292
293    /** Returns true if the system of a specific thread context implements the
294     * Security Extensions
295     */
296    static bool haveSecurity(ThreadContext *tc);
297
298    /** Returns true if the system of a specific thread context implements the
299     * virtualization Extensions
300     */
301    static bool haveVirtualization(ThreadContext *tc);
302
303    /** Returns true if the system of a specific thread context implements the
304     * Large Physical Address Extension
305     */
306    static bool haveLPAE(ThreadContext *tc);
307
308    /** Returns true if the register width of the highest implemented exception
309     * level for the system of a specific thread context is 64 bits (ARMv8)
310     */
311    static bool highestELIs64(ThreadContext *tc);
312
313    /** Returns the highest implemented exception level for the system of a
314     * specific thread context
315     */
316    static ExceptionLevel highestEL(ThreadContext *tc);
317
318    /** Return true if the system implements a specific exception level */
319    static bool haveEL(ThreadContext *tc, ExceptionLevel el);
320
321    /** Returns the reset address if the highest implemented exception level
322     * for the system of a specific thread context is 64 bits (ARMv8)
323     */
324    static Addr resetAddr(ThreadContext *tc);
325
326    /** Returns the supported physical address range in bits for the system of a
327     * specific thread context
328     */
329    static uint8_t physAddrRange(ThreadContext *tc);
330
331    /** Returns the physical address mask for the system of a specific thread
332     * context
333     */
334    static Addr physAddrMask(ThreadContext *tc);
335
336    /** Returns true if ASID is 16 bits for the system of a specific thread
337     * context while in AArch64 (ARMv8) */
338    static bool haveLargeAsid64(ThreadContext *tc);
339
340    /** Is Arm Semihosting support enabled? */
341    static bool haveSemihosting(ThreadContext *tc);
342
343    /** Make a Semihosting call from aarch64 */
344    static uint64_t callSemihosting64(ThreadContext *tc,
345                                      uint32_t op, uint64_t param);
346
347    /** Make a Semihosting call from aarch32 */
348    static uint32_t callSemihosting32(ThreadContext *tc,
349                                      uint32_t op, uint32_t param);
350};
351
352class GenericArmSystem : public ArmSystem
353{
354  public:
355    typedef GenericArmSystemParams Params;
356    const Params *
357    params() const
358    {
359        return dynamic_cast<const Params *>(_params);
360    }
361
362    GenericArmSystem(Params *p) : ArmSystem(p) {};
363    virtual ~GenericArmSystem() {};
364
365    /**
366     * Initialise the system
367     */
368    virtual void initState();
369};
370
371#endif
372