system.hh revision 14128:6ed23d07d0d1 
1/*
2 * Copyright (c) 2010, 2012-2013, 2015-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <memory>
47#include <string>
48#include <vector>
49
50#include "kern/linux/events.hh"
51#include "params/ArmSystem.hh"
52#include "params/GenericArmSystem.hh"
53#include "sim/sim_object.hh"
54#include "sim/system.hh"
55
56class GenericTimer;
57class BaseGic;
58class ThreadContext;
59
60class ArmSystem : public System
61{
62  protected:
63    /**
64     * PC based event to skip the dprink() call and emulate its
65     * functionality
66     */
67    Linux::DebugPrintkEvent *debugPrintkEvent;
68
69    /** Bootloaders */
70    std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
71
72    /**
73     * Pointer to the bootloader object
74     */
75    ObjectFile *bootldr;
76
77    /**
78     * True if this system implements the Security Extensions
79     */
80    const bool _haveSecurity;
81
82    /**
83     * True if this system implements the Large Physical Address Extension
84     */
85    const bool _haveLPAE;
86
87    /**
88     * True if this system implements the virtualization Extensions
89     */
90    const bool _haveVirtualization;
91
92    /**
93     * True if this system implements the Crypto Extension
94     */
95    const bool _haveCrypto;
96
97    /**
98     * Pointer to the Generic Timer wrapper.
99     */
100    GenericTimer *_genericTimer;
101    BaseGic *_gic;
102
103    /**
104     * Reset address (ARMv8)
105     */
106    const Addr _resetAddr;
107
108    /**
109     * True if the register width of the highest implemented exception level is
110     * 64 bits (ARMv8)
111     */
112    bool _highestELIs64;
113
114    /**
115     * Supported physical address range in bits if the highest implemented
116     * exception level is 64 bits (ARMv8)
117     */
118    const uint8_t _physAddrRange64;
119
120    /**
121     * True if ASID is 16 bits in AArch64 (ARMv8)
122     */
123    const bool _haveLargeAsid64;
124
125    /**
126     * True if SVE is implemented (ARMv8)
127     */
128    const bool _haveSVE;
129
130    /** SVE vector length at reset, in quadwords */
131    const unsigned _sveVL;
132
133    /** True if Priviledge Access Never is implemented */
134    const unsigned _havePAN;
135
136    /**
137     * Range for memory-mapped m5 pseudo ops. The range will be
138     * invalid/empty if disabled.
139     */
140    const AddrRange _m5opRange;
141
142    /**
143     * True if the Semihosting interface is enabled.
144     */
145    ArmSemihosting *const semihosting;
146
147  protected:
148    /**
149     * Get a boot loader that matches the kernel.
150     *
151     * @param obj Kernel binary
152     * @return Pointer to boot loader ObjectFile or nullptr if there
153     *         is no matching boot loader.
154     */
155    ObjectFile *getBootLoader(ObjectFile *const obj);
156
157  public:
158    typedef ArmSystemParams Params;
159    const Params *
160    params() const
161    {
162        return dynamic_cast<const Params *>(_params);
163    }
164
165    ArmSystem(Params *p);
166    ~ArmSystem();
167
168    /**
169     * Initialise the system
170     */
171    virtual void initState();
172
173    virtual Addr fixFuncEventAddr(Addr addr)
174    {
175        // Remove the low bit that thumb symbols have set
176        // but that aren't actually odd aligned
177        if (addr & 0x1)
178            return addr & ~1;
179        return addr;
180    }
181
182    /** true if this a multiprocessor system */
183    bool multiProc;
184
185    /** Returns true if this system implements the Security Extensions */
186    bool haveSecurity() const { return _haveSecurity; }
187
188    /** Returns true if this system implements the Large Physical Address
189     * Extension */
190    bool haveLPAE() const { return _haveLPAE; }
191
192    /** Returns true if this system implements the virtualization
193      * Extensions
194      */
195    bool haveVirtualization() const { return _haveVirtualization; }
196
197    /** Returns true if this system implements the Crypto
198      * Extension
199      */
200    bool haveCrypto() const { return _haveCrypto; }
201
202    /** Sets the pointer to the Generic Timer. */
203    void setGenericTimer(GenericTimer *generic_timer)
204    {
205        _genericTimer = generic_timer;
206    }
207
208    /** Sets the pointer to the GIC. */
209    void setGIC(BaseGic *gic)
210    {
211        _gic = gic;
212    }
213
214    /** Get a pointer to the system's generic timer model */
215    GenericTimer *getGenericTimer() const { return _genericTimer; }
216
217    /** Get a pointer to the system's GIC */
218    BaseGic *getGIC() const { return _gic; }
219
220    /** Returns true if the register width of the highest implemented exception
221     * level is 64 bits (ARMv8) */
222    bool highestELIs64() const { return _highestELIs64; }
223
224    /** Returns the highest implemented exception level */
225    ExceptionLevel highestEL() const
226    {
227        if (_haveSecurity)
228            return EL3;
229        if (_haveVirtualization)
230            return EL2;
231        return EL1;
232    }
233
234    /** Returns the reset address if the highest implemented exception level is
235     * 64 bits (ARMv8) */
236    Addr resetAddr() const { return _resetAddr; }
237
238    /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
239    bool haveLargeAsid64() const { return _haveLargeAsid64; }
240
241    /** Returns true if SVE is implemented (ARMv8) */
242    bool haveSVE() const { return _haveSVE; }
243
244    /** Returns the SVE vector length at reset, in quadwords */
245    unsigned sveVL() const { return _sveVL; }
246
247    /** Returns true if Priviledge Access Never is implemented */
248    bool havePAN() const { return _havePAN; }
249
250    /** Returns the supported physical address range in bits if the highest
251     * implemented exception level is 64 bits (ARMv8) */
252    uint8_t physAddrRange64() const { return _physAddrRange64; }
253
254    /** Returns the supported physical address range in bits */
255    uint8_t physAddrRange() const
256    {
257        if (_highestELIs64)
258            return _physAddrRange64;
259        if (_haveLPAE)
260            return 40;
261        return 32;
262    }
263
264    /** Returns the physical address mask */
265    Addr physAddrMask() const
266    {
267        return mask(physAddrRange());
268    }
269
270    /**
271     * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
272     * an invalid/empty range if disabled.
273     */
274    const AddrRange &m5opRange() const { return _m5opRange; }
275
276    /** Is Arm Semihosting support enabled? */
277    bool haveSemihosting() const { return semihosting != nullptr; }
278
279    /**
280     * Returns a valid ArmSystem pointer if using ARM ISA, it fails
281     * otherwise.
282     */
283    static ArmSystem* getArmSystem(ThreadContext *tc);
284
285    /** Returns true if the system of a specific thread context implements the
286     * Security Extensions
287     */
288    static bool haveSecurity(ThreadContext *tc);
289
290    /** Returns true if the system of a specific thread context implements the
291     * virtualization Extensions
292     */
293    static bool haveVirtualization(ThreadContext *tc);
294
295    /** Returns true if the system of a specific thread context implements the
296     * Large Physical Address Extension
297     */
298    static bool haveLPAE(ThreadContext *tc);
299
300    /** Returns true if the register width of the highest implemented exception
301     * level for the system of a specific thread context is 64 bits (ARMv8)
302     */
303    static bool highestELIs64(ThreadContext *tc);
304
305    /** Returns the highest implemented exception level for the system of a
306     * specific thread context
307     */
308    static ExceptionLevel highestEL(ThreadContext *tc);
309
310    /** Return true if the system implements a specific exception level */
311    static bool haveEL(ThreadContext *tc, ExceptionLevel el);
312
313    /** Returns the reset address if the highest implemented exception level
314     * for the system of a specific thread context is 64 bits (ARMv8)
315     */
316    static Addr resetAddr(ThreadContext *tc);
317
318    /** Returns the supported physical address range in bits for the system of a
319     * specific thread context
320     */
321    static uint8_t physAddrRange(ThreadContext *tc);
322
323    /** Returns the physical address mask for the system of a specific thread
324     * context
325     */
326    static Addr physAddrMask(ThreadContext *tc);
327
328    /** Returns true if ASID is 16 bits for the system of a specific thread
329     * context while in AArch64 (ARMv8) */
330    static bool haveLargeAsid64(ThreadContext *tc);
331
332    /** Is Arm Semihosting support enabled? */
333    static bool haveSemihosting(ThreadContext *tc);
334
335    /** Make a Semihosting call from aarch64 */
336    static uint64_t callSemihosting64(ThreadContext *tc,
337                                      uint32_t op, uint64_t param);
338
339    /** Make a Semihosting call from aarch32 */
340    static uint32_t callSemihosting32(ThreadContext *tc,
341                                      uint32_t op, uint32_t param);
342};
343
344class GenericArmSystem : public ArmSystem
345{
346  public:
347    typedef GenericArmSystemParams Params;
348    const Params *
349    params() const
350    {
351        return dynamic_cast<const Params *>(_params);
352    }
353
354    GenericArmSystem(Params *p) : ArmSystem(p) {};
355    virtual ~GenericArmSystem() {};
356
357    /**
358     * Initialise the system
359     */
360    virtual void initState();
361};
362
363#endif
364