system.hh revision 11234:c273990ed9bf 
1/*
2 * Copyright (c) 2010, 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <memory>
47#include <string>
48#include <vector>
49
50#include "kern/linux/events.hh"
51#include "params/ArmSystem.hh"
52#include "params/GenericArmSystem.hh"
53#include "sim/sim_object.hh"
54#include "sim/system.hh"
55
56class GenericTimer;
57class ThreadContext;
58
59class ArmSystem : public System
60{
61  protected:
62    /**
63     * PC based event to skip the dprink() call and emulate its
64     * functionality
65     */
66    Linux::DebugPrintkEvent *debugPrintkEvent;
67
68    /** Bootloaders */
69    std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
70
71    /**
72     * Pointer to the bootloader object
73     */
74    ObjectFile *bootldr;
75
76    /**
77     * True if this system implements the Security Extensions
78     */
79    const bool _haveSecurity;
80
81    /**
82     * True if this system implements the Large Physical Address Extension
83     */
84    const bool _haveLPAE;
85
86    /**
87     * True if this system implements the virtualization Extensions
88     */
89    const bool _haveVirtualization;
90
91    /**
92     * Pointer to the Generic Timer wrapper.
93     */
94    GenericTimer *_genericTimer;
95
96    /**
97     * True if the register width of the highest implemented exception level is
98     * 64 bits (ARMv8)
99     */
100    bool _highestELIs64;
101
102    /**
103     * Reset address if the highest implemented exception level is 64 bits
104     * (ARMv8)
105     */
106    const Addr _resetAddr64;
107
108    /**
109     * Supported physical address range in bits if the highest implemented
110     * exception level is 64 bits (ARMv8)
111     */
112    const uint8_t _physAddrRange64;
113
114    /**
115     * True if ASID is 16 bits in AArch64 (ARMv8)
116     */
117    const bool _haveLargeAsid64;
118
119  protected:
120    /**
121     * Get a boot loader that matches the kernel.
122     *
123     * @param obj Kernel binary
124     * @return Pointer to boot loader ObjectFile or nullptr if there
125     *         is no matching boot loader.
126     */
127    ObjectFile *getBootLoader(ObjectFile *const obj);
128
129  public:
130    typedef ArmSystemParams Params;
131    const Params *
132    params() const
133    {
134        return dynamic_cast<const Params *>(_params);
135    }
136
137    ArmSystem(Params *p);
138    ~ArmSystem();
139
140    /**
141     * Initialise the system
142     */
143    virtual void initState();
144
145    virtual Addr fixFuncEventAddr(Addr addr)
146    {
147        // Remove the low bit that thumb symbols have set
148        // but that aren't actually odd aligned
149        if (addr & 0x1)
150            return addr & ~1;
151        return addr;
152    }
153
154    /** true if this a multiprocessor system */
155    bool multiProc;
156
157    /** Returns true if this system implements the Security Extensions */
158    bool haveSecurity() const { return _haveSecurity; }
159
160    /** Returns true if this system implements the Large Physical Address
161     * Extension */
162    bool haveLPAE() const { return _haveLPAE; }
163
164    /** Returns true if this system implements the virtualization
165      * Extensions
166      */
167    bool haveVirtualization() const { return _haveVirtualization; }
168
169    /** Sets the pointer to the Generic Timer. */
170    void setGenericTimer(GenericTimer *generic_timer)
171    {
172        _genericTimer = generic_timer;
173    }
174
175    /** Get a pointer to the system's generic timer model */
176    GenericTimer *getGenericTimer() const { return _genericTimer; }
177
178    /** Returns true if the register width of the highest implemented exception
179     * level is 64 bits (ARMv8) */
180    bool highestELIs64() const { return _highestELIs64; }
181
182    /** Returns the highest implemented exception level */
183    ExceptionLevel highestEL() const
184    {
185        if (_haveSecurity)
186            return EL3;
187        // @todo: uncomment this to enable Virtualization
188        // if (_haveVirtualization)
189        //     return EL2;
190        return EL1;
191    }
192
193    /** Returns the reset address if the highest implemented exception level is
194     * 64 bits (ARMv8) */
195    Addr resetAddr64() const { return _resetAddr64; }
196
197    /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
198    bool haveLargeAsid64() const { return _haveLargeAsid64; }
199
200    /** Returns the supported physical address range in bits if the highest
201     * implemented exception level is 64 bits (ARMv8) */
202    uint8_t physAddrRange64() const { return _physAddrRange64; }
203
204    /** Returns the supported physical address range in bits */
205    uint8_t physAddrRange() const
206    {
207        if (_highestELIs64)
208            return _physAddrRange64;
209        if (_haveLPAE)
210            return 40;
211        return 32;
212    }
213
214    /** Returns the physical address mask */
215    Addr physAddrMask() const
216    {
217        return mask(physAddrRange());
218    }
219
220    /** Returns true if the system of a specific thread context implements the
221     * Security Extensions
222     */
223    static bool haveSecurity(ThreadContext *tc);
224
225    /** Returns true if the system of a specific thread context implements the
226     * virtualization Extensions
227     */
228    static bool haveVirtualization(ThreadContext *tc);
229
230    /** Returns true if the system of a specific thread context implements the
231     * Large Physical Address Extension
232     */
233    static bool haveLPAE(ThreadContext *tc);
234
235    /** Returns true if the register width of the highest implemented exception
236     * level for the system of a specific thread context is 64 bits (ARMv8)
237     */
238    static bool highestELIs64(ThreadContext *tc);
239
240    /** Returns the highest implemented exception level for the system of a
241     * specific thread context
242     */
243    static ExceptionLevel highestEL(ThreadContext *tc);
244
245    /** Returns the reset address if the highest implemented exception level for
246     * the system of a specific thread context is 64 bits (ARMv8)
247     */
248    static Addr resetAddr64(ThreadContext *tc);
249
250    /** Returns the supported physical address range in bits for the system of a
251     * specific thread context
252     */
253    static uint8_t physAddrRange(ThreadContext *tc);
254
255    /** Returns the physical address mask for the system of a specific thread
256     * context
257     */
258    static Addr physAddrMask(ThreadContext *tc);
259
260    /** Returns true if ASID is 16 bits for the system of a specific thread
261     * context while in AArch64 (ARMv8) */
262    static bool haveLargeAsid64(ThreadContext *tc);
263};
264
265class GenericArmSystem : public ArmSystem
266{
267  public:
268    typedef GenericArmSystemParams Params;
269    const Params *
270    params() const
271    {
272        return dynamic_cast<const Params *>(_params);
273    }
274
275    GenericArmSystem(Params *p) : ArmSystem(p) {};
276    virtual ~GenericArmSystem() {};
277
278    /**
279     * Initialise the system
280     */
281    virtual void initState();
282};
283
284#endif
285