system.hh revision 10846:751aa8add0bc 
1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_SYSTEM_HH__
44#define __ARCH_ARM_SYSTEM_HH__
45
46#include <string>
47#include <vector>
48
49#include "kern/linux/events.hh"
50#include "params/ArmSystem.hh"
51#include "params/GenericArmSystem.hh"
52#include "sim/sim_object.hh"
53#include "sim/system.hh"
54
55class GenericTimer;
56class ThreadContext;
57
58class ArmSystem : public System
59{
60  protected:
61    /**
62     * PC based event to skip the dprink() call and emulate its
63     * functionality
64     */
65    Linux::DebugPrintkEvent *debugPrintkEvent;
66
67    /**
68     * Pointer to the bootloader object
69     */
70    ObjectFile *bootldr;
71
72    /**
73     * True if this system implements the Security Extensions
74     */
75    const bool _haveSecurity;
76
77    /**
78     * True if this system implements the Large Physical Address Extension
79     */
80    const bool _haveLPAE;
81
82    /**
83     * True if this system implements the virtualization Extensions
84     */
85    const bool _haveVirtualization;
86
87    /**
88     * Pointer to the Generic Timer wrapper.
89     */
90    GenericTimer *_genericTimer;
91
92    /**
93     * True if the register width of the highest implemented exception level is
94     * 64 bits (ARMv8)
95     */
96    bool _highestELIs64;
97
98    /**
99     * Reset address if the highest implemented exception level is 64 bits
100     * (ARMv8)
101     */
102    const Addr _resetAddr64;
103
104    /**
105     * Supported physical address range in bits if the highest implemented
106     * exception level is 64 bits (ARMv8)
107     */
108    const uint8_t _physAddrRange64;
109
110    /**
111     * True if ASID is 16 bits in AArch64 (ARMv8)
112     */
113    const bool _haveLargeAsid64;
114
115  public:
116    typedef ArmSystemParams Params;
117    const Params *
118    params() const
119    {
120        return dynamic_cast<const Params *>(_params);
121    }
122
123    ArmSystem(Params *p);
124    ~ArmSystem();
125
126    /**
127     * Initialise the system
128     */
129    virtual void initState();
130
131    virtual Addr fixFuncEventAddr(Addr addr)
132    {
133        // Remove the low bit that thumb symbols have set
134        // but that aren't actually odd aligned
135        if (addr & 0x1)
136            return addr & ~1;
137        return addr;
138    }
139
140    /** true if this a multiprocessor system */
141    bool multiProc;
142
143    /** Returns true if this system implements the Security Extensions */
144    bool haveSecurity() const { return _haveSecurity; }
145
146    /** Returns true if this system implements the Large Physical Address
147     * Extension */
148    bool haveLPAE() const { return _haveLPAE; }
149
150    /** Returns true if this system implements the virtualization
151      * Extensions
152      */
153    bool haveVirtualization() const { return _haveVirtualization; }
154
155    /** Sets the pointer to the Generic Timer. */
156    void setGenericTimer(GenericTimer *generic_timer)
157    {
158        _genericTimer = generic_timer;
159    }
160
161    /** Get a pointer to the system's generic timer model */
162    GenericTimer *getGenericTimer() const { return _genericTimer; }
163
164    /** Returns true if the register width of the highest implemented exception
165     * level is 64 bits (ARMv8) */
166    bool highestELIs64() const { return _highestELIs64; }
167
168    /** Returns the highest implemented exception level */
169    ExceptionLevel highestEL() const
170    {
171        if (_haveSecurity)
172            return EL3;
173        // @todo: uncomment this to enable Virtualization
174        // if (_haveVirtualization)
175        //     return EL2;
176        return EL1;
177    }
178
179    /** Returns the reset address if the highest implemented exception level is
180     * 64 bits (ARMv8) */
181    Addr resetAddr64() const { return _resetAddr64; }
182
183    /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
184    bool haveLargeAsid64() const { return _haveLargeAsid64; }
185
186    /** Returns the supported physical address range in bits if the highest
187     * implemented exception level is 64 bits (ARMv8) */
188    uint8_t physAddrRange64() const { return _physAddrRange64; }
189
190    /** Returns the supported physical address range in bits */
191    uint8_t physAddrRange() const
192    {
193        if (_highestELIs64)
194            return _physAddrRange64;
195        if (_haveLPAE)
196            return 40;
197        return 32;
198    }
199
200    /** Returns the physical address mask */
201    Addr physAddrMask() const
202    {
203        return mask(physAddrRange());
204    }
205
206    /** Returns true if the system of a specific thread context implements the
207     * Security Extensions
208     */
209    static bool haveSecurity(ThreadContext *tc);
210
211    /** Returns true if the system of a specific thread context implements the
212     * virtualization Extensions
213     */
214    static bool haveVirtualization(ThreadContext *tc);
215
216    /** Returns true if the system of a specific thread context implements the
217     * Large Physical Address Extension
218     */
219    static bool haveLPAE(ThreadContext *tc);
220
221    /** Returns true if the register width of the highest implemented exception
222     * level for the system of a specific thread context is 64 bits (ARMv8)
223     */
224    static bool highestELIs64(ThreadContext *tc);
225
226    /** Returns the highest implemented exception level for the system of a
227     * specific thread context
228     */
229    static ExceptionLevel highestEL(ThreadContext *tc);
230
231    /** Returns the reset address if the highest implemented exception level for
232     * the system of a specific thread context is 64 bits (ARMv8)
233     */
234    static Addr resetAddr64(ThreadContext *tc);
235
236    /** Returns the supported physical address range in bits for the system of a
237     * specific thread context
238     */
239    static uint8_t physAddrRange(ThreadContext *tc);
240
241    /** Returns the physical address mask for the system of a specific thread
242     * context
243     */
244    static Addr physAddrMask(ThreadContext *tc);
245
246    /** Returns true if ASID is 16 bits for the system of a specific thread
247     * context while in AArch64 (ARMv8) */
248    static bool haveLargeAsid64(ThreadContext *tc);
249};
250
251class GenericArmSystem : public ArmSystem
252{
253  public:
254    typedef GenericArmSystemParams Params;
255    const Params *
256    params() const
257    {
258        return dynamic_cast<const Params *>(_params);
259    }
260
261    GenericArmSystem(Params *p) : ArmSystem(p) {};
262    virtual ~GenericArmSystem() {};
263
264    /**
265     * Initialise the system
266     */
267    virtual void initState();
268};
269
270#endif
271