xref: /gem5/src/arch/arm/stage2_mmu.hh

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 * Copyright (c) 2012-2013, 2015 ARM Limited
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 *
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 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
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 * modified or unmodified, in source code or in binary form.
 *
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * Authors: Thomas Grocutt
 */

#ifndef __ARCH_ARM_STAGE2_MMU_HH__
#define __ARCH_ARM_STAGE2_MMU_HH__

#include "arch/arm/faults.hh"
#include "arch/arm/tlb.hh"
#include "mem/request.hh"
#include "params/ArmStage2MMU.hh"
#include "sim/eventq.hh"

namespace ArmISA {

class Stage2MMU : public SimObject
{
  private:
    TLB *_stage1Tlb;
    /** The TLB that will cache the stage 2 look ups. */
    TLB *_stage2Tlb;

  protected:

    /** Port to issue translation requests from */
    DmaPort port;

    /** Request id for requests generated by this MMU */
    MasterID masterId;

  public:
    /** This translation class is used to trigger the data fetch once a timing
        translation returns the translated physical address */
    class Stage2Translation : public BaseTLB::Translation
    {
      private:
        uint8_t   *data;
        int       numBytes;
        Request   req;
        Event     *event;
        Stage2MMU &parent;
        Addr      oVAddr;

      public:
        Fault fault;

        Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
                          Addr _oVAddr);

        void
        markDelayed() {}

        void
        finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
               BaseTLB::Mode mode);

        void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
        {
            numBytes = size;
            req.setVirt(0, vaddr, size, flags, masterId, 0);
        }

        Fault translateTiming(ThreadContext *tc)
        {
            return (parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read));
        }
    };

    typedef ArmStage2MMUParams Params;
    Stage2MMU(const Params *p);

    /**
     * Get the port that ultimately belongs to the stage-two MMU, but
     * is used by the two table walkers, and is exposed externally and
     * connected through the stage-one table walker.
     */
    DmaPort& getPort() { return port; }

    unsigned int drain(DrainManager *dm);

    Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
        uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
    Fault readDataTimed(ThreadContext *tc, Addr descAddr,
                        Stage2Translation *translation, int numBytes,
                        Request::Flags flags);

    TLB* stage1Tlb() const { return _stage1Tlb; }
    TLB* stage2Tlb() const { return _stage2Tlb; }
};



} // namespace ArmISA

#endif //__ARCH_ARM_STAGE2_MMU_HH__