stage2_mmu.hh revision 10379
110037SARM gem5 Developers/* 210037SARM gem5 Developers * Copyright (c) 2012-2013 ARM Limited 310037SARM gem5 Developers * All rights reserved 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1410037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 1510037SARM gem5 Developers * modification, are permitted provided that the following conditions are 1610037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 1710037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 1810037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1910037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 2010037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 2110037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 2210037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 2310037SARM gem5 Developers * this software without specific prior written permission. 2410037SARM gem5 Developers * 2510037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610037SARM gem5 Developers * 3710037SARM gem5 Developers * Authors: Thomas Grocutt 3810037SARM gem5 Developers */ 3910037SARM gem5 Developers 4010037SARM gem5 Developers#ifndef __ARCH_ARM_STAGE2_MMU_HH__ 4110037SARM gem5 Developers#define __ARCH_ARM_STAGE2_MMU_HH__ 4210037SARM gem5 Developers 4310037SARM gem5 Developers#include "arch/arm/faults.hh" 4410037SARM gem5 Developers#include "arch/arm/tlb.hh" 4510037SARM gem5 Developers#include "mem/request.hh" 4610037SARM gem5 Developers#include "params/ArmStage2MMU.hh" 4710037SARM gem5 Developers#include "sim/eventq.hh" 4810037SARM gem5 Developers 4910037SARM gem5 Developersnamespace ArmISA { 5010037SARM gem5 Developers 5110037SARM gem5 Developersclass Stage2MMU : public SimObject 5210037SARM gem5 Developers{ 5310037SARM gem5 Developers private: 5410037SARM gem5 Developers TLB *_stage1Tlb; 5510037SARM gem5 Developers /** The TLB that will cache the stage 2 look ups. */ 5610037SARM gem5 Developers TLB *_stage2Tlb; 5710037SARM gem5 Developers 5810037SARM gem5 Developers public: 5910037SARM gem5 Developers /** This translation class is used to trigger the data fetch once a timing 6010037SARM gem5 Developers translation returns the translated physical address */ 6110037SARM gem5 Developers class Stage2Translation : public BaseTLB::Translation 6210037SARM gem5 Developers { 6310037SARM gem5 Developers private: 6410037SARM gem5 Developers uint8_t *data; 6510037SARM gem5 Developers int numBytes; 6610037SARM gem5 Developers Request req; 6710037SARM gem5 Developers Event *event; 6810037SARM gem5 Developers Stage2MMU &parent; 6910037SARM gem5 Developers Addr oVAddr; 7010037SARM gem5 Developers 7110037SARM gem5 Developers public: 7210037SARM gem5 Developers Fault fault; 7310037SARM gem5 Developers 7410037SARM gem5 Developers Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event, 7510037SARM gem5 Developers Addr _oVAddr); 7610037SARM gem5 Developers 7710037SARM gem5 Developers void 7810037SARM gem5 Developers markDelayed() {} 7910037SARM gem5 Developers 8010037SARM gem5 Developers void 8110379Sandreas.hansson@arm.com finish(const Fault &fault, RequestPtr req, ThreadContext *tc, 8210037SARM gem5 Developers BaseTLB::Mode mode); 8310037SARM gem5 Developers 8410037SARM gem5 Developers void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId) 8510037SARM gem5 Developers { 8610037SARM gem5 Developers numBytes = size; 8710037SARM gem5 Developers req.setVirt(0, vaddr, size, flags, masterId, 0); 8810037SARM gem5 Developers } 8910037SARM gem5 Developers 9010037SARM gem5 Developers Fault translateTiming(ThreadContext *tc) 9110037SARM gem5 Developers { 9210037SARM gem5 Developers return (parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read)); 9310037SARM gem5 Developers } 9410037SARM gem5 Developers }; 9510037SARM gem5 Developers 9610037SARM gem5 Developers typedef ArmStage2MMUParams Params; 9710037SARM gem5 Developers Stage2MMU(const Params *p); 9810037SARM gem5 Developers 9910037SARM gem5 Developers Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr, 10010037SARM gem5 Developers uint8_t *data, int numBytes, Request::Flags flags, int masterId, 10110037SARM gem5 Developers bool isFunctional); 10210037SARM gem5 Developers Fault readDataTimed(ThreadContext *tc, Addr descAddr, 10310037SARM gem5 Developers Stage2Translation *translation, int numBytes, Request::Flags flags, 10410037SARM gem5 Developers int masterId); 10510037SARM gem5 Developers 10610037SARM gem5 Developers TLB* stage1Tlb() const { return _stage1Tlb; } 10710037SARM gem5 Developers TLB* stage2Tlb() const { return _stage2Tlb; } 10810037SARM gem5 Developers}; 10910037SARM gem5 Developers 11010037SARM gem5 Developers 11110037SARM gem5 Developers 11210037SARM gem5 Developers} // namespace ArmISA 11310037SARM gem5 Developers 11410037SARM gem5 Developers#endif //__ARCH_ARM_STAGE2_MMU_HH__ 11510037SARM gem5 Developers 116