stage2_mmu.cc revision 10873:7c972b9aea16
1/* 2 * Copyright (c) 2012-2013, 2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Thomas Grocutt 38 */ 39 40#include "arch/arm/stage2_mmu.hh" 41 42#include "arch/arm/faults.hh" 43#include "arch/arm/system.hh" 44#include "arch/arm/table_walker.hh" 45#include "arch/arm/tlb.hh" 46#include "cpu/base.hh" 47#include "cpu/thread_context.hh" 48 49using namespace ArmISA; 50 51Stage2MMU::Stage2MMU(const Params *p) 52 : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb), 53 port(_stage1Tlb->getTableWalker(), p->sys), 54 masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()->name())) 55{ 56 // we use the stage-one table walker as the parent of the port, 57 // and to get our master id, this is done to keep things 58 // symmetrical with other ISAs in terms of naming and stats 59 stage1Tlb()->setMMU(this, masterId); 60 stage2Tlb()->setMMU(this, masterId); 61} 62 63Fault 64Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr, 65 uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional) 66{ 67 Fault fault; 68 69 // translate to physical address using the second stage MMU 70 Request req = Request(); 71 req.setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0); 72 if (isFunctional) { 73 fault = stage2Tlb()->translateFunctional(&req, tc, BaseTLB::Read); 74 } else { 75 fault = stage2Tlb()->translateAtomic(&req, tc, BaseTLB::Read); 76 } 77 78 // Now do the access. 79 if (fault == NoFault && !req.getFlags().isSet(Request::NO_ACCESS)) { 80 Packet pkt = Packet(&req, MemCmd::ReadReq); 81 pkt.dataStatic(data); 82 if (isFunctional) { 83 port.sendFunctional(&pkt); 84 } else { 85 port.sendAtomic(&pkt); 86 } 87 assert(!pkt.isError()); 88 } 89 90 // If there was a fault annotate it with the flag saying the foult occured 91 // while doing a translation for a stage 1 page table walk. 92 if (fault != NoFault) { 93 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 94 armFault->annotate(ArmFault::S1PTW, true); 95 armFault->annotate(ArmFault::OVA, oVAddr); 96 } 97 return fault; 98} 99 100Fault 101Stage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr, 102 Stage2Translation *translation, int numBytes, 103 Request::Flags flags) 104{ 105 Fault fault; 106 // translate to physical address using the second stage MMU 107 translation->setVirt(descAddr, numBytes, flags | Request::PT_WALK, masterId); 108 fault = translation->translateTiming(tc); 109 return fault; 110} 111 112Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent, 113 uint8_t *_data, Event *_event, Addr _oVAddr) 114 : data(_data), numBytes(0), event(_event), parent(_parent), oVAddr(_oVAddr), 115 fault(NoFault) 116{ 117} 118 119void 120Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req, 121 ThreadContext *tc, BaseTLB::Mode mode) 122{ 123 fault = _fault; 124 125 // If there was a fault annotate it with the flag saying the foult occured 126 // while doing a translation for a stage 1 page table walk. 127 if (fault != NoFault) { 128 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 129 armFault->annotate(ArmFault::S1PTW, true); 130 armFault->annotate(ArmFault::OVA, oVAddr); 131 } 132 133 if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 134 parent.getPort().dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes, 135 event, data, tc->getCpuPtr()->clockPeriod(), 136 req->getFlags()); 137 } else { 138 // We can't do the DMA access as there's been a problem, so tell the 139 // event we're done 140 event->process(); 141 } 142} 143 144unsigned int 145Stage2MMU::drain(DrainManager *dm) 146{ 147 return port.drain(dm); 148} 149 150ArmISA::Stage2MMU * 151ArmStage2MMUParams::create() 152{ 153 return new ArmISA::Stage2MMU(this); 154} 155