stage2_mmu.cc revision 10717:4f8c1bd6fdb8 
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grocutt
38 */
39
40#include "arch/arm/stage2_mmu.hh"
41#include "arch/arm/faults.hh"
42#include "arch/arm/system.hh"
43#include "arch/arm/table_walker.hh"
44#include "arch/arm/tlb.hh"
45#include "cpu/base.hh"
46#include "cpu/thread_context.hh"
47
48using namespace ArmISA;
49
50Stage2MMU::Stage2MMU(const Params *p)
51    : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
52      port(_stage1Tlb->getTableWalker(), p->sys),
53      masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()->name()))
54{
55    // we use the stage-one table walker as the parent of the port,
56    // and to get our master id, this is done to keep things
57    // symmetrical with other ISAs in terms of naming and stats
58    stage1Tlb()->setMMU(this, masterId);
59    stage2Tlb()->setMMU(this, masterId);
60}
61
62Fault
63Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
64    uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional)
65{
66    Fault fault;
67
68    // translate to physical address using the second stage MMU
69    Request req = Request();
70    req.setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0);
71    if (isFunctional) {
72        fault = stage2Tlb()->translateFunctional(&req, tc, BaseTLB::Read);
73    } else {
74        fault = stage2Tlb()->translateAtomic(&req, tc, BaseTLB::Read);
75    }
76
77    // Now do the access.
78    if (fault == NoFault && !req.getFlags().isSet(Request::NO_ACCESS)) {
79        Packet pkt = Packet(&req, MemCmd::ReadReq);
80        pkt.dataStatic(data);
81        if (isFunctional) {
82            port.sendFunctional(&pkt);
83        } else {
84            port.sendAtomic(&pkt);
85        }
86        assert(!pkt.isError());
87    }
88
89    // If there was a fault annotate it with the flag saying the foult occured
90    // while doing a translation for a stage 1 page table walk.
91    if (fault != NoFault) {
92        ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
93        armFault->annotate(ArmFault::S1PTW, true);
94        armFault->annotate(ArmFault::OVA, oVAddr);
95    }
96    return fault;
97}
98
99Fault
100Stage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr,
101                         Stage2Translation *translation, int numBytes,
102                         Request::Flags flags)
103{
104    Fault fault;
105    // translate to physical address using the second stage MMU
106    translation->setVirt(descAddr, numBytes, flags | Request::PT_WALK, masterId);
107    fault = translation->translateTiming(tc);
108    return fault;
109}
110
111Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent,
112        uint8_t *_data, Event *_event, Addr _oVAddr)
113    : data(_data), numBytes(0), event(_event), parent(_parent), oVAddr(_oVAddr),
114    fault(NoFault)
115{
116}
117
118void
119Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req,
120                                     ThreadContext *tc, BaseTLB::Mode mode)
121{
122    fault = _fault;
123
124    // If there was a fault annotate it with the flag saying the foult occured
125    // while doing a translation for a stage 1 page table walk.
126    if (fault != NoFault) {
127        ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
128        armFault->annotate(ArmFault::S1PTW, true);
129        armFault->annotate(ArmFault::OVA, oVAddr);
130    }
131
132    if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
133        parent.getPort().dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes,
134                                   event, data, tc->getCpuPtr()->clockPeriod(),
135                                   req->getFlags());
136    } else {
137        // We can't do the DMA access as there's been a problem, so tell the
138        // event we're done
139        event->process();
140    }
141}
142
143unsigned int
144Stage2MMU::drain(DrainManager *dm)
145{
146    return port.drain(dm);
147}
148
149ArmISA::Stage2MMU *
150ArmStage2MMUParams::create()
151{
152    return new ArmISA::Stage2MMU(this);
153}
154