stage2_mmu.cc revision 10717
110037SARM gem5 Developers/* 210717Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015 ARM Limited 310037SARM gem5 Developers * All rights reserved 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1410037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 1510037SARM gem5 Developers * modification, are permitted provided that the following conditions are 1610037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 1710037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 1810037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1910037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 2010037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 2110037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 2210037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 2310037SARM gem5 Developers * this software without specific prior written permission. 2410037SARM gem5 Developers * 2510037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610037SARM gem5 Developers * 3710037SARM gem5 Developers * Authors: Thomas Grocutt 3810037SARM gem5 Developers */ 3910037SARM gem5 Developers 4010717Sandreas.hansson@arm.com#include "arch/arm/stage2_mmu.hh" 4110037SARM gem5 Developers#include "arch/arm/faults.hh" 4210037SARM gem5 Developers#include "arch/arm/system.hh" 4310717Sandreas.hansson@arm.com#include "arch/arm/table_walker.hh" 4410037SARM gem5 Developers#include "arch/arm/tlb.hh" 4510037SARM gem5 Developers#include "cpu/base.hh" 4610037SARM gem5 Developers#include "cpu/thread_context.hh" 4710037SARM gem5 Developers 4810037SARM gem5 Developersusing namespace ArmISA; 4910037SARM gem5 Developers 5010037SARM gem5 DevelopersStage2MMU::Stage2MMU(const Params *p) 5110717Sandreas.hansson@arm.com : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb), 5210717Sandreas.hansson@arm.com port(_stage1Tlb->getTableWalker(), p->sys), 5310717Sandreas.hansson@arm.com masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()->name())) 5410037SARM gem5 Developers{ 5510717Sandreas.hansson@arm.com // we use the stage-one table walker as the parent of the port, 5610717Sandreas.hansson@arm.com // and to get our master id, this is done to keep things 5710717Sandreas.hansson@arm.com // symmetrical with other ISAs in terms of naming and stats 5810717Sandreas.hansson@arm.com stage1Tlb()->setMMU(this, masterId); 5910717Sandreas.hansson@arm.com stage2Tlb()->setMMU(this, masterId); 6010037SARM gem5 Developers} 6110037SARM gem5 Developers 6210037SARM gem5 DevelopersFault 6310037SARM gem5 DevelopersStage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr, 6410717Sandreas.hansson@arm.com uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional) 6510037SARM gem5 Developers{ 6610037SARM gem5 Developers Fault fault; 6710037SARM gem5 Developers 6810037SARM gem5 Developers // translate to physical address using the second stage MMU 6910037SARM gem5 Developers Request req = Request(); 7010037SARM gem5 Developers req.setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0); 7110037SARM gem5 Developers if (isFunctional) { 7210037SARM gem5 Developers fault = stage2Tlb()->translateFunctional(&req, tc, BaseTLB::Read); 7310037SARM gem5 Developers } else { 7410037SARM gem5 Developers fault = stage2Tlb()->translateAtomic(&req, tc, BaseTLB::Read); 7510037SARM gem5 Developers } 7610037SARM gem5 Developers 7710037SARM gem5 Developers // Now do the access. 7810037SARM gem5 Developers if (fault == NoFault && !req.getFlags().isSet(Request::NO_ACCESS)) { 7910037SARM gem5 Developers Packet pkt = Packet(&req, MemCmd::ReadReq); 8010037SARM gem5 Developers pkt.dataStatic(data); 8110037SARM gem5 Developers if (isFunctional) { 8210717Sandreas.hansson@arm.com port.sendFunctional(&pkt); 8310037SARM gem5 Developers } else { 8410717Sandreas.hansson@arm.com port.sendAtomic(&pkt); 8510037SARM gem5 Developers } 8610037SARM gem5 Developers assert(!pkt.isError()); 8710037SARM gem5 Developers } 8810037SARM gem5 Developers 8910037SARM gem5 Developers // If there was a fault annotate it with the flag saying the foult occured 9010037SARM gem5 Developers // while doing a translation for a stage 1 page table walk. 9110037SARM gem5 Developers if (fault != NoFault) { 9210037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 9310037SARM gem5 Developers armFault->annotate(ArmFault::S1PTW, true); 9410037SARM gem5 Developers armFault->annotate(ArmFault::OVA, oVAddr); 9510037SARM gem5 Developers } 9610037SARM gem5 Developers return fault; 9710037SARM gem5 Developers} 9810037SARM gem5 Developers 9910037SARM gem5 DevelopersFault 10010037SARM gem5 DevelopersStage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr, 10110717Sandreas.hansson@arm.com Stage2Translation *translation, int numBytes, 10210717Sandreas.hansson@arm.com Request::Flags flags) 10310037SARM gem5 Developers{ 10410037SARM gem5 Developers Fault fault; 10510037SARM gem5 Developers // translate to physical address using the second stage MMU 10610037SARM gem5 Developers translation->setVirt(descAddr, numBytes, flags | Request::PT_WALK, masterId); 10710037SARM gem5 Developers fault = translation->translateTiming(tc); 10810037SARM gem5 Developers return fault; 10910037SARM gem5 Developers} 11010037SARM gem5 Developers 11110037SARM gem5 DevelopersStage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent, 11210037SARM gem5 Developers uint8_t *_data, Event *_event, Addr _oVAddr) 11310537Sandreas.hansson@arm.com : data(_data), numBytes(0), event(_event), parent(_parent), oVAddr(_oVAddr), 11410037SARM gem5 Developers fault(NoFault) 11510037SARM gem5 Developers{ 11610037SARM gem5 Developers} 11710037SARM gem5 Developers 11810037SARM gem5 Developersvoid 11910379Sandreas.hansson@arm.comStage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req, 12010379Sandreas.hansson@arm.com ThreadContext *tc, BaseTLB::Mode mode) 12110037SARM gem5 Developers{ 12210037SARM gem5 Developers fault = _fault; 12310037SARM gem5 Developers 12410037SARM gem5 Developers // If there was a fault annotate it with the flag saying the foult occured 12510037SARM gem5 Developers // while doing a translation for a stage 1 page table walk. 12610037SARM gem5 Developers if (fault != NoFault) { 12710037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 12810037SARM gem5 Developers armFault->annotate(ArmFault::S1PTW, true); 12910037SARM gem5 Developers armFault->annotate(ArmFault::OVA, oVAddr); 13010037SARM gem5 Developers } 13110037SARM gem5 Developers 13210037SARM gem5 Developers if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 13310717Sandreas.hansson@arm.com parent.getPort().dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes, 13410717Sandreas.hansson@arm.com event, data, tc->getCpuPtr()->clockPeriod(), 13510717Sandreas.hansson@arm.com req->getFlags()); 13610037SARM gem5 Developers } else { 13710037SARM gem5 Developers // We can't do the DMA access as there's been a problem, so tell the 13810037SARM gem5 Developers // event we're done 13910037SARM gem5 Developers event->process(); 14010037SARM gem5 Developers } 14110037SARM gem5 Developers} 14210037SARM gem5 Developers 14310717Sandreas.hansson@arm.comunsigned int 14410717Sandreas.hansson@arm.comStage2MMU::drain(DrainManager *dm) 14510717Sandreas.hansson@arm.com{ 14610717Sandreas.hansson@arm.com return port.drain(dm); 14710717Sandreas.hansson@arm.com} 14810717Sandreas.hansson@arm.com 14910037SARM gem5 DevelopersArmISA::Stage2MMU * 15010037SARM gem5 DevelopersArmStage2MMUParams::create() 15110037SARM gem5 Developers{ 15210037SARM gem5 Developers return new ArmISA::Stage2MMU(this); 15310037SARM gem5 Developers} 154