stacktrace.hh revision 6757
15794SN/A/* 28841SN/A * Copyright (c) 2005 The Regents of The University of Michigan 38841SN/A * All rights reserved. 48841SN/A * 58841SN/A * Redistribution and use in source and binary forms, with or without 68841SN/A * modification, are permitted provided that the following conditions are 78841SN/A * met: redistributions of source code must retain the above copyright 88841SN/A * notice, this list of conditions and the following disclaimer; 98841SN/A * redistributions in binary form must reproduce the above copyright 108841SN/A * notice, this list of conditions and the following disclaimer in the 118841SN/A * documentation and/or other materials provided with the distribution; 128841SN/A * neither the name of the copyright holders nor the names of its 138841SN/A * contributors may be used to endorse or promote products derived from 145794SN/A * this software without specific prior written permission. 155794SN/A * 165794SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175794SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185794SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195794SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205794SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215794SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225794SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235794SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245794SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255794SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265794SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275794SN/A * 285794SN/A * Authors: Nathan Binkert 295794SN/A */ 305794SN/A 315794SN/A#ifndef __ARCH_ARM_STACKTRACE_HH__ 325794SN/A#define __ARCH_ARM_STACKTRACE_HH__ 335794SN/A 345794SN/A#include "base/trace.hh" 355794SN/A#include "cpu/static_inst.hh" 365794SN/A 375794SN/Aclass ThreadContext; 385794SN/Anamespace ArmISA 395794SN/A{ 405794SN/A 415794SN/Aclass StackTrace; 425794SN/A 435794SN/Aclass ProcessInfo 445794SN/A{ 455794SN/A private: 465794SN/A ThreadContext *tc; 4711261Sandreas.sandberg@arm.com 4811261Sandreas.sandberg@arm.com int thread_info_size; 495794SN/A int task_struct_size; 505794SN/A int task_off; 515954SN/A int pid_off; 525794SN/A int name_off; 538232SN/A 549152SN/A public: 555794SN/A ProcessInfo(ThreadContext *_tc); 565794SN/A 575794SN/A Addr task(Addr ksp) const; 585794SN/A int pid(Addr ksp) const; 595794SN/A std::string name(Addr ksp) const; 605794SN/A}; 615794SN/A 625794SN/Aclass StackTrace 635794SN/A{ 649807SN/A protected: 655794SN/A typedef ArmISA::MachInst MachInst; 665794SN/A private: 675794SN/A ThreadContext *tc; 685794SN/A std::vector<Addr> stack; 695794SN/A 705794SN/A private: 715794SN/A bool isEntry(Addr addr); 725794SN/A bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra); 735794SN/A bool decodeSave(MachInst inst, int ®, int &disp); 745794SN/A bool decodeStack(MachInst inst, int &disp); 755794SN/A 765794SN/A void trace(ThreadContext *tc, bool is_call); 775794SN/A 785794SN/A public: 795794SN/A StackTrace(); 805794SN/A StackTrace(ThreadContext *tc, StaticInstPtr inst); 815794SN/A ~StackTrace(); 829165SN/A 838851SN/A void clear() 845794SN/A { 855794SN/A tc = 0; 8610913SN/A stack.clear(); 875794SN/A } 885794SN/A 895794SN/A bool valid() const { return tc != NULL; } 905794SN/A bool trace(ThreadContext *tc, StaticInstPtr inst); 915794SN/A 925794SN/A public: 935794SN/A const std::vector<Addr> &getstack() const { return stack; } 945794SN/A 955794SN/A#if TRACING_ON 965794SN/A private: 975794SN/A void dump(); 985794SN/A 995794SN/A public: 1005794SN/A void dprintf() { if (DTRACE(Stack)) dump(); } 1015794SN/A#else 1025794SN/A public: 1035794SN/A void dprintf() {} 1045794SN/A#endif 1055794SN/A}; 1065794SN/A 1075794SN/Ainline bool 1085794SN/AStackTrace::trace(ThreadContext *tc, StaticInstPtr inst) 1095794SN/A{ 1105794SN/A if (!inst->isCall() && !inst->isReturn()) 1115794SN/A return false; 1125794SN/A 1135794SN/A if (valid()) 1149294SN/A clear(); 1159294SN/A 1165794SN/A trace(tc, !inst->isReturn()); 1178922SN/A return true; 1188922SN/A} 1199807SN/A 1208922SN/A} // Namespace ArmISA 1218922SN/A 1228922SN/A#endif // __ARCH_ARM_STACKTRACE_HH__ 1238922SN/A