remote_gdb.cc revision 10037:5cac77888310
12292SN/A/* 27597Sminkyu.jeong@arm.com * Copyright (c) 2010, 2013 ARM Limited 37597Sminkyu.jeong@arm.com * All rights reserved 47597Sminkyu.jeong@arm.com * 57597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137597Sminkyu.jeong@arm.com * 142292SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152292SN/A * All rights reserved. 162292SN/A * 172292SN/A * Redistribution and use in source and binary forms, with or without 182292SN/A * modification, are permitted provided that the following conditions are 192292SN/A * met: redistributions of source code must retain the above copyright 202292SN/A * notice, this list of conditions and the following disclaimer; 212292SN/A * redistributions in binary form must reproduce the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer in the 232292SN/A * documentation and/or other materials provided with the distribution; 242292SN/A * neither the name of the copyright holders nor the names of its 252292SN/A * contributors may be used to endorse or promote products derived from 262292SN/A * this software without specific prior written permission. 272292SN/A * 282292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Nathan Binkert 412689Sktlim@umich.edu * William Wang 422292SN/A */ 432292SN/A 443326Sktlim@umich.edu/* 456658Snate@binkert.org * Copyright (c) 1990, 1993 The Regents of the University of California 462733Sktlim@umich.edu * All rights reserved 472907Sktlim@umich.edu * 482292SN/A * This software was developed by the Computer Systems Engineering group 492292SN/A * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 502722Sktlim@umich.edu * contributed to Berkeley. 512669Sktlim@umich.edu * 522292SN/A * All advertising materials mentioning features or use of this software 532790Sktlim@umich.edu * must display the following acknowledgement: 542790Sktlim@umich.edu * This product includes software developed by the University of 552790Sktlim@umich.edu * California, Lawrence Berkeley Laboratories. 562790Sktlim@umich.edu * 572669Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 582678Sktlim@umich.edu * modification, are permitted provided that the following conditions 592678Sktlim@umich.edu * are met: 605606Snate@binkert.org * 1. Redistributions of source code must retain the above copyright 612292SN/A * notice, this list of conditions and the following disclaimer. 622678Sktlim@umich.edu * 2. Redistributions in binary form must reproduce the above copyright 632292SN/A * notice, this list of conditions and the following disclaimer in the 642292SN/A * documentation and/or other materials provided with the distribution. 652669Sktlim@umich.edu * 3. All advertising materials mentioning features or use of this software 662292SN/A * must display the following acknowledgement: 672678Sktlim@umich.edu * This product includes software developed by the University of 682292SN/A * California, Berkeley and its contributors. 692678Sktlim@umich.edu * 4. Neither the name of the University nor the names of its contributors 702678Sktlim@umich.edu * may be used to endorse or promote products derived from this software 712678Sktlim@umich.edu * without specific prior written permission. 724319Sktlim@umich.edu * 734319Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 744319Sktlim@umich.edu * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 754319Sktlim@umich.edu * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 764319Sktlim@umich.edu * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 772678Sktlim@umich.edu * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 782678Sktlim@umich.edu * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 792292SN/A * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 802678Sktlim@umich.edu * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 812678Sktlim@umich.edu * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 825336Shines@cs.fsu.edu * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 832678Sktlim@umich.edu * SUCH DAMAGE. 844873Sstever@eecs.umich.edu * 852678Sktlim@umich.edu * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94 862292SN/A */ 872678Sktlim@umich.edu 882678Sktlim@umich.edu/*- 892678Sktlim@umich.edu * Copyright (c) 2001 The NetBSD Foundation, Inc. 902678Sktlim@umich.edu * All rights reserved. 912678Sktlim@umich.edu * 922678Sktlim@umich.edu * This code is derived from software contributed to The NetBSD Foundation 932678Sktlim@umich.edu * by Jason R. Thorpe. 942698Sktlim@umich.edu * 952344SN/A * Redistribution and use in source and binary forms, with or without 962678Sktlim@umich.edu * modification, are permitted provided that the following conditions 972678Sktlim@umich.edu * are met: 984986Ssaidi@eecs.umich.edu * 1. Redistributions of source code must retain the above copyright 994986Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer. 1006974Stjones1@inf.ed.ac.uk * 2. Redistributions in binary form must reproduce the above copyright 1016974Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 1026974Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution. 1036974Stjones1@inf.ed.ac.uk * 3. All advertising materials mentioning features or use of this software 1046974Stjones1@inf.ed.ac.uk * must display the following acknowledgement: 1056974Stjones1@inf.ed.ac.uk * This product includes software developed by the NetBSD 1066974Stjones1@inf.ed.ac.uk * Foundation, Inc. and its contributors. 1072678Sktlim@umich.edu * 4. Neither the name of The NetBSD Foundation nor the names of its 1082820Sktlim@umich.edu * contributors may be used to endorse or promote products derived 1092678Sktlim@umich.edu * from this software without specific prior written permission. 1102678Sktlim@umich.edu * 1116974Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 1126974Stjones1@inf.ed.ac.uk * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 1136974Stjones1@inf.ed.ac.uk * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 1146974Stjones1@inf.ed.ac.uk * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 1156974Stjones1@inf.ed.ac.uk * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 1166974Stjones1@inf.ed.ac.uk * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 1172678Sktlim@umich.edu * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 1182678Sktlim@umich.edu * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 1192678Sktlim@umich.edu * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 1202678Sktlim@umich.edu * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 1212678Sktlim@umich.edu * POSSIBILITY OF SUCH DAMAGE. 1222344SN/A */ 1232307SN/A 1246974Stjones1@inf.ed.ac.uk/* 1256974Stjones1@inf.ed.ac.uk * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $ 1266974Stjones1@inf.ed.ac.uk * 1276974Stjones1@inf.ed.ac.uk * Taken from NetBSD 1282678Sktlim@umich.edu * 1294032Sktlim@umich.edu * "Stub" to allow remote cpu to debug over a serial line using gdb. 1302678Sktlim@umich.edu */ 1312292SN/A 1322292SN/A#include <sys/signal.h> 1332292SN/A#include <unistd.h> 1342292SN/A 1352678Sktlim@umich.edu#include <string> 1362678Sktlim@umich.edu 1376974Stjones1@inf.ed.ac.uk#include "arch/arm/decoder.hh" 1382292SN/A#include "arch/arm/pagetable.hh" 1392292SN/A#include "arch/arm/registers.hh" 1402292SN/A#include "arch/arm/remote_gdb.hh" 1412292SN/A#include "arch/arm/system.hh" 1422292SN/A#include "arch/arm/utility.hh" 1435529Snate@binkert.org#include "arch/arm/vtophys.hh" 1445529Snate@binkert.org#include "base/intmath.hh" 1455529Snate@binkert.org#include "base/remote_gdb.hh" 1462292SN/A#include "base/socket.hh" 1474329Sktlim@umich.edu#include "base/trace.hh" 1484329Sktlim@umich.edu#include "cpu/static_inst.hh" 1494329Sktlim@umich.edu#include "cpu/thread_context.hh" 1504329Sktlim@umich.edu#include "cpu/thread_state.hh" 1512292SN/A#include "debug/GDBAcc.hh" 1522307SN/A#include "debug/GDBMisc.hh" 1532307SN/A#include "mem/page_table.hh" 1542907Sktlim@umich.edu#include "mem/physical.hh" 1552907Sktlim@umich.edu#include "mem/port.hh" 1562292SN/A#include "sim/full_system.hh" 1572292SN/A#include "sim/system.hh" 1582329SN/A 1592329SN/Ausing namespace std; 1602329SN/Ausing namespace ArmISA; 1612292SN/A 1622292SN/ARemoteGDB::RemoteGDB(System *_system, ThreadContext *tc) 1632292SN/A : BaseRemoteGDB(_system, tc, MAX_NUMREGS) 1642292SN/A{ 1652292SN/A} 1662292SN/A 1672292SN/A/* 1682292SN/A * Determine if the mapping at va..(va+len) is valid. 1692292SN/A */ 1702292SN/Abool 1712292SN/ARemoteGDB::acc(Addr va, size_t len) 1723492Sktlim@umich.edu{ 1732329SN/A if (FullSystem) { 1742292SN/A Addr last_va; 1752292SN/A va = truncPage(va); 1762292SN/A last_va = roundPage(va + len); 1772292SN/A 1782292SN/A do { 1792292SN/A if (virtvalid(context, va)) { 1802292SN/A return true; 1812292SN/A } 1822292SN/A va += PageBytes; 1832292SN/A } while (va < last_va); 1842292SN/A 1852292SN/A DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); 1862292SN/A return true; 1872292SN/A } else { 1882292SN/A TlbEntry entry; 1892292SN/A //Check to make sure the first byte is mapped into the processes address 1902292SN/A //space. 1912727Sktlim@umich.edu if (context->getProcessPtr()->pTable->lookup(va, entry)) 1922727Sktlim@umich.edu return true; 1932727Sktlim@umich.edu return false; 1942727Sktlim@umich.edu } 1952727Sktlim@umich.edu} 1962727Sktlim@umich.edu 1972727Sktlim@umich.edu/* 1982727Sktlim@umich.edu * Translate the kernel debugger register format into the GDB register 1992727Sktlim@umich.edu * format. 2002727Sktlim@umich.edu */ 2012727Sktlim@umich.eduvoid 2022727Sktlim@umich.eduRemoteGDB::getregs() 2032727Sktlim@umich.edu{ 2042727Sktlim@umich.edu DPRINTF(GDBAcc, "getregs in remotegdb \n"); 2052727Sktlim@umich.edu 2062727Sktlim@umich.edu memset(gdbregs.regs, 0, gdbregs.bytes()); 2072727Sktlim@umich.edu 2082727Sktlim@umich.edu if (inAArch64(context)) { // AArch64 2092361SN/A // x0-x31 2102361SN/A for (int i = 0; i < 32; ++i) { 2112361SN/A gdbregs.regs[REG_X0 + i] = context->readIntReg(INTREG_X0 + i); 2122361SN/A } 2132727Sktlim@umich.edu // pc 2142727Sktlim@umich.edu gdbregs.regs[REG_PC_64] = context->pcState().pc(); 2152727Sktlim@umich.edu // cpsr 2162727Sktlim@umich.edu gdbregs.regs[REG_CPSR_64] = context->readMiscRegNoEffect(MISCREG_CPSR); 2172727Sktlim@umich.edu // v0-v31 2182727Sktlim@umich.edu for (int i = 0; i < 32; ++i) { 2192727Sktlim@umich.edu gdbregs.regs[REG_V0 + 2 * i] = static_cast<uint64_t>( 2202727Sktlim@umich.edu context->readFloatRegBits(i * 4 + 3)) << 32 | 2212727Sktlim@umich.edu context->readFloatRegBits(i * 4 + 2); 2222727Sktlim@umich.edu gdbregs.regs[REG_V0 + 2 * i + 1] = static_cast<uint64_t>( 2232727Sktlim@umich.edu context->readFloatRegBits(i * 4 + 1)) << 32 | 2242727Sktlim@umich.edu context->readFloatRegBits(i * 4 + 0); 2252727Sktlim@umich.edu } 2262727Sktlim@umich.edu } else { // AArch32 2272727Sktlim@umich.edu // R0-R15 supervisor mode 2282727Sktlim@umich.edu // arm registers are 32 bits wide, gdb registers are 64 bits wide two 2292727Sktlim@umich.edu // arm registers are packed into one gdb register (little endian) 2302727Sktlim@umich.edu gdbregs.regs[REG_R0 + 0] = context->readIntReg(INTREG_R1) << 32 | 2312727Sktlim@umich.edu context->readIntReg(INTREG_R0); 2322727Sktlim@umich.edu gdbregs.regs[REG_R0 + 1] = context->readIntReg(INTREG_R3) << 32 | 2332727Sktlim@umich.edu context->readIntReg(INTREG_R2); 2342727Sktlim@umich.edu gdbregs.regs[REG_R0 + 2] = context->readIntReg(INTREG_R5) << 32 | 2352727Sktlim@umich.edu context->readIntReg(INTREG_R4); 2364329Sktlim@umich.edu gdbregs.regs[REG_R0 + 3] = context->readIntReg(INTREG_R7) << 32 | 2374329Sktlim@umich.edu context->readIntReg(INTREG_R6); 2384329Sktlim@umich.edu gdbregs.regs[REG_R0 + 4] = context->readIntReg(INTREG_R9) << 32 | 2394329Sktlim@umich.edu context->readIntReg(INTREG_R8); 2404329Sktlim@umich.edu gdbregs.regs[REG_R0 + 5] = context->readIntReg(INTREG_R11) << 32| 2414329Sktlim@umich.edu context->readIntReg(INTREG_R10); 2424329Sktlim@umich.edu gdbregs.regs[REG_R0 + 6] = context->readIntReg(INTREG_SP) << 32 | 2434329Sktlim@umich.edu context->readIntReg(INTREG_R12); 2444329Sktlim@umich.edu gdbregs.regs[REG_R0 + 7] = context->pcState().pc() << 32 | 2454329Sktlim@umich.edu context->readIntReg(INTREG_LR); 2464329Sktlim@umich.edu 2474329Sktlim@umich.edu // CPSR 2484329Sktlim@umich.edu gdbregs.regs[REG_CPSR] = context->readMiscRegNoEffect(MISCREG_CPSR); 2492292SN/A 2502292SN/A // vfpv3/neon floating point registers (32 double or 64 float) 2512292SN/A 2522292SN/A gdbregs.regs[REG_F0] = 2532292SN/A static_cast<uint64_t>(context->readFloatRegBits(0)) << 32 | 2542292SN/A gdbregs.regs[REG_CPSR]; 2552292SN/A 2562292SN/A for (int i = 1; i < (NumFloatV7ArchRegs>>1); ++i) { 2572292SN/A gdbregs.regs[i + REG_F0] = 2582292SN/A static_cast<uint64_t>(context->readFloatRegBits(2*i)) << 32 | 2592292SN/A context->readFloatRegBits(2*i-1); 2602292SN/A } 2612292SN/A 2622292SN/A // FPSCR 2632307SN/A gdbregs.regs[REG_FPSCR] = static_cast<uint64_t>( 2642307SN/A context->readMiscRegNoEffect(MISCREG_FPSCR)) << 32 | 2652307SN/A context->readFloatRegBits(NumFloatV7ArchRegs - 1); 2662367SN/A } 2672367SN/A} 2682307SN/A 2692367SN/A/* 2702307SN/A * Translate the GDB register format into the kernel debugger register 2712329SN/A * format. 2722307SN/A */ 2732307SN/Avoid 2742307SN/ARemoteGDB::setregs() 2752307SN/A{ 2762307SN/A 2772307SN/A DPRINTF(GDBAcc, "setregs in remotegdb \n"); 2782307SN/A if (inAArch64(context)) { // AArch64 2792307SN/A // x0-x31 2802307SN/A for (int i = 0; i < 32; ++i) { 2812307SN/A context->setIntReg(INTREG_X0 + i, gdbregs.regs[REG_X0 + i]); 2822307SN/A } 2832307SN/A // pc 2842307SN/A context->pcState(gdbregs.regs[REG_PC_64]); 2852307SN/A // cpsr 2862307SN/A context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR_64]); 2872329SN/A // v0-v31 2882307SN/A for (int i = 0; i < 32; ++i) { 2892307SN/A context->setFloatRegBits(i * 4 + 3, 2902307SN/A gdbregs.regs[REG_V0 + 2 * i] >> 32); 2912307SN/A context->setFloatRegBits(i * 4 + 2, 2922307SN/A gdbregs.regs[REG_V0 + 2 * i]); 2932307SN/A context->setFloatRegBits(i * 4 + 1, 2942307SN/A gdbregs.regs[REG_V0 + 2 * i + 1] >> 32); 2952307SN/A context->setFloatRegBits(i * 4 + 0, 2962307SN/A gdbregs.regs[REG_V0 + 2 * i + 1]); 2972307SN/A } 2982292SN/A } else { // AArch32 2992292SN/A // R0-R15 supervisor mode 3002329SN/A // arm registers are 32 bits wide, gdb registers are 64 bits wide 3012329SN/A // two arm registers are packed into one gdb register (little endian) 3022292SN/A context->setIntReg(INTREG_R0 , bits(gdbregs.regs[REG_R0 + 0], 31, 0)); 3032329SN/A context->setIntReg(INTREG_R1 , bits(gdbregs.regs[REG_R0 + 0], 63, 32)); 3042329SN/A context->setIntReg(INTREG_R2 , bits(gdbregs.regs[REG_R0 + 1], 31, 0)); 3052292SN/A context->setIntReg(INTREG_R3 , bits(gdbregs.regs[REG_R0 + 1], 63, 32)); 3062292SN/A context->setIntReg(INTREG_R4 , bits(gdbregs.regs[REG_R0 + 2], 31, 0)); 3072292SN/A context->setIntReg(INTREG_R5 , bits(gdbregs.regs[REG_R0 + 2], 63, 32)); 3082292SN/A context->setIntReg(INTREG_R6 , bits(gdbregs.regs[REG_R0 + 3], 31, 0)); 3092292SN/A context->setIntReg(INTREG_R7 , bits(gdbregs.regs[REG_R0 + 3], 63, 32)); 3102329SN/A context->setIntReg(INTREG_R8 , bits(gdbregs.regs[REG_R0 + 4], 31, 0)); 3112292SN/A context->setIntReg(INTREG_R9 , bits(gdbregs.regs[REG_R0 + 4], 63, 32)); 3122292SN/A context->setIntReg(INTREG_R10, bits(gdbregs.regs[REG_R0 + 5], 31, 0)); 3132292SN/A context->setIntReg(INTREG_R11, bits(gdbregs.regs[REG_R0 + 5], 63, 32)); 3142292SN/A context->setIntReg(INTREG_R12, bits(gdbregs.regs[REG_R0 + 6], 31, 0)); 3152292SN/A context->setIntReg(INTREG_SP , bits(gdbregs.regs[REG_R0 + 6], 63, 32)); 3162292SN/A context->setIntReg(INTREG_LR , bits(gdbregs.regs[REG_R0 + 7], 31, 0)); 3172292SN/A context->pcState(bits(gdbregs.regs[REG_R0 + 7], 63, 32)); 3182292SN/A 3192329SN/A //CPSR 3202329SN/A context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR]); 3212329SN/A 3222292SN/A //vfpv3/neon floating point registers (32 double or 64 float) 3232292SN/A context->setFloatRegBits(0, gdbregs.regs[REG_F0]>>32); 3242292SN/A 3252292SN/A for (int i = 1; i < NumFloatV7ArchRegs; ++i) { 3262292SN/A if (i%2) { 3272329SN/A int j = (i+1)/2; 3282292SN/A context->setFloatRegBits(i, bits(gdbregs.regs[j + REG_F0], 31, 0)); 3292292SN/A } else { 3302292SN/A int j = i/2; 3312292SN/A context->setFloatRegBits(i, gdbregs.regs[j + REG_F0]>>32); 3322292SN/A } 3332292SN/A } 3342292SN/A 3352292SN/A //FPSCR 3362292SN/A context->setMiscReg(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32); 3372292SN/A } 3382292SN/A} 3392292SN/A 3402292SN/Avoid 3412292SN/ARemoteGDB::clearSingleStep() 3422292SN/A{ 3432292SN/A DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n", 3442292SN/A takenBkpt, notTakenBkpt); 3452292SN/A 3462292SN/A if (takenBkpt != 0) 3472292SN/A clearTempBreakpoint(takenBkpt); 3482292SN/A 3492292SN/A if (notTakenBkpt != 0) 3502292SN/A clearTempBreakpoint(notTakenBkpt); 3512292SN/A} 3522329SN/A 3532329SN/Avoid 3542292SN/ARemoteGDB::setSingleStep() 3557720Sgblack@eecs.umich.edu{ 3567720Sgblack@eecs.umich.edu PCState pc = context->pcState(); 3572292SN/A PCState bpc; 3582292SN/A bool set_bt = false; 3592292SN/A 3602292SN/A // User was stopped at pc, e.g. the instruction at pc was not 3612292SN/A // executed. 3622292SN/A MachInst inst = read<MachInst>(pc.pc()); 3632292SN/A StaticInstPtr si = context->getDecoderPtr()->decode(inst, pc.pc()); 3642292SN/A if (si->hasBranchTarget(pc, context, bpc)) { 3652292SN/A // Don't bother setting a breakpoint on the taken branch if it 3662292SN/A // is the same as the next pc 3672292SN/A if (bpc.pc() != pc.npc()) 3682292SN/A set_bt = true; 3692292SN/A } 3702292SN/A 3712292SN/A DPRINTF(GDBMisc, "setSingleStep bt_addr=%#x nt_addr=%#x\n", 3722292SN/A takenBkpt, notTakenBkpt); 3732292SN/A 3742292SN/A setTempBreakpoint(notTakenBkpt = pc.npc()); 3752292SN/A 3762292SN/A if (set_bt) 3772292SN/A setTempBreakpoint(takenBkpt = bpc.pc()); 3782292SN/A} 3792292SN/A 3802292SN/A// Write bytes to kernel address space for debugger. 3817720Sgblack@eecs.umich.edubool 3827720Sgblack@eecs.umich.eduRemoteGDB::write(Addr vaddr, size_t size, const char *data) 3832292SN/A{ 3842292SN/A return BaseRemoteGDB::write(vaddr, size, data); 3852292SN/A} 3862292SN/A 3872292SN/A